Realistic Storage of Pending Requests in Content-Centric Network Routers
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1 Realistic Storage of Pedig Requests i Cotet-Cetric Network Routers Wei You, Bertrad Mathieu, Patrick Truog, Jea-Fraçois Peltier Orage Labs Laio, Frace {wei.you, bertrad2.mathieu, patrick.truog, jeafracois.peltier}@orage.com Gwedal Simo Telecom Bretage Brest, Frace gwedal.simo@telecom-bretage.eu Abstract Cotet-Cetric Networkig (CCN) is a ovel etwork paradigm, which aims at movig from the traditioal hostto-host etwork model to a cliet-to-cotet oe. This shift brigs may beefits but also leads a big challege o the hardware techologies for implemetig CCN odes. For example the Pedig Iterest Table, oe critical compoet i a CCN ode, is ivolved i every CCN message forwardig process, ad eeds to be updated every time a packet comes i. The implemetatio of this table requires a memory that is fast for short access time ad also large eough for storig the pedig Iterests. Ufortuately today s memory techologies caot meet these requiremets with the curret hash-based architecture. After highlightig this limitatio, we preset a distributed PIT architecture which is based o the Bloom filter structure. The evaluatios validate that our solutio ca reduce the PIT table size ad support higher packet arrival rate. Our solutio allows to implemet this compoet o today s fast memory like SRAM. Therefore this proposal ca improve the cotet fetchig performace ad improve the quality of cotet delivered i CCN etwork. I. INTRODUCTION The host-to-host commuicatio paradigm that has ruled the Iteret for 4 years is ow challeged by ew usages: people care more about which cotet or iformatio they are really iterested i, ad less o where the iformatio is. Cotet-Cetric Networkig (CCN) [6] proposes a ew etworkig paradigm based o a cliet-to-cotet model. I CCN, the etworkig targets are o loger the idetified hosts, but the amed cotets. Each cotet object is idetified by a uique ame, which is idepedet from its locatio. This promisig etworkig approach requires however revisitig the architecture of routers, which are called CCN odes. A CCN ode has a exteded set of features. It has to deal with the Iterest packets that are emitted by the ed-users requestig a cotet. Sice the same cotet ca be requested by may users, CCN odes have a cache ability (compoet amed Cotet Store i CCN). If the cotet is ot cached, the Iterest packet is forwarded to all the potetial cotet holders. The cotet respose (a.k.a Data packet) is set back to all the cliets havig expressed iterest for this cotet. Thus, a CCN ode cotais a Pedig Iterest Table (PIT), which maitais the list of received Iterests ad a Forwardig Iformatio Base (FIB), which is used to forward the icomig Iterest packets. The FIB table is similar to the FIB table i a traditioal IP etwork but the PIT is a ew cocept. Techology Access time (s) Cost ($/MB) Max. size SRAM (o-chip) Mbits SRAM (off-chip) Mbits RLDRAM Gb DRAM GB TABLE I CURRENT MEMORY TECHNOLOGY [8] Today s hardware, especially memory chips, do ot eable the developmet of all features of CCN odes. If we look at memory techologies i Tab I, we observe that the chips with the shorter access time have small storage, while the chips that ca offer a larger space do ot have a fast access time. These limitatios, which were highlighted i [8], call for the developmet of ew techiques i order to fit ext-geeratio etworkig proposal ito today s memory techologies. I this paper we focus o the PIT table, which has ot received much research attetio so far. Previous works have maily focused o the Cotet Store [2, 7] or o memory architecture for efficiet FIB forwardig processes [5]. The PIT eeds to memorize every differet icomig Iterest, ad to remove the Iterest etry whe the associated cotet comes back. Sice almost every icomig message could lead to a update process i this table, the PIT should be built o a fast memory chip. O the other had, the PIT should have a large storig capacity because the legth of CCN cotet ame is at least as large as the legth of a IPv6 address We show i III that curret PIT implemetatio, which is based o a hash-table, caot fit with today s memory techologies. We preset i IV the ew PIT implemetatio that we have itroduced i [1]. This proposal is called DiPIT as it is based o a Distributed PIT table. I V, we aalyze the feasibility ad the scalability of DiPIT i terms of memory space cosumptio ad etworkig load aspect. Fially, we describe i VI the deploymet of DiPIT ito a hierarchical CCN etwork, the we make recommedatios for both the choice of a PIT implemetatio ad the memory techologies, based o the expected iterest rate i the etwork. II. PREAMBLE: MODELING PIT TABLE We provide i the followig a model for the CCN PIT table. We also itroduce the mai otatios that we used throughout this paper i Table II.
2 Parameters face λ i λ pit RT T CS hit τ iterest Nbr pitetry Meaig umber of iterfaces i the CCN ode Iterest packet arrival rate at the iterface i Iterest packet eterig rate to the PIT table average Data packet roud-trip time hit ratio of the Cotet Store ratio of Iterest packets for the same CotetName. It depeds o the traffic distributio umber of stored etries i the PIT table TABLE II CCN NODE MODELING PARAMETERS Cost i $ 6, 4, 2, hash= 24 bits hash= 32 bits hash= 64 bits average Iterest arrival rate i Mpcks storage limits Whe a Iterest arrives a CCN ode, it should first be checked i Cotet Store. This Iterest packet is the cosidered by the PIT table if o Data cached i the Cotet Store ca fulfill this request. Thus the Iterest eterig rate for the PIT is: λ pit = br λ i (1 CS hit ) The etries i PIT table are the cosumed by the Data packets, so the umber of etries is i average λ pit RT T. We also cosider redudat Iterest packet, thus we obtai that the actual umber of stored PIT etries is: Nbr pitetry = λ i (1 CS hit ) RT T τ iterest (1) III. ANALYSIS ON THE CENTRALIZED HASH TABLE The PIT table described i the semial CCN paper [6] is a cetralized hash table. This implemetatio is also chose by default i the ope-source release CCNx [1]. We aalyze i this Sectio the scalability of the hash-based CCN PIT table. I our evaluatio we cosider oly the two fastest memory techologies, the SRAM ad the RLDRAM. The SRAM could be built either o-chip or off-chip (Table I). The o-chip SRAM memory offers a faster access time however it is limited at 5 Mbits size. This size is too small for the PIT table, so SRAM refers to the off-chip SRAM i the rest of the paper. We highlight i Equatio (1) that the umber of PIT etries depeds o both CS hit ratio (CS hit ) ad traffic popularity distributio (τ iterest ). Both parameters do ot vary much for a give CCN ode, ad idepedet of the implemetatio desig of the PIT. To simplify the aalysis, we set CS hit = ad τ iterest = 1. A. Table size ad Cost Each etry i a hash table PIT cotais the key value of CotetName (of legth size key ) ad the icomig iterface idetifier iformatio (of legth size face id ). The estimated hash table size is the: Size hash = (size key + size face id ) λ i RT T (2) Cost i $ Fig. 1. Required SRAM memory cost vs. λ i access time limits Fig. 2. average Iterest arrival rate i Mpcks hash= 24 bits hash= 32 bits hash= 64 bits Required RLDRAM memory cost vs. λ i I our evaluatio, we suppose a router with face = 4 iterfaces. The parameter λ i rages from to 2 Millios of packets per secod (Mpcks). The average packet RTT is 8 ms as defied i [8]. I order to hash the cotet ames, we use three differet hash values: 24 bits, 32 bits ad 64 bits. I Figure 1 ad Figure 2 we preset the cost of implemetig a hash-based cetralized PIT table o a SRAM memory or o a RLDRAM memory, respectively. We ca see that i Figure 1, all the three curves stop at cost = $6,75, which refers to the maximum size of SRAM (25 MBytes). We highlight here that a SRAM is fast eough for the processig of packets, but it caot store the etries for high Iterest arrival rate. Eve for short hash value like 24 bits, the SRAM ca oly support up to 15 Mpcks packet arrival rate. The three curves i Figure 2 stop at λ = 66 Mpcks sice the RLDRAM caot process more packets per secod. If the size is o more a problem, RLDRAM is too slow for most CCN odes. To summarize this first evaluatio, oly SRAM with hash values lower to 32 bits ca meet both packet arrival rate ad memory size requiremets of a high-level CCN ode. B. Collisio ratio Short hash value legth eables the implemetatio of PIT with large storage of Iterests. But the shorter is the hash value legth, the more probable are collisios. A collisio i hash table occurs whe distict elemets are coded at the same etry of a hash table. The elemets that suffer from a collisio are stored i a liked list at the same hash etry, therefore a collisio does ot cause packet loss (except if the
3 1.8 Collisio ratio.6.4 hash= 16 bits.2 hash= 24 bits hash= 32 bits Fig. 3. average Iterest arrival rate i Mpcks Predicted collisio ratio of SRAM i fuctio of λ i memory is full), but iformatio retrieval is much loger. Here we evaluate the collisio rate for differet hash value legths. br i 2 size key, br Collisio = i > 2 size key br i br i 2 size key where br i = λ i RT T (3) We the evaluate the collisio ratio for hash value legths 16 bits, 24 bits ad 32 bits (sice we observed that higher values are ot possible). I Figure 3, both 16 bits ad 24 bits experiece collisios for small Iterest arrival rate. Moreover collisio ratios quickly reach their maximum level. Oly the 32 bits hash values preset low collisio rate util 2 Mpcks. C. Discussio Through both evaluatios i III-A ad III-B we observe that the selectio of the memory techology depeds o the packet arrival rate. For example, a RLDRAM with a 32 bits (or more) hash value ca support a edge router with a low packet arrival rate (e.g. less tha 66 Mpcks). However, for a bigger router (e.g., a core etwork router), the packet rate is geerally higher tha 66 Mpcks ad a SRAM with a 32 bits hash value is the oly optio. If the rate is higher tha 13 Mpcks, the hash table implemetatio has some critical limitatios because either SRAM or RLDRAM ca support both memory ad access time requiremets. Alterative solutios should be desiged. IV. DIPIT: A DISTRIBUTED BLOOM FILTER BASED PIT Sice access time of off-chip SRAM is ot the bottleeck, the key issue is the reductio of the table size. I a recet paper [1], we proposed a distributed CCN PIT table system, amely DiPIT. I this paper, we cosider DiPIT as a alterative PIT implemetatio. We give a brief descriptio of DiPIT hereafter. More details ca be foud i [1]. I DiPIT, the sigle cetralized PIT table is distributed o each router iterface. The distributed small PIT table associated to each iterface is amed a PITi. Each PITi is costructed with a coutig Bloom filter. Oe PITi is i charge Fig. 4. Duplicated Iterest comig through differet iterfaces of the icomig Iterest messages ad Data messages oly through the iterface it is related to. Whe a Iterest message arrives o a iterface, the message is checked i the related PITi. If there is already a etry for this Iterest, this packet is ot forwarded upstream. Otherwise, the Iterest message is coded i the coutig Bloom filter, ad forwarded upstream accordig to the FIB table. A icomig Data packet is checked with all PITi tables. The Data is forwarded through ay iterface whose PITi returs a positive verificatio result. The related footprits are the deleted from the coutig Bloom filters. The Bloom filter ca itroduce false positives. The false positive ratio ca be calculated as : fp = (1 e k m ) k where is the umber of iserted elemets, k the umber of hash fuctios, ad m the legth of the vector. I our case, is the product of the packet rate λ ad the RT T. I the desig of CCN, if oe ode receives multiple Iterests o the same cotet, oly the first oe is forwarded. Our DiPIT architecture ca avoid sedig the duplicated Iterest comig through the same iterface, but ot for those comig from other iterfaces, because every PITi is idepedet from each other. This leads to a extra etworkig load. However, such evet ca oly occur whe two Iterest packets arrive o distict iterfaces i a time frame of RTT (otherwise the secod Iterest packet would fid the Data i the Cotet Store). We aalyse ow this potetial limitatios. Let us suppose the worst case, i.e. several iterfaces receivig the same Iterest withi a Data roud-trip time. No matter how may iterfaces of the CCN ode receive ad forward the same Iterest, the impact o the whole etwork is oly withi oe hop. The case is illustrated i Figure 4. The arrows deote Iterest packet propagatio. Node A receives the same Iterest several times from its differet iterfaces. Accordig to its FIB table, all these Iterests will be forwarded to ode B. For ode B, all these Iterests come from the lik betwee B ad A via the same iterface. Thus oly the first icomig Iterest is further forwarded to the ext hop C. The other Iterests are blocked by the PITi tables because they arise a positive matchig i the Bloom filter. V. EVALUATIONS OF THE DISTRIBUTED PIT We ow evaluate the cost ad performace aspects of DiPIT. We also evaluate whether DiPIT with acceptable false positive ratio ca allow the SRAM techologies to meet both memory ad access time requiremets. This aalysis has ot bee preseted i [1]. (4)
4 Cost i $ fp= 1% fp= 1% fp=.1% fp=.1% fp=.1% hash= 32bits average Iterest arrival rate i Mpcks memory space i MBytes (log 1 ) PITi k = PITi k = 7 PITi k = 11 hash 32bits probability of false positives (log 1 ) Fig. 5. PITi Required memory size vs. λ i Fig. 6. Required memory size vs. false positive A. Table size ad cost The DiPIT table size depeds o the legth of the Bloom filter ad the umber of iterfaces face. The legth of a Bloom filter m ca be calculated from the acceptable false positive fp, the umber of applied hash fuctios k, ad the umber of iserted elemets. From Equatio (4), we have k m = log(1 fp 1 k ) Each required memory size for a coutig Bloom filter is the product of the vector legth ad the couter size. We deote the couter size as Couter. Thus the estimated memory size of the etire DiPIT system is: Size = Couter λ i RT T k log(1 fp k ) To evaluate the performace of DiPIT, we cosider the followig settigs. We use SRAM because RDLRAM does ot support high packet arrival rate. Agai λ i rages from to 2, RT T = 8 ms, ad the CCN ode has four iterfaces. We give 2 bits for each couter. Sice today s Iteret services ted to tolerate a packet loss rate of 1% at least, we thus set our acceptable false positive i the rage from.1% (which is actually very low) to 1%. I most previous works, the acceptable false positive probability is comprised betwee.1% ad 1% [3, 4, 9, 11]. I Figure 5, we preset the cost for DiPIT ad differet acceptable false positive parameters. To ease the compariso to hash-table based solutios, we also show the cost for a hash table with 32 bits hash value (the oly oe that is acceptable accordig to our aalyse). Out of all DiPIT solutios, the oly oe that a bigger cost is whe the acceptable false positive rate is.1%. Moreover, DiPIT ca tolerate larger packet arrival rates. The DiPIT solutio ca overcome the SRAM memory space limitatio because the whole PIT table is ow distributed to each iterface ad each PITi table ca be idepedetly built o a SRAM chip. Thus eve if the size of the overall PIT is above the 25 MBytes limitatio, the size of each PITi is smaller tha the maximum memory size. (5) B. Table size ad false positive The acceptable false positive ratio is a key parameter of the DiPIT system because the memory size derives from the false positive ratio i Equatio (5). I the evaluatio we aalyse the impact of false positive o the table size. We fix the average Iterest arrival rate at 1 Mpcks ad the Data RTT as 8 ms. I Figure 6 the variable k is the umber of hash fuctios used i DiPIT. The required memory space is calculated accordig to differet false positive ad hash fuctios umber. We ca see that the 32 bits hash table overcomes the DiPIT whe the acceptable false positive is lesser tha.3% (k = 5, 3.5 o the x-axis) or.3% (k = 11, 4.5 o the x-axis). C. Extra Data traffic load Because a PITi produces a false positive, some Data might be set out although o Iterest matches. Here we aalyse the geerated extra etworkig load. Let us suppose a CCN ode with face iterfaces receives br data. We deote by fp j i the false positive ratio of the iterface i at the ode j. We set N hop as the umber of times the false Data ca be forwarded. The sum of the false Data packets that are set out by oe ode impacts the N hop etworkig lik such as: Number data = N hop (br data j=1 1=1 fp j i ) (6) We fix the average Data arrival rate at 1 Mpcks ad the Data RTT as 8 ms. The acceptable false positive is 1%,.1% ad.1%. From Figure 7 we ca see that after the secod hop, the extra traffic is early zero. I fact, oe ode ca geerate some extra Data packets but this extra traffic is stopped at the ext hops because the probability several (eve oly 2) odes produce the same mistake is very low. D. Discussio These three evaluatios prove that the DiPIT ca overcome the limitatios of fast memory chips. Whe the packet arrival rate exceeds 13 Mpcks, oly the distributed system ca allow SRAM techologies to be used for PIT. The trade-off is the false positive. DiPIT is especially the solutio for high-level etworkig routers (like a core router or the peerig router) that have a higher packet arrival rate. Ad sice DiPIT requires
5 umber of extra Data packets fp= 1% fp=.1% fp=.1% Fig umber of hops Extra Data packet load decreased durig propagatig Fig. 8. A hierarchical etworkig topology less memory tha a hash table, DiPIT ca also be cosidered for CCN odes with smaller packet rate arrival (if this ode is ot too sesitive to false positive effects). I Bloom-filter based PIT system more hash fuctios ca reduce the filter size (Figure 6). If we seek a faster performace ad we are less sesitive to the cost, we ca use less hash fuctios (as k = 3 or 5) ad larger filter i order to reach a targeted acceptable false positive. O the cotrary, if we wat to limit the cost, we ca implemet more hash fuctios (as k = 7 or 11) i order to reduce the memory space. VI. CASE STUDY: HIERARCHICAL NETWORK We ow preset a case study o a hierarchical etwork. We especially idetify the coditios uder which a traditioal hash table ca be implemeted ad we show that DiPIT ca sigificatly expad the applicability of CCN i etworks with today s memory techologies. distributed PIT size for a edge server is: Size 1 = 2 4 (1 CS 1 ) τ iterest λ i 1 6 (2 d + D) 1 3 k 1 log(1 fp k1 1 ) The core router I receives the Iterest packets from four edge routers, so it has a higher iput packet rate (whe the Cotet Store has a realistic hit ratio). The Iterest arrival rate at each iterface is equal to the Iterest leavig rate at the edge router up-streamig iterface. Thus the overall distributed PIT size for the core router is: Size I = 2 4 (1 CS 1 ) (1 CS I )(τ iterest ) 2 λ i 1 6 (d + D) 1 3 k I log(1 fp k I I ) We ca similarly derive the overall DiPIT size for the root as: (7) (8) A. Aalysis We cosider a three level hierarchical topology, illustrated i Figure 8. We deote the peerig router as root. The root is coected with four core routers, which are deoted as I, II, III ad IV. Each core router is coected to four edge routers, oted as 1, 2, 3, 4. The set of ed-users which is coected to a edge router is oted as A, B,..., E. Each set of ed-users geerates Iterest packets with λ i Mpcks. Each iteral lik has a d ms delay. The root has D ms delay with outside etwork. The acceptable false positive for the root, the core router ad the edge routers are deoted fp root, fp I, ad fp 1 respectively. The umber of hash fuctios for the Bloom filter are k root, k I ad k 1 respectively. The Cotet Store hit ratio for each level router is CS root, CS I ad CS 1 respectively. The ratio of idetical Iterest packets amog the traffic is τ iterest %. The edge router 1 receives the Iterest messages from four iterfaces at a rate λ i Mpcks. The RTT for each iterface is 2 d + D ms. We suppose that τ iterest are idetical for the traffic of every iterface ad every router. Thus the overall Size root = 2 4 (1 CS 1 ) (1 CS I ) (1 CS root ) B. Settigs (τ iterest ) 3 λ i 1 6 D 1 3 k root log(1 fp kroot root ) We ow build the evaluatio system. We cosider that edge router receives Iterest packets from four set of termials at rate 1 Mpcks ad τ iterest % = 95%. The trasmissio time o each iteral lik is 2 ms, so RT T is smaller or equal to 8 ms. We do ot cosider Cotet Store cachig because our mai motivatio is to idetify the right techologies for PIT, so the impact of CS hit = is idetical o every techology. Sice we showed that false positive has ot a sigificat impact o the whole etwork, we set a relatively high acceptable false positive ratio for the root router (1%) while we use.1% for the edge ad core routers. Fially, we used 7 hash fuctios for the edge routers, because the packet rate is ot high. O the cotrary, core routers ad root routers eed faster performace, thus we use 5 ad 3 hash fuctio for them, respectively. (9)
6 λ i edge routers core routers root routers is the oly optio util λ i = 14 Mpcks. Recommedatios for core ad root routershave to be read the same way. Figure 9 highlights the mai cotributio of this paper: we provide a way to let a operator make choices for the deploymet of a CCN etwork. Cosider for example a operator with icomig traffic at 15 Mpcks, ad the requiremet to limit the false positive for the edge, core routers, ad root router at.2%,.2%, ad.2% respectively. The right choice for the edge routers is DiPIT+RLDRAM, for the core routers is Hash+RLDRAM ad for the root router is DiPIT+SRAM Fig. 9. fp.1% fp.3% fp.15% fp.1% fp.3% fp.15% Hash RLDRAM Hash SRAM DiPIT RLDRAM DiPIT SRAM Summary of the best choices for PIT table, accordig to the cost VII. CONCLUSION The CCN paradigm ca brig may beefits to Iteret evolutio. However today s memory techologies are ot ready to support this iovatio i term of memory space ad access time, especially for the PIT table. I this paper we aalysed the feasibility ad the scalability of the hash table. We also aalyzed the DiPIT system, which aims at beig implemeted i smaller so faster memory chips. Each techique has its advatage. The hash table presets some limitatios at the table size ad the performace speed aspects but it does ot produce ay extra etwork load. The DiPIT system requires less memory space ad eables implemetatios o fast memory chips, so it ca hadle higher packet arrival rate. However DiPIT itroduces some extra etwork load because Bloom Filter ca experiece some false positive. Differet etworkig coditios call for differet approaches. We also showed that mixig differet memory chip techologies is possible. I future works, we will deploy modified versio of CCNx o a large testbeds for further aalysis. We also cosider the study of a distributed table for FIB ad Cotet Store. Our goal is to make sure that CCN protocols ca be implemeted i off-the-shelf routers. ACKNOWLEDGMENT This work is partially fuded by the Frech Natioal Research Agecy (ANR), CONNECT project. C. Discussio We ow summarize how to choose the PIT architecture (traditioal hash table or DiPIT) ad the cheapest memory techology for the routers at differet levels. See Figure 9. I short, all gree blocks correspod to cofiguratios where DiPIT allows a implemetatio of PIT table i today s memory techologies although it is impossible to make it with traditioal hash tables (the blue blocks). We ow explai how to read Figuree 9. We take the edge router as a example. If we ca accept a false positive ratio that is larger tha.1% (right colum), DiPIT is always cheaper tha cetralized hash tables. Ad if the λ i is smaller tha 66 Mpcks (calculated with fp =.1%), it is better to implemet with RLDRAM because it is cheaper. If we are sesitive to the false positive (fp <.1%), the hash table is a better solutio. However whe the λ i exceeds 86 Mpcks, the hash table ca o more be used. The DiPIT with SRAM REFERENCES [1] Project CCNx. [2] S. Ariafar, P. Nikader, ad J. Ott. O cotet-cetric router desig ad implicatios. I ACM CoNext Workshop ReARCH, 21. [3] A. Broder ad M. Mitzemacher. Network applicatios of bloom filters: A survey. Iteret Mathematics, 1(4):485 59, 24. [4] D. Guo, J. Wu, H. Che, ad X. Luo. Theory ad etwork applicatios of dyamic bloom filters. I IEEE INFOCOM, 26. [5] H. Hwag, S. Ata, ad M. Murata. Realizatio of ame lookup table i routers towards cotet-cetric etworks. I Proc. of CNSM, 211. [6] V. Jacobso, D. Smetters, J. Thorto, M. Plass, N. Briggs, ad R. Brayard. Networkig amed cotet. I ACM CoNEXT, 29. [7] L. Muscariello, G. Carofiglio, ad M. Gallo. Badwidth ad storage sharig performace i iformatio cetric etworkig. I Proc. of the ACM SIGCOMM workshop ICN, 211. [8] D. Perio ad M. Varvello. A reality check for cotet cotric etworkig. I ACM Sigcomm Workshop ICN, 211. [9] Y. Qiao, T. Li, ad S. Che. Oe memory access bloom filters ad their geeralizatio. I IEEE INFOCOM, 211. [1] W. You, B. Mathieu, P. Truog, J.-F. Peltier, ad G. Simo. DiPIT: a distributed Bloom-Filter based PIT table for CCN odes. I ICCCN (to apear), 212. [11] M. Yu, A. Fabrikat, ad J. Rexford. Buffalo: bloom filter forwardig architecture for large orgaizatios. I ACM CoNEXT, 29.
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