Exploring System Coherency and Maximizing Performance of Mobile Memory Systems

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1 Exploring System Coherency and Maximizing Performance of Mobile Memory Systems Shanghai: William Orme, Strategic Marketing Manager of SSG Beijing & Shenzhen: Mayank Sharma, Product Manager of SSG ARM Tech Symposia China 2015 November 2015

2 Memory Requirements for Next-Gen Mobile Devices The rise of rich and complex mobile content High performance tablets and hybrids replacing laptop purchases 4K content adoption HDR cameras 120fps+ video for super slow motion playback System memory bandwidths must stay ahead of demand Responsiveness is key to user experience, everything happens at the click of the screen 25GB/s 34GB/s 50GB/s LPDDR2 LPDDR3 LPDDR4 2

3 Heterogeneous Compute Accelerates Image & Vision Fully coherent memory systems can unleash heterogeneous computing Shared virtual memory and APIs like OpenCL 2.0 and HSA offer a simplified programmers model Example use cases: Mobile Computational photography Moving and still image real-time stabilization Deep learning Augmented reality DTV/STB Gesture controlled UIs Super resolution Automotive Lane detection Pedestrian, vehicle and collision detection Road sign recognition 3

4 Shared Virtual Memory Removes Overheads Software Coherency without Shared Virtual Memory (SVM) Software must manage cache maintenance and data copying CPU Clean and copy GPU Clean and copy Hardware I/O Coherency with coarse-grained SVM Same address space, CPU and GPU take turns CPU Clean and copy GPU CPU GPU CPU GPU Clean Remove copy and CPU cache clean Hardware Full Coherency with fine-grained SVM Same address space, fully parallel operation CPU GPU No cache maintenance 4

5 GPU Software Coherency in Today GPU compute de-noise acceleration Optimizing the GPU acceleration processing pipeline Fine-tuned interoperation between the CPU and GPU 2x performance increase by using GPU +2x Performance Source: 5

6 Hardware Coherency Benefit Industry Data Cloud Server Face Detection Algorithm Gaming Visualization Suffix Array Construction +2.5x Performance +5.8x Performance +7.5x Rendered FPS -2.5x Energy/Frame -5x Power Source: oct-2012v11-arm-techcon?qid=f573ad3e-3d9b-4bcb-bba7-8eea &v=qf1&b=&from_search=5 Source: Source: 6 Application examples on 3 rd party HSA hardware

7 Heterogeneous System Coherency ARM develops IP together with a system-level view to get the most out of silicon Cortex processors, Mali multimedia and CoreLink System IP are designed and validated together System-optimized IP enables greater SoC differentiation Reduced CPU latency Efficient utilization of interconnect and memory Quality of Service guarantees Fully coherent memory big.little TM and heterogeneous compute Faster design cycle CPU CPU Video Display GPU Highly optimized memory system CoreLink Interconnect CoreLink Controllers DRAM 7

8 Introducing CoreLink CCI-550 and DMC-500 Proven, Trusted and Widely Licensed System IP CoreLink CCI Family > 60 Licenses CoreLink DMC Family > 30 Licenses CoreLink Interconnect > 200 Licenses * Existing CoreLink CCI Family Licensees include 8

9 Premium Mobile with Fully Coherent GPU big.little processing CoreLink GIC-500 Cortex-A72 Cortex-A53 I/O Coherent Masters NIC-450 MMU-500 Mali Mimir Fully Coherent GPU Fully coherent GPU with 1 to 4 ACE with Shared Virtual Memory Mali- V550 Video Mali- DP550 Display CoreLink MMU-500 Snoop Filter CoreLink CCI-550 CoreLink NIC-450 Scalable from 1 to 6 ACE interfaces Peripherals 1 to 6 memory interfaces CoreLink DMC-500 CoreLink DMC-500 CoreLink DMC-500 CoreLink DMC-500 Memory System Integrated TrustZone 9 End to end Quality of Service LPDDR3/LPDDR4 DRAM

10 CoreLink CCI-550 Cache Coherent Interconnect More Bandwidth, Less Latency +60% peak bandwidth increase Quality-of-Service enhancements reduce latency by 20% Advanced Power Efficiency Integrated snoop filter can save 100 s of mw Fully coherent GPU simplifies software, increases performance Scalability 1 to 6 ACE interfaces and 1 to 6 memory interfaces Optimized solution for a wide range of applications including mobile, digital TV, automotive and costefficient networking applications 10

11 Improved Peak Memory System Bandwidth +60% Peak Interconnect Bandwidth CoreLink CCI-550 6x DMC CoreLink CCI-400 2x DMC CoreLink CCI-500 2x DMC CoreLink CCI-500 4x DMC CoreLink CCI-550 4x DMC Peak interconnect throughput, assumes same process technology and normalised dynamic memory controller (DMC) model. CoreLink CCI-550 includes CoreLink CCI-500 features and configuration space. 11 External 4K Display Higher Frame Rates Console Quality Gaming Responsive UI

12 Highly Configurable, Minimal Area, Many Applications CoreLink CCI Area Scales with Performance big LITTLE GPU 12 Tablet Premium Smartphone Low Cost Smartphone CoreLink CCI area measured from physical implementation trials >75% Interconnect Area Reduction Scalable for multiple performance points 1 to 6 ACE interfaces CoreLink CCI to 6 memory interfaces Fully configurable to minimize area and power Multiple applications: Lowest power mobile, digital TV, automotive infotainment, low cost networking

13 Integrated Snoop Filter Extends System Coherency ACE Fully Coherent ACE Fully Coherent ACE-Lite IO Coherent ACE Fully Coherent ACE Fully Coherent ACE Fully Coherent Snoop Filter CoreLink CCI-400 First Generation big.little All coherency snoops sent to all processors Two fully coherent processor clusters First released in 2011 and widely licensed CoreLink CCI-550 with Snoop Filter Snoop filter offers further scaling One central snoop instead of broadcast to many Lower snoop latency Ability to scale ACE masters without quadratic increase in snoops 13 Lower power and higher performance Removes the need to speculate to DRAM Extended processor frequency scaling, longer retention * Snoop filter first introduced with CoreLink CCI-500

14 CoreLink DMC-500 Dynamic Memory Controller Highly Optimized, efficient memory access 27% increase in memory bandwidth utilization Latest LPDDR4/3 memory support up to LPDDR Low power design and operating modes End to end quality of service 25% reduction in average CPU latency Complete solution with CoreLink interconnect Integrated solution TrustZone security and media protection for DRM content Supports industry standard DFI 4.0 PHY interface Integrated memory scheduling and memory controller enables highest utilisation 14

15 End to End Quality of Service Mechanisms Examples of traffic types: Latency Sensitive Best Effort CPU CPU GPU DMA Real Time Display Macro Regulation in Interconnect Programmable QoS Value (Qv) Dynamic Qv by regulation e.g. bandwidth Arbitration by priority Non-blocking: forward if Qv > QoSAccept CoreLink CCI-550 & NIC-450 QoS Value QoSAccept CoreLink DMC-500 DRAM Micro Regulation in Memory Controller QoSAccept increases as memory queue fills: reserve space for critical requests Real time traffic will time-out at maximum latency constraint Starvation avoidance 15

16 QoSAccept Demonstrates Lowest Latency Latency sensitive CPU with single outstanding transaction CPU CPU HB HB HB CoreLink CCI-550 & NIC-450 QoS Value Best effort masters request high bandwidth DRAM QoSAccept CoreLink DMC-500 CPU to DRAM round trip latency (mean) No QoS Priority Only QoSACCEPT 38% latency reduction Priority only may fill memory queue and back-pressure interconnect QoSAccept reserves memory queue for CPU traffic, removes blocking in interconnect Latency measured in system level RTL simulation with traffic generators 16

17 Highly Optimized Integrated Solution ARM IP Portfolio Advanced IP Tooling Designed & Validated together ARM Mali CCI DMC Cortex 17

18 ARM CoreLink Interconnect Families Cortex-A7 GPU Radio Sensors CoreLinkTM NIC-400 IO GIC-500 I/O Coherent Masters NIC-450 Mali Cortex-A72 Cortex-A53 TM -T880 MMU-500 Snoop Filter CoreLink TM CCI-550 Mali- D550 Video NIC-450 Mali- V550 Display MMU-500 GIC-500 Cortex CPU Cortex CPU or CHI or CHI master master Cortex-A57 Cortex-A57 Cortex-A57 Cortex-A57 ACE Cortex CPU Cortex CPU or CHI or CHI master master Cortex-A53 Cortex-A53 Cortex-A53 Cortex-A53 CoreLink CCN-512 Cache Coherent Network 1-32MB L3 cache DSP DSP GbE PCIe PCIe DSP SATA DPI DPI Crypto USB AHB NIC-400 I/O Virtualisation CoreLink MMU-500 Snoop Filter Full SoC Connectivity 18 Peripherals DMC-400 CoreSightTM Debug & Trace CoreLink NIC Network Interconnect Lowest cost, lowest latency Connecting 100 s of devices Applications: All markets: from Single core IOT to rest of SoC connectivity with CCI & CCN Peripherals CoreSight TM Debug & Trace DMC -500 DMC -500 LPDDR3/LPDDR4 DRAM Highest Efficiency CoreLink CCI Memory System With Integrated TrustZone Cache Coherent Interconnect Enables big.little processing Highly scalable, minimize area Applications: Mobile, STB, DTV, automotive IVI, low cost networking Memory Controller DMC-520 x72 DDR Memory Controller DMC-520 x72 DDR Memory Controller DMC-520 x72 DDR Memory Controller DMC-520 x72 DDR Highest Performance CoreLink CCN Network Interconnect NIC-400 Cache Coherent Network First AMBA 5 CHI interconnect High frequency, up to CPU speed Integrated system cache Applications: Infrastructure networking and servers, HPC Over 100 licensees of ARM interconnect products DMC -500 DMC -500 Flash SRAM Network Interconnect NIC-400 GPIO PCIe

19 Summary System coherency continues to evolve from multi-cluster to heterogeneous Enabled by fully coherent GPU and shared virtual memory ARM System IP enables partners to build better systems System tested, optimized and validated with ARM Cortex processors and ARM Mali multimedia CoreLink CCI-550 Cache Coherent Interconnect Acceleration through coherency CoreLink DMC-500 Dynamic Memory Controller Latest memory, maximum utilization and lowest latency 19

20 Thank You The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2015 ARM Limited

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