Evaluation of Parallel Processing Systems through Queuing Model
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1 ISSN Vkas Shnde, Internatonal Journal of Advanced Volume Trends 4, n Computer No.2, March Scence - and Aprl Engneerng, 205 4(2), March - Aprl 205, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng Avalable Onlne at Evaluaton of arallel rocessng Systems through Queung Model Vkas Shnde Department of Appled Mathematcs, Madhav Insttute of Technology & Scence, Gwalor-Inda ABSTRACT In ths nvestgaton, Jackson queueng network has been wdely used to model and analyze the performance of complex parallel systems. M/G/ queueng system s used to model a parallel processng system, whch s expandable n vertcal and horzontal manner. Determne a closed form soluton for the system performance metrcs, such as processor s watng tme, system processng power, etc. Keywords: Queueng Network, Massve arallel rocessng, Shared Memory, Watng Tme.. INTRODUCTION arallel processng of the computer systems has been wdely studed due to a sgnfcant role n day-by-day fast computng of the jobs. As parallel computng systems prolferate the need for effectve performance evaluaton, queueng technques become ever more mportant. In fact, the performance of such systems depends on the hardware resources, (CU, Memory, etc.,) on software (system programs, complers, etc.,) and on the organzaton and management of these resources. In vew of the ncreasng complexty of computng systems, t s more and more dffcult to predct ther performance ndces based on analytcal queueng models. In such models, t s convenent to represent the resources as servers and the programs as customers. A model of parallel processng system s a system whch s expandable n vertcal and horzontal manner and can be treated as cluster for a sngle queue of watng jobs. A job s modeled as a sequence of ndependent stages whch must be processed, where the number of processors desred by the jobs n each stage may be dfferent. If, for some stage, the job n servce requres fewer processors than the system provdes, then the job wll occupy the processors accordng to ts need and the other processors wll be dle for that stage. If, for some other stage, the job n servce requres more processors than the system provdes, then t wll use all the processors n the system for an extended perod of tme such that the total work served n that stage s conserved. Many researchers have extensvely nvestgated processng systems va queue theoretc approaches. Al-Saqab et al. [] establshed a dstrbuted schedulng algorthm that wll track the avalable workstatons.e the workstatons not beng used by ther owners n networks and act upon those workstatons by schedulng processes of parallel applcatons onto them. Guan and Cheung [2] constructed a massvely parallel processng system whch has drawn a lot of attenton to an mportant feature affectng the performance and characterstcs of the archtecture wth an nterconnecton of multple processors. 36
2 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, Jean-Mare et al. [5] ntroduced a hybrd analytcal approach by usng technques from the theores of both stochastc task graphs and queueng networks. Jozwak and Jan [6] dscussed qualty drven model based mult processor accelerator desgn method that adequately addresses the archtecture desgn ssues of hardware mult processors for the modern hghly demandng embedded applcatons. Jan [7] studed communcaton archtectures for massvely parallel hardware mult processors. Systematc framework and a correspondng methodology for workload modelng of parallel systems was proposed by Kotss [8]. Mohapatra et al. [0] proposed the structure for processors whch s dvded nto groups or cluster and organzed n several stages. Maheshwar and Shen [] establshed a clusterng algorthm wheren all the clusters have balanced amount of computaton load and there s only one communcaton path between any par of clusters. Nassar [2] evaluated the throughput of several mult buses as a dscrete tme Markov chan under dfferent workng condtons. Rejns [3] consdered the delay effect caused by memory nterference n a parallel processng system wth shared memory was mplemented usng a machne repar queueng. Tomc [4] gave the matrx representaton of the lnear evoluton operator of the certan class of parallel processng system and effectvely used as a performance predcton tool for the modern parallel processng systems. Wasserman et al. [5] studed the problem of dynamc allocaton of the resources of a general parallel processng system comprsed of several heterogeneous processors. The rest of paper s organzed as follows. Model descrpton s gven n secton 2. In secton 3, descrbed the governng equaton and ther performance analyss. Concluson s mentoned n secton MODEL DESCRITION Every computer conssts of a set of processors (CUs), 2, 3, n and m 0 shared memory unts M, M 2, M 3,..M m whch communcate va an nterconnecton network N, as llustrated n fgure. The memory unts consttute a global man memory that provdes a convenent message depostory for processor-toprocessor communcaton. A system wth ths arrangement s called a shared memory computer. A global shared memory can be a serous bottleneck, partcularly when the processors share large amounts of nformaton, snce normally only one processor can access a gven memory module at a tme. If the processors have ther own local memores, then the global memory can be reduced n sze, or even elmnated completely. To separate the functons of processng and memory, whch refer to a CU wth no assocated man memory, but wth other temporary storage unts such as regster fles and caches as a processng element (E). 37
3 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, E E 2 E 3 E n Interconnecton network N Memory M Fgure : Shared Memory The basc cluster shown n fgure 2, each processng unt has a local memory for ts own computaton and there s a shared memory for facltatng the communcaton between the processors. A horzontal communcaton network (HCN) s used for transmttng data between processors and shared memory. Moreover the basc cluster ncludes a unt for I/O operatons and a unt for supervsory and managng the processors. A vertcal communcaton network (VCN) s used for transmttng control sgnals and vertcal expanson of the system. The basc cluster s defned n two ways: () by ncreasng the number of the processng unts or usng several basc clusters wth one addtonal memory that s shared by those clusters, and () n a two stage system, t must be noted that n the second level of the system, there s a HCN that connects the VCN of each basc cluster to SM 2. The unts that are located nsde the basc clusters are ndcated by (SM, HCN,.), and the unts that are located outsde of the cluster are ndcated by (SM 2, HCN 2, ) SM Horzontal Communcaton Network LM LM 2 LM N 2 N I/O Manager Vertcal Communcaton Network Fgure 2: Basc Cluster 38
4 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, SM2 Horzontal Communcaton Network 2 SM HCN Cluster 2 I/ O Manager VCN Vertcal Communcaton Network 2 Fgure 3: Two Stage System Ths method can expand the system vertcally and constructng s-stages system. A cluster n th stage of the s-stages system s depcted n fgure 4. Here cluster nclude some processng clusters or C namely, one I/O cluster and one managng cluster. There are two nterconnecton networks, HCN and VCN that transmttng data nsde and outsde of the clusters respectvely. Such systems can be expanded vertcally by ncreasng the number of stages or horzontally by ncreasng the number of Cs n each level. In multstage clusterng structure based system, f there are number of Cs that make a cluster wll be equal for all clusters of th stage, the system s known as homogenous at level. If system s homogenous n all level t wll be called homogenous on the other hand f t wll not be homogenous at least n one stage, t wll be recognzed as non homogenous or heterogeneous. 39
5 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, SM Horzontal Communcaton Network C - C - I/OC - MC - Vertcal Communcaton Network Vertcal Expanson ath Horzontal Expanson ath Fgure 4: Cluster n th stage of s stage system 3. THE ERFORMANCE ANALYSIS For evaluatng the performance of the system, let consder the system s constructed based on homogenous MSCS. In ths system any processor performs a pece of the man program that s called processor s job. Durng the job executon, t s probable that a job needs to communcate wth the other jobs. Therefore several queues can be constructed for each nterconnecton networks and shared memores. Consder the followng assumptons for analyzng the system. C s the number of C S n th stage of system and C o s the number of processors n each basc cluster. rocessors tself generated the nter job communcaton requests. The tme between two consecutve requests have exponentally dstrbuted wth parameter λ. Access tme to memory n th stage has exponentally dstrbuted wth parameter µ m. The destnaton of each request wll be unformly dstrbuted between processor s 40
6 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, jobs and the probablty of outgong request from th stage s denoted by. The servce tme of the nter connecton networks n th stage have exponentally dstrbuted wth parameter µ h and µ v for HCN and VCN, respectvely. Conflct over memory modules and nterconnecton networks wll be resolved by the queueng center whch s modeled as M/G/. Request processors must be wated untl they offer servce as per above scheme and durng watng perod, they can not generate any other request. The parallel processng system n whch the nput rate of each stage must be computed and queueng problem s analyzed by developng the M/G/ model. For analyzng the desgn of M s wth a large number of unts, the area of computaton for closed queueng network wll be very large. Apply queueng network methodology for analyzng the closed queueng network and also determne the nput rate of each servce center as a functon of the nput rate for prevous center. Ths technque can reduce the calculaton and smulaton tme. As shown n the fgure 5, all the request departs from HCN wll pass through the SM wth probablty one. Therefore, compute nput request rate of VCN s and HCN s. The processor requests wll be drected to servce center HCN and VCN by probablty (- ) and, respectvely. If the request rate of a processor wll be λ, the nput rate of HCN and VCN that orgnated from that process wll be λ (- ) and λ. h ROC HCN SM m h2 v VCN 2 HCN 2 SM 2 m2 VCN 2 HCN 3 Fgure 5: Mult stage Cluster M s wth s stage system Snce there are (C 0 -) processors n each basc cluster, the requests that receve to HCN and VCN orgnatng from other processor n the same cluster, ndcated by γ h and γ v, wll be λ(- )(C 0 -) and λ (C 0 -), respectvely. So the total requests of the processors that receved to servce centers n the frst SM 3 stage can be computed by followng equatons: 2 h3 v m3 From VCN s-2 To VCN3 - s - VCN S- hs vs HCN S SM s ms 4
7 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, m C 0 v ( C 0 ) C h 0 ( ) ( ) ( C 0 () )( ) (2) The nput request rate at the th stage from each Cs s λ (v-) steps wll be neglgble. After calculatng the effectve request rate, the watng tme can be determne by Lttle formula as 2 2 L L W or W 2( ) s 2( ) 2 s (8) C v m h v() ( ) (C ( ) v( ) ) v( ) ( C v() C (3) ) ( ) (4) v( ) In the last stage there s no request for outer cluster, so that C ms s hs v( s v() vs 0 (5) processor for each communcaton request, (5) whch can determne the processor utlzaton as by usng: Cs ( s ) v( s) Cs s v( s) (6) rocessor Utlzaton = U = ) 2( ) 2 2 w 2 s Now consder M/G/ model to calculate the () queue length at each mode for all stages, then the average of total wated processors n the system can be computed as. By usng ollaczek-khntchne formula, t gve T = N x U x S = s s 2( ) S L (7) C (7) (2) 2 2 2( ) 2 s 0 The wated processors would not be able to generate the request. In ths stuaton the effectve processor s request rate would be lower than the requred. The effectve request rate wll be decreased wth the same rato as there are actve processor s n the system. L and λ have been calculated successvely tll ther changes n two consecutve Here,, v, m h a processor request to are the probabltes that referred to VCN, SM & HCN respectvely and computed by the followng product type soluton m v j j0 (9) h ( ) j0 j (0) By determnng the average watng tme of a Total processng power of the system (T), s obtaned by consderng the sngle processor power (S). Thus 4. CONCLUSIONS In ths nvestgaton, the performance modelng of a parallel processng system as a sequence of stages, each of whch requres a certan ntegral number of processors for a certan ntegral of tme. Ths proposed a new structure and 42
8 Vkas Shnde, Internatonal Journal of Advanced Trends n Computer Scence and Engneerng, 4(2), March - Aprl 205, developed an analytcal model for massve parallel processng system based on queueng theory. The system performance metrcs may provde nsghts to the system desgners and decson makers to mprove the system at optmal cost. REFERENCES. Al-Saqab, K., Sarwar, S. and Saleh, K.: Dstrbuted gang schedulng n networks of heterogeneous workstatons, J. Computer Communcatons, Vol. 20, No. 5, pp (997) 2. Guan, H. and Cheung, To-Yat. : Effcent approaches for constructng a massvely parallel processng system, J. of systems Archtecture, Vol. 46, No. 3, pp (2000) 3. Hayes, J.. : Computer Archtecture and organzaton, McGraw-Hll. (998) 4. Hwang, K. H. and Xu,.Z.: Scalable parallel computng, McGraw-Hll (998) 5. Jean-Mare, A., Lefebvre-Barbaroux, S. and Lu, Z.: An analytcal approach to the performance evaluaton of master-slave computatonal models, J. arallel Computng, Vol. 24, No. 5-6, pp (998) 6. Jozwak, L., Jan, Y.: Desgn of massvely parallel hardware mult-processors for hghly demandng embedded applcatons, J of Mcroprocessors and Mcrosystems, Vol. 37, pp (203) 7. Jan, Y. and Jozwak, L. : Scalable communcaton archtectures for massvely parallel hardware mult processors, J of arallel Dstrbuton Computng, Vol. 72, pp (202) 8. Kotss, G.: A systematc approach for workload modelng for parallel processng systems, J. arallel computng, Vol. 22, No. 3, pp (997) 9. Kelenrock, L.: Queueng Systems, Vol. II, Computer Applcaton, New York Wely. (975) 0. Mohapatra,., Das, C. R. and Feng, T. Y.: erformance analyss of cluster based multprocessor, IEEE Trans. on Computer, Vol. 43, pp (994). Maheshwar,. and Shen, H.: An effcent clusterng algorthm for parttonng parallel programs, J. arallel Computng, Vol. 24, No. 5-6, pp (998) 2. Nassar, H.: A Markov model for multbus multprocessor systems under asynchronous operaton, J. Informaton rocessng Letters, Vol. 54, No., pp. -6. (995) 3. Rejns, G. L. and Gemund, Van. J. C.: Analyss of a shared- memory multprocessor va a novel queueng model, J of system Archtecture, Vol. 45, No. 4, pp (999) 4. Tomc, D.: Spectral performance evaluaton of parallel processng systems, J. arallel computng, Vol. 3, No., pp (2002) 5. Wasserman, K. M., Mchalds G. and Bambos, N.: Optmal processor allocaton to dfferentated job flows, J. erformance Evaluaton, Vol. 63, No., pp. -4. (2006) 43
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