Big Buffer of Switch

Transcription

1 Big Buffer of Switch

2 Content Why Do We Need Big Buffer Arch of Switch Buffer How to Test Buffer 1

3 Why Do We Need Big Buffer When audience watch movies on the Internet, they are faced with the fact that the movies often suspends for seconds. If a big buffer is provided, audience will not sense what has happened. In Quality of Service (QoS) shaping, a big buffer can make traffic more even than a small buffer so that downstream devices can process traffic easily. In the data center environment, a big buffer can make data transfer faster and more smooth. Without a big buffer, packets are lost when traffic bursts, and mosaics appear on the image. Flow in STOR With a big buffer, packets are not lost when traffic bursts, and the image is clear and smooth. Flow out 2

4 Why Do We Need Big Buffer Fine-grained traffic management Level 1. Service-based CAR Level 2. VLAN-based CAR Three-class CAR: service + user + interface Level 3. Interface-based scheduling 3

5 Content 1 Why Do We Need Big Buffer 2 Arch of Switch Buffer 3 How to Test Buffer 4

6 Buffering Mechanism of a Common LPU Static Buffer A chip provides four types of interface: GE interface, 10GE interface, HG interface, and CPU interface. Static buffer is allocated on GE, 10GE, and HG interfaces using the same rules. This training document takes the GE interface as an example to introduce the static buffer allocation mechanism. There are eight queues (0-7) on a GE interface. The static buffer is allocated by queue which is the minimum unit. Each queue is allocated 24 cells, that is, approximately MB (24 x 128 bytes). The static buffer configured on the GE interface is the total of static buffer allocated on the eight queues, which is approximately MB (8 x MB). Different from the GE, 10GE, and HG interfaces, the CPU interface needs to process a certain number of important packets. Therefore, 72 cells (approximately MB) of static buffer are allocated to each queue on the CPU interface. The total static buffer for eight queues amounts to approximately MB. 5

7 Buffering Mechanism of a Common LPU Static Buffer Next, let's move on to calculation of the buffer allocated to the entire chip. This slide takes the dual-chip device for example. If the 24 interfaces on the front panel and interfaces on the rear card belong to the first chip. The 24 interfaces on the rear panel and four 10GE interfaces belong to the second chip. The two chips are connected using four HG interfaces. Assuming the rear cards on the first chip are two 8 x GE cards, interfaces on a chip are 24 fixed interfaces, 16 GE interfaces, four HG interfaces, and one CPU interface. The first chip has two rear cards, and each rear card has eight GE interfaces, so there are a total of 16 GE interfaces. Based on the calculation method in the preceding slide, the total static buffer is calculated using the formula: ( ) x 8 x 24 x x 72 x 128 = MB. 6

8 Buffering Mechanism of a Common LPU Dynamic Buffer Assuming the dynamic buffer threshold (DBT) of each interface is X, the available buffer is A (the difference between the total buffer and the total static buffer, namely, 4 MB MB = MB), and the parameter of the dynamic buffer is a, the rules for allocating buffer to the interface comply with the following formulas: X α (A - X), which indicates that the DBT must be smaller than the product of a and the available buffer. X α x A/(1 + α) To ensure that buffer is allocated to each interface when the interface is congested or blocked, set the value of a to 1. Then, a single interface's DBT is a half of A. If there are two interfaces, the following formulas must be complied with: X α (A - X -Y) X α (A - X -Y) X + Y 2α x A/(1 + 2α) X + Y 2A/3 As shown in these formulas, when the number of interfaces that occupy buffer increases, the available buffer gets closer to the actual value. 7

9 Buffering Mechanism of a Common LPU Dynamic Buffer The buffer space that is supported by current switches is 4 MB in total. Therefore, the dynamic buffer is MB (4 MB MB). Original Mode: The value of a is set to 1/16. The maximum of dynamic buffer that each interface can occupy is calculated using the formula: X = (1/16)/(1 + 1/16) x = MB. After the MMU value is increased, the value of a is set to 2. The maximum of dynamic buffer that each interface can occupy is calculated using the formula: X = 2/(1 + 2) x MB = 1.89 MB. In burst traffic buffering mode, the value of a is set to 8. The maximum of dynamic buffer that each interface can occupy is calculated using the formula: X = 4/(1 + 4) x MB = 2.27 MB. It is obvious that when the number of interfaces that occupy buffer becomes larger, the available buffer gets closer to the actual value. It can be seen from the preceding formulas that even in burst traffic buffering mode, a single interface's buffer is still small and cannot meet the requirement for a delay of less than 200 ms. 8

10 Methods of Implementing Big Buffer on Frame Switches Intelligent Buffer 10 Gbit/s Private Field 1.6 Mbit/s Public Field 9.9 Gbit/s External buffer capacity: The rate on the backplane is 4 x 12 Gbit/s. When traffic bursts, the backplane sends the traffic to one of the 48 GE interfaces. The other 47 GE interfaces need to buffer the rest of traffic. Switch reliability requires the buffering time be 200 ms and the buffer capacity be 9.4 GB. In addition, 10 Gbit/s external DDR3 modules meet the design requirement. That is, the external buffer supports the downstream buffering time of 200 ms on a single interface. Maximum buffering time of a single interface = Buffer capacity/interface rate 10 GB/1 Gbit/s = 10s To improve security of interface buffer, private fields need to be configured in data packets. Among 10 GB of traffic, the maximum private field of a single interface occupies 1.6 MB, and the public field occupies 9.9 GB. Therefore, the maximum buffering time of a single interface is approximately 9.9s. 9

11 Specifications for the LPUs with Big Buffer on Frame Switches 48GE optical big buffer Item Maximum power consumption MAC IP ARP ACL MPLS VPN Specifications 48GE electrical interface: 160 W 48GE optical interface: 185 W 128 kbit/s IPv4: 128 kbit/s, IPv6: 64 kbit/s 16 kbit/s Ingress: 38 kbit/s MPLS L2 VPN, MPLS L3 VPN 48GE electrical big buffer Super large buffer: 1.25 GB data buffer of a single interface with the buffering time of 200 ms, which prevents packet loss caused by traffic burst. 10

12 Content Why Do We Need Big Buffer Arch of Switch Buffer How to Test Buffer 11

13 Test Buffer DUT_1 Port-3 Port-1 Port-2 Tport-1 Tester Tport-2 Tport-3 1. Establish the test environment according to the preceding diagram. 2. Tport2 sends data flows to Tport1 with no packet loss. At the same time, Tport3 sends some packets to Tport1. 3. Stop transmitting all data flows at the same time. Compare the number of sent packets of Tport2 and Tport3 with the number of received packets of Tport1. 4. If received packets are more than packets, decrease the number of burst packets on Tport3 and repeat the second process until the number of sent packets is equal to that of received packets. 5. At that time, the burst traffic is buffered in the switch. The number of burst packets is set to m, and the packet size is set to n. buffer = m x n 12

14 Test Buffer For example, the Quality of Experience (QoE) line card test result is as follows: Each interface has 25 MB of buffer space, and the total slot buffer is 1.2 GB. 25 MB x 8/1 Gbit/s = 200 ms Each interface is enabled with a delay of 200 ms, so that the movie will not suspend for seconds. 13

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