CCIX: a new coherent multichip interconnect for accelerated use cases

Transcription

1 : a new coherent multichip interconnect for accelerated use cases Akira Shimizu Senior Manager, Operator relations Arm 2017 Arm Limited Arm 2017

2 Interconnects for different scale SoC interconnect. Connectivity for on-chip processor, accelerator, IO and memory elements Server node interconnect - scale-up. Simple multichip interconnect (typically PCIe) topology on a PCB motherboard with simple switches and expansion connectors Rack interconnect - scale-out. Scale-out capabilities with complex topologies connecting 1000 s of server nodes and storage elements 2

3 Key drivers for interconnect technology Decline of Moore s law forcing more heterogeneous compute. Big data analytics growing at 11.7% CAGR. 5G wireless applications requiring 10x more bandwidth, 10x lower latency by Increase in distributed data forcing more network intelligence at faster data rates (10GbE -> 100GbE -> 400GbE). Data bandwidth and sharing growth projected at 10x-50x increase vs. present PCIe by

4 TM cache coherent interconnect for accelerators New class of interconnect for accelerated applications. Mission of the Consortium is to develop and promote adoption of an industry standard specification to enable coherent interconnect technologies between general-purpose processors and acceleration devices for efficient heterogeneous computing. 4

5 Consortium Inc Promoters Formed January 2016, incorporated in February Complete ecosystem with 34 members and growing. Contributors Hardware specification available for design starts for member companies. pronounced: (c siks). Arteris, Inc. Guizhou Huaxintong Semiconductor Technology Co. Ltd. INVECAS INC Netronome Phytium Technology Co., Ltd. PLDA Shanghai Zhaoxin Semiconductor Co., Ltd. Silicon Laboratories Inc. SmartDV Technologies India Private Ltd. Adopters 5

6 Applications benefiting from 4G and 5G base station Data-center Search Embedded Computing High Performance (Super)Computing In memory database processing Intelligent network acceleration Machine / Deep Learning Mobile Edge Computing Video analytics 6

7 multichip connectivity High performance, low latency. defines 25GT/s (3x performance*) Examining 56GT/s (7x performance*) and beyond Accelerator Enabling low latency via light transaction layer Flexible, scalable interconnect topologies. Flexible point-to-point, daisy chained and switched topologies Seamless integration. Switch Smart Network Persistent Runs on existing PCIe transport layer and management stack Supports all major instruction set architectures (ISA) 7

8 System topology examples PCIe PCIe Accelerator Accel Accel PCIe Accel PCIe Accel Switch Accel Accel Accel Accel Accelerator Direct attached, daisy chain, mesh and switched topologies. 8

9 DMA Engines: The problem with traditional accelerators Operating System vendors are interested in the opportunity for workload-optimized accelerators. Traditional DMA approach is to provide a special (Linux) kernel driver for every unique accelerator. uires skilled kernel developers (a driver for each accelerator), failure mode is catastrophic (system crash/downtime) Operating Systems used tomorrow have already been deployed. Updates are 9-12 months apart. Drivers must be in upstream Linux before we support them, a year+ turnaround for every accelerator 'Trilby : DMA Engine driven FPGA based workload accelerator built by Jon Masters for research into the barriers to adoption in the Enterprise, uses traditional approach of kernel driver and Operating System hacks. 9

10 Coherent virtual memory eliminates data transfer overhead Non-coherent system without Shared Virtual (SVM) Software must manage cache maintenance and data copying Clean and copy data Accelerator Clean and copy data Clean and copy data Accelerator coherent system with Shared Virtual (SVM) Hardware managed cache maintenance, shared address space with direct memory access Accelerator 10

11 acceleration functions that just work in the cloud Container_1 Container_2 Container_1 Container_2 JVM_1 App_1 VNF_2 function... VNF_1 function... App_4 VNF_3 func VNF_4 func Non-privileged Nonpriveleged Guest OS 1 Guest OS 2 Guest OS 3 Priveleged Privileged Virtual Machines Virtual Machine 1 Virtual Machine 2 Virtual Machine Monitor (VMM)/Hypervisor Virtual Machine 3 Hyper- Hyper Priveleged Privileged Firmware, Option ROMs, etc Physical Machine Firmware Physical Machine (e.g., processors, DRAM, caches, mmu, iommu, other resources and SoC devices...) (Optional) Optional System Dependent System Dependent Other External Devices (e.g., disks, NICs, FPGAs, GPUs, crypto, other accelerators, other devices...) 11

12 layered architecture Protocol Layer coherency protocol, memory read & write flows Link Layer formats messages for target transport Protocol Layer messages Link Layer PCIe packets Transaction Layer Adds optimized packets, manages credit based flow control Physical Layer Dual mode PHY to support extended data rates Transaction Layer PCIe Data Link Layer PCIe Transaction Layer /PCIe Physical Layer Tx Rx 12

13 example request to home data flows Accelerator shares processor memory Shared processor and accelerator memory Home Home Home Daisy chain to shared processor memory Shared memory with aggregation Home Home Home 13

14 Improved efficiency with transaction layer Reduced latency with light weight transaction layer Improved packet efficiency with optimized header 14

15 PCI PCI PCI PCI port aggregation to boost bandwidth and transactions with Port Aggregation defines a hashing function to steer requests across multiple links. Aggregation effectively multiplies the bandwidth. Aggregation could also be used to increase number of transactions (eg 50GT/s vs 25GT/s). PCIe requires separate address spaces, requests can not be hashed. Home Home Home PCIe with Aggregation Home0 Accelerator Home0 Mem0 Mem1 15

16 RNI PCIe Transaction Layer Data Link Layer Transaction Layer PHY (up to 25Gpbs) CML SoC integration example Example CMN-600 mesh design DMC-620 DMC rd party PCIe/ IP CXS CoreLink CMN-600 XP 16 Lanes AXI DMC-620 DMC

17 Arm demonstration vehicle Arm s DynamIQ and CoreLink CMN-600 technology. Cadence and PCIe controller and PHY IP. TSMC 7nm process technology. Connectivity to Xilinx s Virtex UltraSoC+ FPGA. Xilinx, Arm, Cadence, and TSMC Announce World's First Silicon Demonstration Vehicle in 7nm Process Technology 17

18 Scale-up server node performance with is a class of interconnect providing high performance, low latency for new accelerators use cases. Easy adoption and simplified development by leveraging today s data center infrastructure. IP available from Arm and ecosystem to optimize SoC today. Server, FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs For more information go to: 18

19 Thank You! Danke! Merci! 谢谢! ありがとう! Gracias! Kiitos! The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. 19