BISTed cores and Test Time Minimization in NOC-based Systems

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1 BISTed cores and Test Time Minimization in NOC-based Systems Érika Cota 1 Luigi Carro 1,2 Flávio Wagner 1 Marcelo Lubaszewski 1,2 1 PPGC - Instituto de Informática 2 PPGEE - Depto. Engenharia Elétrica PO Box 15064, ZIP Av. Osvaldo Aranha, 103 ZIP Universidade Federal do Rio Grande do Sul Universidade Federal do Rio Grande do Sul Porto Alegre - RS - Brazil Porto Alegre - RS - Brazil {erika,flavio}@inf.ufrgs.br {carro,luba}@eletro.ufrgs.br Abstract This work discusses the role of BISTed cores in the test time reduction of NoC-based systems. A previously proposed technique that reuses network-on-chip for test purposes is used to define the optimum number of BISTed cores in the system, considering test time minimization and power consumption requirements. Experimental results show that not all of the embedded cores must have a self-contained test method to achieve a minimum global system test time. Keywords: Core-based Testing, Systems-on-chip Testing, Built-In Self Test, Design for Test. 1. Introduction The use of Built-In Self Test (BIST) techniques has been presented as one of the most interesting solutions to tackle the test complexity of a system-on-chip. If an embedded core is capable of testing itself, it requires less and slower communications with the external tester, and reduces the area and pin overhead at system level. Moreover, as BISTed cores do not require test access mechanisms (TAMs), the possibility of test parallelization at the system level is higher, that is, reduced test times can be achieved by the parallel testing of several cores without increasing the system costs in terms of pins. Test time reduction by means of test parallelization can also be achieved if an on-chip network is implemented as test access mechanism, as proposed in [1]. Test time reduction at lower costs can be achieved if an available network on-chip, defined to implement the connections among cores in an application, is reused as test access mechanism, as proposed in [2]. The main advantage of the reuse of an on-chip network is the availability of a number of access paths to This work was partially supported by CNPq each core, depending on the number of interfaces between the system and the external tester. If the system functional inputs and outputs can be reused, the pin overhead is null, while the area overhead is minimum, since the access mechanism is already available on the chip. Test time can be also minimized if the intrinsic parallelism of the communication platform is explored to increase the test parallelization. Test parallelization in NOC-based systems can be further improved by the use of BISTed cores. In this case, there are only two messages that must transit between the external tester and an embedded core: a test enable indication, and the resulting signature obtained by the core. Thus, the more BISTed cores are available in the system, the better should be the system test time, as less data must be transmitted throughout the network. However, BISTed versions of a core usually imply larger number of test patterns, leading to larger test times. Furthermore, BISTed cores also present higher power consumption during test. Therefore, during the test scheduling task, it may be necessary to increase test time as full parallelization may not be possible because of the power constraints. Considering the possible trade-offs of system configuration and testing time, the immediate question is: how many, and which of the embedded cores in the system should have a BIST test method, in order to reduce the global system test time? This work proposes a method to define which cores in a NOC-based system should have a BIST testing approach, so that the whole system test time is minimized. The paper is organized as follows: Section 2 reviews related work and explains the motivation of the proposed method. The use of the NoC during test is presented in Section 3. Section 4 presents the BIST model used in this work, while Section 5 presents the algorithm defined for the BISTed cores selection. In Section 6, experimental results are presented. Section 7 concludes the paper.

2 2. Related Work The use of a mix of BIST and external testing techniques at the system level has been discussed in several works, like [3]-[7]. Kaminska et al. [3] report a fuzzy tool to automatically select a cost effective test strategy for MCM modules. Their goal is to determine the correct balance of DFT and BIST that must be used at the system level, considering a multichip module. Sugihara et al. [6] and Jervan et al. [5] propose automatic methods to select the best combination of pseudorandom and deterministic patterns for each core in an SoC to minimize the system test time. In both works, each core is assumed to have a number of test sets, each set using a different combination of pseudo-random and deterministic patterns. The selection algorithms operate over the defined test sets, choosing one set for each core so that the system test is minimized. In [6] the usage of BIST controllers and TAM is also optimized. The quality of the final solution for these approaches is related to the number of possible test sets, which define the search space for the selection algorithms. However, the generation of the possible test sets can be a complex and time-consuming task. Ultimately, the mentioned approaches can select which cores in the system must have a BIST-based test, when, for example, a completely deterministic test set is selected for a core. However, this selection can only be made after a considerable number of test sets is generated. Thus, if the number of cores for which test sets must be defined is reduced, one can better explore the hybrid BIST method at core level. 3. Using the NoC During Test The reuse of the available on-chip network as an access mechanism to each core in the system has been proposed in a previous work [2]. The test vectors and test responses of each core are firstly expressed as a set of packets to be transmitted throughout the network. Functional inputs and outputs of the core, as well as the internal scan chains, are transformed into wrapper scan chains of similar length, in such a way that the channel width is enough to transport one bit of each scan chain. For each core, the number of packets to be transmitted is twice the number of test vectors (one for the vector and another one for the test response). The functional input and output points of the system are reused for the transmission of all packets (vectors and responses) from/to the external tester to/from all embedded cores. The system test time is measured as the time required until all response packets of all cores are received by the tester in the system outputs. The test problem is modeled as a scheduling one, where the packets that must be transmitted through the network are the tasks to be scheduled, and the different access paths for each core are defined as the resources that can be used by those tasks. Each task (packet) can use only one resource (path). A basic list scheduling algorithm was implemented, resulting in a very effective test method for such systems, with reduced test times with no pins and area overhead. Power consumption during test is modelled for the NoCbased TAM in [8]. Four sources of power consumption during test are considered: the core, the wrapper, the router, and the communication channel. The power consumption of each core during test is provided by the core provider, as well as the wrapper consumption for one packet processing. The total power consumption for a packet transmission is calculated according to the path established in the network for that packet: for each router and each channel active in the path, the router and channel consumptions are added. Then, the core and wrapper consumptions for one vector are added. The power consumption per cycle is included in the test planning method by assigning this information to each time slot of the test scheduling. Thus, before scheduling any packet, the total power required to transmit this packet is calculated. If the addition of this value to the total power consumption of the slot does not surpass the power consumption limit defined for the system, that packet can be scheduled. Otherwise, the packet is set to be scheduled later. 4. BIST and External Test In this work, we assume two types of test for a core: External test: the vectors are previously defined using a test pattern generator and stored in an external tester. Then, during test, the external tester delivers each pattern to the core, and collects and analyzes each core response. Built-in test: vectors are generated during test by a pseudo-random pattern generator embedded into the core. Test responses are collected by an also embedded signature analyzer. Only the final signature is sent the external tester to be evaluated. The built-in test is assumed to run at the normal frequency of the core under test. External test, on the other hand, will operate in the frequency of the on-chip network, which can be smaller than the operating frequency of the core. Furthermore, the proposed technique assumes that there are two versions of each core: one using an external test method, and another one using a complete built-in test 2

3 method. As the BIST method assumed is based on pseudorandom patterns, we consider that the BISTed version of each core has more test patterns, larger area and higher power consumption than the external tested version. A BISTed version of a circuit can be implemented in several ways, with different area overheads, test times and power consumption. In this paper, we initially consider a single BIST model for all cores, in order to explain the selection method without loss of generality. Then, in Section 6, an example of a mixed model, where each core has BIST solution with specific cost, is presented. Notice that the selection of which BIST method each core must have is not being addressed in this work. We assume that each core has at least one BISTed version available that one can consider during test planning. The BIST model used in section 5 considers an increase of 30% in the area of the core, 50% in the core power consumption during test, and 100% the number of test patterns, compared to the external testing. Notice that the actual number of pseudo-random vectors can be more than twice the number of deterministic patterns. However, as the test speed of the BIST approach is higher than the external test, this reduced number of vectors models the actual number of clock cycles considering the access mechanism frequency. Under this assumption, the test time of the BISTed version of a cores is still larger than the external version, but is closer to the actual BIST test time. 5. BISTed Cores Selection Algorithm In terms of system pin count and the communication with the external tester, the best option at system level is to have all embedded cores with BIST. However, power consumption during test can not be neglected if the number of BISTed cores is high. Moreover, as the core test time using BIST is higher than the external test time, the minimization of the system test time is the factor to be considered. Both, the test time minimization and the power consumption constraint must be considered while one seeks for a good tradeoff between the full BISTed version and the full external version of the system. The algorithm for selection of which cores in the system should be tested using a BIST technique is the following: 1. start with a full BISTed version of the system, that is, all cores have BIST. In this case, the possibility of test parallelization and the higher test frequency represent a good possibility for test time reduction, while the costs for pin count and communication with the tester are minimum. 2. define a test scheduling for the system, considering specified power constraints; 3. select the core with the largest test time and replace this core by its external tested version; 4. repeat steps 2 and 3 until the new system test time is worse than the previous solution; In fact, the algorithm selects the cores that must be tested by an external tester in order to reduce test time, that is, the cores that must use the system resources to be tested, because the system test time can not afford the increase in the number of test patterns and power consumption caused by the BISTed solution. The reduction in the system test time comes from the smaller number of patterns of external testing, and also from the access mechanism (in our case, the NOC itself), which allows a larger bandwidth and parallel message processing. 6. Experimental Results In this work, we use a packet-switched network model named SOCIN (System-on-Chip Interconnection Network), developed at UFRGS. The experiments were carried out in a 2-D grid topology with channels defined to be 32-bit wide, with packets having unlimited length. SOCIN uses creditbased flow-control and XY routing - a deadlock-free, deterministic and source-based approach, in which a packet is firstly routed on the X direction and after on the Y direction before reaching its destination. Switching is based on the wormhole approach, where a packet is broken up into flits (flow control units), the smallest unit over which the flow control is performed, and the flits follow the header in a pipeline way. The flit size equals the channel width, and routers include a 4-flit queues at each input port. The results for the system p22810 of the ITC 02 SoC Test Benchmarks [9] are presented. As the power information of the cores in this benchmark is not available, synthetic values are defined as a function of the number of scan flip-flops for each core. Therefore, the information in the example is always relative, as the absolute values are not the actual ones. Also, the test information of this benchmark considers only the external test of each core. Thus, for the BISTed version of each core we used the assumptions presented in Section 4, that is, twice the number of patterns, 30% more area in the core and 50% more power consumption during test. In the experiments, the power consumption limit was defined as a function of the power consumption of the embedded cores during normal operation mode. This function is defined as a percentage of the sum of the normal power consumption of all cores. Thus, for example, a power limit of 50% indicates that the power consumption limit corresponds to the half of the sum of the power consumption of all cores in normal mode. Notice that in a real case, the designer can define any power limit. 3

4 Figure 1 shows the variation in the system test time for a number of system configurations under no power constraints. Figure 2. Test time variation with selected BISTed cores for power constraint of 50% Figure 1. Test time variation with selected BISTed cores for no power constraint One can observe that, for this system and BIST model, the test time when all cores are BISTed is smaller than the solution will all cores with external testing. In fact, the test time for this case is 27.8% smaller than the test time for the system with no BISTed cores. However, the best test time is achieved when a combination of BISTed and non-bisted cores is used. This reduction has been shown before in [6], when multiple sets of test patterns are available and a single TAM is used for the external tests. Figure 1 shows that the minimization also exists when multiple external tests are delivered at the same time. Moreover, this result shows that not all cores are required to have a BISTed version to be used. In fact, as presented in Figure 1, the system test time starts to increase when the non-bisted version of core 20 is used. When only cores 1 and 15 are non-bisted, the system test time is defined by the BISTed version of core 20. However, even when this core is replaced by its external tested version, it still defines the system test time. Figures 2 and 3 show the variation in the system test time according to the number of BISTed cores when power constraints are considered. One can observe the same behavior of figure 1, that is, the system test time when all cores are BISTed is smaller than when no core is BISTed. Moreover, the test time reduces as some cores are replaced by their external tested versions. For more relaxed power constraints (50%), the system behavior is very similar to the situation where no power constraint exist. For this case, it is important to notice that although the system test time does not significantly change, the test scheduling is very different from one configuration to another. Indeed, the order of the test is changed, so that the power consumption limit is respected. For example, the average power consumption in the scheduling corresponding to the minimum test time of figure 1 is only 3% higher than the average power consumption for the minimum test time of figure 2. However, the peak power consumption drops 58% from the first configuration to the second one. For more restricted power constraints, like a 30% limit, it is interesting to notice in figure 3 that the minimum test time is achieved only when four cores are replaced by their external tested version. Indeed, as the BISTed versions consume more power during test, test time is increased in this case to meet the power requirements. Thus, only when less BISTed cores are used the test parallelization within the power limits can be defined. However, notice that the minimum test time for this case is 24% greater than the minimum test time of Figure 2. Figure 4 shows the test time variation according to the selected BISTed cores when a multiple BIST model is used. In this example, the increase in the power consumption and in the core test time in the BISTed version of each core was random assigned. One can observe that the cores selected in the previous single BIST model are the same selected when different BIST costs are used. For this system, cores 15, 1, and 20 have a much larger test time, compared to the other embed- 4

5 BIST model for each core, in order to minimize the system test time. Furthermore, the area overhead caused by the BIST can not be neglected, and can also be optimized by further selections based on this parameter. Thus, for example, after minimizing the system test time, one can consider the modification of other cores that are too expensive in terms of area. References Figure 3. Test time variation with selected BISTed cores for power constraint of 30% Figure 4. Test time variation with selected BISTed cores for multiple BIST models ded cores. Therefore, any increase in their test time compromises the overall system test time. [1] M. Nahvi and A. Ivanov. A Packet Switching Communication-Based Test Access Mechanism for System Chips. In ETW, Mar [2] E. Cota, C. Zeferino, M. Kreutz, L. Carro, M. Lubaszewski, and A. Susin. The Impact of NoC Reuse on the Testing of Core-based Systems. In Accepted to VTS, Apr [3] M. Fares and B. Kaminska. Test Strategy Selection for Multichip Systems. In 3rd International Conference on the Economics of Design, Test, and Manufacturing, pages , May [4] M. Abadir. Economics Modeling of Multichip Module Testing Strategies. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, 21(4): , Nov [5] G. Jervan, Z. Peng, and R. Ubar. Test Cost Minimization for Hybrid BIST. In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages , Oct [6] M. Sugihara, H. Date, and H. Yasuura. Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. In DATE, pages , Mar [7] G. Jervan, Z. Peng, R. Ubar, and H. Kruus. A Hybrid BIST Architecture and its Optimization for SoC Testing. In International Symposium on Quality electronic Design, pages 273 9, [8] E. Cota, L. Carro, F. Wagner, and M. Lubaszewski. Power- Aware NoC Reuse on the Testing of Core-based Systems. In To appear in European Test Workshop, May [9] E. J. Marinissen, V. Iyengar, and K. Chakrabarty. ITC 02 Soc Test Benchmarks. Oct Final Remarks We have discussed the role of the BISTed core in the test time minimization of a core-based system when an onchip network is reused as test access mechanisms of such a system. Experimental results have shown that there is a good combination of BISTed and externally tested cores, that must be sought in order to meet test time and power consumption during test requirements. The fact that each core might have different versions of BIST is actually a design for testability opportunity. Our current work comprehends the definition of an optimal 5

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