CPE 335 Computer Organization. Basic MIPS Pipelining Part I
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1 CPE 335 Computer Organization Basic MIPS Pipelining Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides CPE232 Basic MIPS Pipelining 1
2 Review: Single Cycle vs. Multiple Cycle Timing Single Cycle Implementation: Clk Cycle 1 Cycle 2 Multiple Cycle Implementation: lw sw Waste multicycle clock slower than 1/5 th of single cycle clock due to stage register overhead Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch CPE232 Basic MIPS Pipelining 2
3 How Can We Make It Even Faster? Split the multiple instruction cycle into smaller and smaller steps There is a point of diminishing returns where as much time is spent loading the state registers as doing the work Start fetching and executing the next instruction before the current one has completed Pipelining (all?) modern processors are pipelined for performance Remember the performance equation: CPU time = CPI * CC * IC Fetch (and execute) more than one instruction at a time Superscalar processing CPE232 Basic MIPS Pipelining 3
4 A Pipelined MIPS Processor In multicycle implementation, one functional unit is used in each clock cycle. Use idle units to do something else? Start the next instruction before the current one has completed improves throughput - total amount of work done in a given time instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB - clock cycle (pipeline stage time) is limited by the slowest stage - for some instructions, some stages are wasted cycles CPE232 Basic MIPS Pipelining 4
5 Single Cycle, Multiple Cycle, vs. Pipeline Single Cycle Implementation: Clk Cycle 1 Cycle 2 lw sw Waste Multiple Cycle Implementation: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 Clk lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Pipeline Implementation: lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB CPE232 Basic MIPS Pipelining 5
6 Why Pipeline? For Performance! Time (clock cycles) I n s t r. O r d e r Inst 0 Inst 1 Inst 2 Inst 3 ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg Once the pipeline is full, one instruction is completed every cycle, so CPI = 1 Inst 4 Time to fill the pipeline ALU IM Reg DM Reg CPE232 Basic MIPS Pipelining 6
7 Pipelining Performance Example: Comparing pipelining to single-cycle Consider a program that consists of a large number of load instructions: 1) Determine the time required to fetch the fourth load instruction and the speed up of pipelining 2) Determine the total time required to execute 3 load instructions and the speed up of pipelining 3) Repeat (2) when load instructions are executed 4) Repeat (1) and (2) if the delay of the register file is 100 ps * Assume the operation time for the major units (memory, ALU, and register file) is 200 ps. Cycle time in single-cycle is determined by the load instruction and equals 1000 ps ( ) Cycle time in pipelining is determined by the slowest stage; 200 ps CPE232 Basic MIPS Pipelining 7
8 Pipelining Performance cont d Consider a sequence of load instructions Single Cycle Pipelining CPE232 Basic MIPS Pipelining 8
9 Pipelining Performance cont d Time to start executing the fourth instruction Single-Cycle = 1000 x 3 = 3000 ps Pipelining = 3 x 200 = 600 ps (we fetch one instruction every clock cycle Speedup = 3000/600 = 5 Effect on execution time for three load instructions Single-cycle = 3 x 1000 = 3000 ps Pipelined = 1400 ps Speedup = 3000/1400 << 5???? (not enough workload) Consider adding 1,000,000 instructions Speedup = ( x 1,000,000) / ( x1,000,000) ~= 5 CPE232 Basic MIPS Pipelining 9
10 Pipelining Performance cont d Assume that the register file takes only 100 ps and we have 1,000,000 load instructions Single-cycle cycle time = 800 ps Pipelining cycle time = 200 ps Time to start the fourth instruction Single-cycle = 3 x 800 = 2400 ps Pipeline = 3x200 ps Speed up = 2400/ 600 = 4 Total execution time Speedup = (1,000,000x800) / (1,000,000x200) < 5 This is due to unbalanced stages CPE232 Basic MIPS Pipelining 10
11 Pipelining Performance cont d Ideally, pipeline speedup is n times faster than the single-cycle, where n is the number of pipeline stages. Time between instructions pipelined Time between instructions = Number of pipeline stages In the 5-stage MIPS, the pipelined version would be 5 times faster. When the pipeline is full, the throughput will be one instruction per cycle Factors that affect pipelining performance Time to fill and empty the pipeline with instructions Number of instructions to execute Unbalanced operation times for stages Consider register file access to be 100 ps?! Pipeline Hazards (Discussed in part II) Instruction mix nonpipelined CPE232 Basic MIPS Pipelining 11
12 MIPS Pipeline Datapath Modifications Notes on instruction execution in MIPS The execution of instructions is divided into 5 steps/cycles/stages: IF, ID, EX, MEM, and WB Instruction flow is from left to right except in two cases: o o In the write-back stage where the result is written into the register file in the middle of the datapath Choosing between the incremented PC and the branch address in the MEM stage What do we need to add/modify in our MIPS datapath to implement pipelining In pipeline execution, all units are operating in every cycle; we have to duplicate hardware where needed State registers are added between stages to preserve intermediate data and control for each instruction CPE232 Basic MIPS Pipelining 12
13 MIPS Pipeline Datapath Modifications IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack Add PC 4 Instruction Memory Read Address IFetch/Dec Read Addr 1 Register Read Read Addr 2Data 1 File Write Addr Read Data 2 Write Data Dec/Exec Shift left 2 Add ALU Exec/Mem Address Write Data Data Memory Read Data Mem/WB Sign 16 Extend 32 System Clock Do you see any problem? CPE232 Basic MIPS Pipelining 13
14 Corrected Datapath to Save RegWrite Addr Need to preserve the destination register address in the pipeline state registers IF/ID ID/EX EX/MEM Add PC 4 Instruction Memory Read Address Read Addr 1 Register Read Read Addr 2Data 1 File Write Addr Read Data 2 Write Data Shift left 2 Add ALU Address Write Data Data Memory Read Data MEM/WB Sign 16 Extend 32 CPE232 Basic MIPS Pipelining 14
15 MIPS Pipeline Data Flow Example Load Instruction Instruction Fetch Put PC and the loaded instruction in the IF/ID register CPE232 Basic MIPS Pipelining 15
16 MIPS Pipeline Data Flow Example Load Instruction Instruction Decode and register read Store rs, rt, sign extended offset, and the updated PC in the ID/EX register CPE232 Basic MIPS Pipelining 16
17 MIPS Pipeline Data Flow Example Load Instruction Execute or address calculation Store branch address, rt, result, and zero flag in the EX/MEM register CPE232 Basic MIPS Pipelining 17
18 MIPS Pipeline Data Flow Example Load Instruction Memory access Store the data from memory into MEM/WB register CPE232 Basic MIPS Pipelining 18
19 MIPS Pipeline Data Flow Example Load Instruction Write back Copy the data loaded in the MEM/WB register to register file CPE232 Basic MIPS Pipelining 19
20 Data Fields in the Pipeline Registers Pipeline Register IF/ID ID/EX EX/MEM MEM/WB Data Fields Instruction and PC PC, Reg[rs], Reg[rt], sign-extended offset, rt, rd Branch address, Zero, ALU result, Reg[rt], Destination register address (rt or rd) ALU Result, Data from memory, Destination register address Data fields are moved from one pipeline register to another every clock cycle until they are no longer needed CPE232 Basic MIPS Pipelining 20
21 MIPS Pipeline Control Path All control signals can be determined during Decode Expand the pipeline registers to store and move the control signals between stages until they are needed CPE232 Basic MIPS Pipelining 21
22 MIPS Pipeline Control Path Define the control signals The pipeline registers are updated every cycle; no separate write signals CPE232 Basic MIPS Pipelining 22
23 MIPS Pipeline Control Details Control signals used each stage Pipeline Stage IF ID EX MEM WB Control signals None None RegDst, ALUOp1, ALUOp0, ALUSrc Branch, MemRead, MemWrite MemtoReg, RegWrite Control signals values based on instruction type CPE232 Basic MIPS Pipelining 23
24 MIPS Pipeline - Example Given the code segment and the register contents below, show the contents of the data and control fields in the pipeline registers if the sixth instruction has been fetched (i.e. the beginning of cycle 7) Address Instruction 0x lw $10, 20($1) 0x sub $11,$1,$2 0x add $12,$3,$4 0x c lw $13, 24($1) 0x add $3,$2,$1 0x Sub $1,$5,$6 Register Contents $1 1 $2 5 $3 3 $4-6 $5 2 $6 7 $11 12 $12-15 $13 10 CPE232 Basic MIPS Pipelining 24
25 MIPS Pipeline - Example Multicycle diagram Time I n s t r. O r d e r lw $10, 20($1) sub $11,$1,$2 add $12,$3,$4 lw $13, 24($1) add $3,$2,$1 ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg ALU IM Reg DM Reg Sub $1,$5,$6 ALU IM Reg DM Reg CPE232 Basic MIPS Pipelining 25
26 MIPS Pipeline - Example Single-cycle diagram Sub $1,$5,$6 add $3,$2,$1 lw $13, 24($1) add $12,$3,$4 sub $11,$1,$2 CPE232 Basic MIPS Pipelining 26
27 MIPS Pipeline - Example The sixth instruction is fetched; it will be written to IF/ID register while the data and control for earlier instructions are pushed to the next pipeline registers /register file IF/ID register No control signals are stored Store the instruction sub $1,$5,$6 and PC+4 - IF/ID.Instruction = 0x00A IF/ID.PC = 0x CPE232 Basic MIPS Pipelining 27
28 MIPS Pipeline - Example ID/EX register Store the information of add $3,$2,$1 and PC+4 - ID/EX.PC = 0x ID/EX.RegRsContents = 0x ID/EX.RegRtContents = 0x ID/EX.RegRt = (00001) 2 - ID/EX.RegRd = (00011) 2 - ID/EX.SignExtend = 0x Control Information - ID/EX.MemToReg = 1 - ID/EX.RegWrite = 1 - ID/EX.MemRead = 0 - ID/EX.MemWrite = 0 - ID/EX.Branch = 0 - ID/EX.ALUSrc = 0 - ID/EX.RegDst = 1 - ID/EX.ALUOp = (10) 2 CPE232 Basic MIPS Pipelining 28
29 MIPS Pipeline - Example EX/MEM register Store the information of lw $13,24($1), branch address, and memory address - EX/MEM.BranchAddress = 0x EX/MEM.ALUOut = 0x EX/MEM..Zero = 0 - EX/MEM.RegDestination= (01101) 2 - EX/MEM.RegRtContents = 0x A Control Information - EX/MEM.MemToReg = 0 - EX/MEM.RegWrite = 1 - EX/MEM.MemRead = 1 - EX/MEM.MemWrite = 0 - EX/MEM.Branch = 0 CPE232 Basic MIPS Pipelining 29
30 MIPS Pipeline - Example MEM/WB register Store the information of add $12, $3,$4, addition result, and data memory - MEM/WB.RegDestination= (01100) 2 - MEM/WB.ALUOut = 0xFFFFFFFD - MEM/WB.MemoryData = XXXX Control Information - MEM/WB.MemToReg = 1 - MEM/WB.RegWrite = 1 For the sub $11, $1,$2 It will be writing (1-5) to $1 CPE232 Basic MIPS Pipelining 30
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