Microchip Summary Ethernet GigEpack

Transcription

1 V.5/17 Microchip Summary Ethernet GigEpack KSZ9031 In Production The KSZ9031 is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000Mbps or 10/100Mbps. The KSZ9031RNX provides the reduced gigabit media independent interface (RGMII). The KSZ9031 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a lowcost MOSFET to supply the 1.2V core. The KSZ9031 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and the board. The LinkMD TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths. The standard KSZ9031RNX is available in the 48-pin, lead-free QFN package, and the AEC- Q100 automotive qualified parts, KSZ9031RNXUA and KSZ9031RNXVA, are available in the 48-pin lead-free WQFN package. The KSZ9031MNX is available in a 64-pin, lead-free QFN package. Features Single-chip 10/100/1000Mbps IEEE compliant Ethernet transceiver KSZ9031Mxx feature GMII/MII standard interface with 3.3V/2.5V/1.8V tolerant I/Os KSZ9031Rxx feature RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os

2 Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full) On-chip termination resistors for the differential pairs On-chip LDO controller to support single 3.3V supply operation requires only one external FET to generate 1.2V for the core Jumbo frame support up to 16KB 125MHz Reference Clock Output Energy-detect power-down mode for reduced power consumption when the cable is not attached Wake-on-LAN (WOL) support with robust custom-packet detection AEC-Q100 qualified for automotive applications (KSZ9031RNXUA, KSZ9031RNXVA) Programmable LED outputs for link, activity, and speed Baseline wander correction LinkMD TDR-based cable diagnostic to identify faulty copper cabling Parametric NAND tree support to detect faults between chip I/Os and board Loopback modes for diagnostics Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation Automatic detection and correction of pair swaps, pair skew, and pair polarity MDC/MDIO management interface for PHY register configuration Interrupt pin option Power-down and power-saving modes Operating voltages: Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator) VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V Transceiver (AVDDH): 3.3V or 2.5V (commercial temp) Available in 48-pin QFN (7mm x 7mm) and 64-pin QFN (8mm x 8mm) packages

3 LAN7800 In Production Microchip's LAN7800 is a Super Speed USB 3.1 Gen 1 to 10/100/1000 Gigabit Ethernet bridge providing an ultra high-performance and cost-effective USB to Ethernet connectivity solution. The LAN7800 contains an integrated 10/100/1000 Gigabit Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device controller, SuperSpeed USB3.1 Gen 1 device controller, 10/100/1000 Gigabit Ethernet MAC, Integrated OTP, EEPROM controller. The device supports 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet and implements Control, Interrupt, Bulk-in and Bulk-out USB endpoints. The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX support and is compliant with IEEE 802.3/802.3u/802.3ab standards. USB-based networking provides flexibility for the routing and placement of network connections anywhere in the system. USB-based solutions leverage the existing USB stack for the Ethernet driver. The LAN7800 is also available with a wide range of drivers including Windows, Mac and Linux. The LAN7800 also offers Microchip s NetDetach and UniClock technologies. NetDetach allows for reduced power by enabling the host CPU to enter a low-power state when Ethernet is inactive. UniClock simplifies the clocking scheme and reduces system BOM cost by using a single 25MHz crystal for both USB and Ethernet connectivity. Multiple power management features are provided, including various low-power modes and Magic Packet, Wake-on-LAN (WoL) and Link Status Change wake events. MSFT QOAC (alway On Always Connected) is also supported. These wake events can be programmed to initiate a USB remote wakeup and if desired, also generate a hardware PME event. The device is available in commercial (0 to 70 C) and industrial temperature range (-40 to 85 C) options. HP Auto-MDIX eliminates the need for special "crossover" cables when connecting LAN devices together.

4 Features Highlights Single-chip, Super-Speed USB 3.1 Gen 1 to 10/100/1000 Ethernet controller Fully supports IEEE 802.3/802.3u/802.3ab standards Fully supports transformerless board level links 9K jumbo frames are supported IEEE 802.3az Energy Efficient Ethernet (EEE) Implements NetDetach technology for reduced system power consumption Provides dedicated PME wake-up signal Always On Always Connected (AOAC) Internal OTP memory to remove the need for external EEPROM Integrated core voltage regulator Requires only a single 25MHz crystal Easy upgrade for USB-based 10/100 Ethernet (LAN9500/9500A) to 10/100/1000 Gigabit Ethernet Industrial temperature range option available (LAN7800-I) 7x7mm, 48-pin SQFN (0.5mm pitch), RoHS-compliant package 6x6mm, 48-pin SQFN (0.4mm pitch), RoHS-compliant package Target Applications Embedded Systems Consumer Electronics Devices Netbooks/Smartbooks/MIDs Docking Stations Digital TVs (DTVs) Set-Top Boxes Personal Video Recorders (PVRs) Network Printers USB Port Replicators Stand-alone USB to Ethernet Dongles Industrial Designs

5 KSZ9897 In Production The KSZ9897 is a fully integrated layer 2, managed, seven-port gigabit Ethernet switch with numerous advanced features. Five of the seven ports incorporate 10/100/1000 Mbps PHYs. The other two ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. Full register access is available by SPI or I 2 C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface. Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering. An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments. Features Integrated 7-port 10/100/1000 Layer-2 switch with Gigabit uplink Non-blocking wire-speed Ethernet switching fabric Advanced Switch Capabilities Full-featured forwarding and filtering control, including Access Control List (ACL) filtering IEEE802.1X support (Port-Based Network Access Control) IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging VLAN ID tag/untag options on per port basis IEEE802.3x full-duplex flow control and half-duplex back pressure collision control IGMPv1/v2/v3 snooping for multicast packet filtering IPv6 multicast listener discovery (MLD) snooping QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels IPv4/IPv6 QoS support Programmable rate limiting at ingress and egress ports Broadcast storm protection Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets Self-address filtering for implementing ring topologies

6 Comprehensive Configuration Register Access High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers I2C Interface to access all registers MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE specification In-band management to access all registers via any of the seven ports, strap enabled I/O pin strapping facility to set certain register bits from I/O pins at reset time Control registers configurable on-the-fly Switch Monitoring Features Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII MIB counters for fully-compliant statistics gathering (34 MIB counters per port) Low Power Dissipation Full-chip software power-down Energy detect power-down (EDPD) Support IEEE P802.3az Energy Efficient Ethernet (EEE) Wake on LAN (WoL) support