Constructing Virtual Architectures on Tiled Processors. David Wentzlaff Anant Agarwal MIT

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1 Constructing Virtual Architectures on Tiled Processors David Wentzlaff Anant Agarwal MIT 1

2 Emulators and JITs for Multi-Core David Wentzlaff Anant Agarwal MIT 2

3 Why Multi-Core? 3

4 Why Multi-Core? Future architectures will be on-chip parallel machines Moore s Law provides more parallel silicon resources Diminishing sequential returns Growth applications are parallel 4

5 Why Multi-Core? Future architectures will be on-chip parallel machines Moore s Law provides more parallel silicon resources Diminishing sequential returns Growth applications are parallel Future architectures will be optimized for parallel applications Hardware compatibility will be broken 5

6 Why Emulators and JITs on Multi-Core? Future architectures will be on-chip parallel machines Moore s Law provides more parallel silicon resources Diminishing sequential returns Growth applications are parallel Future architectures will be optimized for parallel applications Hardware compatibility will be broken 6

7 Why Emulators and JITs on Multi-Core? Future architectures will be on-chip parallel machines Moore s Law provides more parallel silicon resources Diminishing sequential returns Growth applications are parallel Future architectures will be optimized for parallel applications Hardware compatibility will be broken Future architectures will need to run legacy applications Market forces will require future chips to run 1983 Frogger for DOS Software re-verification on new architectures too costly 7

8 Are Emulators and JITs for Multi-Core Different? 8

9 Are Emulators and JITs for Multi-Core Different? Yes 9

10 Are Emulators and JITs for Multi-Core Different? Yes Bountiful parallel resources Example: Code optimization cost is reduced hot spot analysis may miss sequential performance Parallelize client application 10

11 Are Emulators and JITs for Multi-Core Different? Yes Bountiful parallel resources Example: Code optimization cost is reduced hot spot analysis may miss sequential performance Parallelize client application Parameters for Multi-Core are different Core-to-Core latencies reduced 11

12 Road Map Exploit on-chip parallel resources to accelerate emulation 12

13 Road Map Exploit on-chip parallel resources to accelerate emulation 13

14 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance 14

15 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance Acceleration Mechanisms 15

16 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance Acceleration Mechanisms 1. Pipelining Virtual Architectures 16

17 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance Acceleration Mechanisms 1. Pipelining Virtual Architectures 2. Speculative Parallel 17

18 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance Acceleration Mechanisms 1. Pipelining Virtual Architectures 2. Speculative Parallel 3. Static & Dynamic Architecture Reconfiguration 18

19 Road Map Exploit on-chip parallel resources to accelerate emulation Focused on performance Acceleration Mechanisms 1. Pipelining Virtual Architectures 2. Speculative Parallel 3. Static & Dynamic Architecture Reconfiguration Proof of concept system All software parallel translator: x86 on Raw 19

20 Background: x86 Binary Disk Data RAM x86 Parser & High Level Translator High Level Optimization Code Cache Code Cache Tags Low Level Code Generation Translator Low Level Optimization and Scheduling Runtime -- Execution 20

21 Background: Old Parallel 21

22 1. Pipelining Virtual Architectures 22

23 1. Pipelining Virtual Architectures Translator Tile Code Cache Tile Execution Tile MMU Tile Data Cache Tile 23

24 1. Pipelining Virtual Architectures Translator Tile Code Cache Tile Execution Tile MMU Tile Data Cache Tile Utilize a Tiled Processor as fabric to construct virtual processor 24

25 1. Pipelining Virtual Architectures Translator Tile Code Cache Tile Execution Tile MMU Tile Data Cache Tile Utilize a Tiled Processor as fabric to construct virtual processor Coarse grain pipelining to exploit parallelism 25

26 Sequential Time Execution Time Time Optimization Time 26

27 2. Speculative Parallel Time Execution Time Time Optimization Time 27

28 3. Reconfiguration Different programs have different characteristics Processor Architect uses benchmarks to choose compromise processor 28

29 3. Reconfiguration Different programs have different characteristics Processor Architect uses benchmarks to choose compromise processor Static Reconfiguration Choose different virtual machine configuration based off application Dynamic Reconfiguration Detect phases/programs dynamic needs and reconfigure at runtime Cost to reconfiguration 29

30 Reconfiguration Photo Courtesy Intel Corp. 30

31 Prototype System and Evaluation 31

32 Background: Architectures * ISA Implementation x86 (Pentium III) CISC instruction set Hardware Virtual Memory (VM) Hardware Memory Protection Condition Codes used for branching Hardware instruction cache 1 superscalar processor core 3-way parallelism Out-of-order processor * Photo Courtesy Intel Corp. Raw RISC instruction set No VM No Memory Protection No Condition Codes Software managed instruction memory 16 Processors arranged in 4x4 mesh 4 low latency networks In-order processors 32

33 System Design Runtime -- Execution L1 Code Cache L1 Data Cache Manager L2 Code Cache Banked L1.5 Code Cache MMU TLB L2 Data $ Bank 0 System Functionality & Loader L2 Data $ Bank 1 L2 Data $ Bank 2 L2 Data $ Bank 3 33

34 System Design Runtime -- Execution L1 Code Cache Runtime-Exec L1 I-$ L1 Data L1 Cache D-$ Manager L2 Code Cache Banked L1.5 Code Cache MMU TLB L2 Data $ Bank 0 System Functionality & Loader L2 Data $ Bank 1 L2 Data $ Bank 2 L2 Data $ Bank 3 34

35 Methodology Cycle comparison of Raw vs. Pentium III All results collected on real hardware No hardware added Same binaries (unmodified) Metric: Slowdown Raw executing x86 code compared by cycle against Pentium III 35

36 Baseline Performance 36

37 2. Speculative Parallel 37

38 L2 Code Cache Miss Rate 2. Speculative Parallel Code Cache 38

39 3. Static Reconfiguration Manager L2 Code Cache Banked L1.5 Code Cache Runtime-Exec L1 I-$ L1 D-$ L2 Data $ Bank 1 System Functionality & Loader L2 Data $ Bank 2 MMU TLB L2 Data $ Bank 0 L2 Data $ Bank 3 39

40 3. Static Reconfiguration Manager L2 Code Cache Banked L1.5 Code Cache Runtime-Exec L1 I-$ L1 D-$ L2 Data $ Bank 1 System Functionality & Loader L2 Data $ Bank 2 MMU TLB L2 Data $ Bank 0 L2 Data $ Bank 3 40

41 3. Static Reconfiguration Manager L2 Code Cache Banked L1.5 Code Cache Runtime-Exec L1 I-$ L1 D-$ System Functionality & Loader MMU TLB L2 Data $ Bank 0 41

42 3. Dynamic Reconfiguration Manager L2 Code Cache Banked L1.5 Code Cache Runtime-Exec L1 I-$ L1 D-$ L2 Data $ Bank 1 System Functionality & Loader L2 Data $ Bank 2 MMU TLB L2 Data $ Bank 0 L2 Data $ Bank 3 42

43 3. Dynamic Reconfiguration Manager L2 Code Cache Banked L1.5 Code Cache Runtime-Exec L1 I-$ L1 D-$ L2 Data $ Bank 1 System Functionality & Loader L2 Data $ Bank 2 MMU TLB L2 Data $ Bank 0 L2 Data $ Bank 3 43

44 3. Reconfiguration Zoom 44

45 Baseline Performance Analysis 45

46 Baseline Performance Analysis 46

47 Baseline Performance Analysis Intrinsic Raw Emulator Pentium III latency occupancy latency occupancy L1 Cache Hit L2 Cache Hit L2 Cache Miss

48 Baseline Performance Analysis Intrinsic Raw Emulator Pentium III latency occupancy latency occupancy L1 Cache Hit L2 Cache Hit L2 Cache Miss CPI = (memory_access_rate * (((1 L1_miss_rate) * L1_hit_occupancy) + (L1_miss_rate * (((1 L2_miss_rate * L2_miss_occupancy))))) + ((1 memory_access_rate) * non_memory_cpi) 48

49 Baseline Performance Analysis Intrinsic Raw Emulator Pentium III latency occupancy latency occupancy L1 Cache Hit L2 Cache Hit L2 Cache Miss Memory CPI CPI = (memory_access_rate * (((1 L1_miss_rate) * L1_hit_occupancy) + (L1_miss_rate * (((1 L2_miss_rate * L2_miss_occupancy))))) + ((1 memory_access_rate) * non_memory_cpi) 49

50 Baseline Performance Analysis Memory System Lack of ILP Condition Codes (Flags) 3.9x slowdown 1.3x slowdown 1.1x slowdown 50

51 Baseline Performance Analysis Memory System Lack of ILP Condition Codes (Flags) 3.9x slowdown 1.3x slowdown x 1.1x slowdown 5.5x slowdown 51

52 Baseline Performance Analysis Memory System Lack of ILP Condition Codes (Flags) 3.9x slowdown 1.3x slowdown x 1.1x slowdown 5.5x slowdown Code Cache Misses 1 20x slowdown 52

53 Baseline Performance Analysis 53

54 Future Work Hardware additions to facilitate parallel emulation x86 Server farm on a chip Inter-Virtual Processor dynamic load balancing Differing forms of Dynamic Reconfiguration Vary number of functional units 54

55 Questions? 55

56 Extras 56

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