FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)

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1 FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor [O.G], Dept.of ECE, As-salam engineering and technology, I. INTRODUCTION Current silicon technologies enable the integration of billions of transistors in a single chip, supporting the creation of complex systems on a chip (SoCs). Networks on Chip (NoCs) constitute a suitable alternative for traditional SoC interconnect architectures, as they provide a high level of scalability and parallelism, supporting the ever-increasing number of cores in single chip. On-chip communication implemented with dedicated wires is only effective for systems with a small number of cores, as it presents poor reusability and scalability. Shared buses are more scalable and reusable, but only one communication at a time is allowed and the bandwidth is shared among all cores. Moreover, it also lacks scalability, given that all cores share the same communication medium. The NoC approach addresses all these issues. It consists of a communication infrastructure in which cores are connected to routers and these communicate among themselves through channels.our main aim is to create a NOC routerfor multi core processor architecture and that has been implementedin the NOC Router on a FPGA. Basically NOC architecture consist of two or more router which has associated with their processor, architecture is illustrated as figure 1.1 Hardware architecture. Processor 1 Figure 1 Hardware architecture There are several types of interconnections like point to point, bus architecture, Carbon Nanotubes, Optical fiber, and NoCs. Out of these a new paradigm called Network on Chip (NoCs) has been emerged as a replacement to the conventional type of on chip Interconnections. The problem with bus communication is lead to design fine architecture for interconnection. Troubles in older system are, bus communication used only in SOC. Bus requires more Power, size and less performance, practically for multiprocessor chips using a single bus interconnection. So it is less suitable reliable and fast inter connection. Hence we design NOC based interconnection which has to be fast, reliable data and less power consuming pipelined architecture. II. PROPOSED WORK FPGA based design of low power reconfigurable router for NoC applications are proposed in the present work. The router designed in the present work has four channels (namely, east, west, north and south) and a crossbar switch. Each channel consists of First in First out (FIFO) buffers and multiplexers.proposed system is written in VHDL, simulated using modelsim.for the Synthesis purpose Xilinx ISE Designis used. It provides the RTL view, design summary of circuit, and total power consumption by the circuit. Xilinx SPARTAN-3E FPGA is used for the implementation. Router 1 Router 2 Processor 2 NOC ISSN: Page 1

2 Figure 2 Router architecture The NoC/Router should deal with these issues Transmitting large data (buffer size, latency) Loss of data due to full buffer Data priority Data from several inputs to one output Blocked path prevents data transmission To meet the above requirements we design packet architecture where each Packet is divided to several smaller segments called flits, each flit is several bit width. A. PACKETS IN WORMHOLE ARCHITECTURE Wormhole switching allocates buffers and physical channels to flits (packetssplitinto multiple small flits as shown figure 4.) instead of large packets. A packet is decomposed into one or more flits. We call this decomposition flitization. Flitization is named following packetization, i.e., encapsulating a message into one or more packets. A flitisthe smallest unit, on which flow control is performed, can advance once buffering in the next switch is available to hold the flit. This results in that the flits of a packet are delivered in a pipeline fashion. In order to have a fast and reliable data interconnection this flitization process is followed. As illustrated in Figure 3, a packet is segmented into four flits, with one head. Figure 3 - Packets in Wormhole architecture B. FLIT STRUCTURE A message is broken into multiple packets (each packet contains header information that allows the receiver to re-construct the original message). A packet may itself be broken into flit flit does not contain additional headers.two packets can follow different paths to the destination Flits are always ordered and follow the same path. Such architecture allows the use of a large packet size (low header overhead) and yet allows fine-grained resource allocation on a per-flit basis. Figure 4 Flit structure in NOC Wormhole Flow Control just like cut-through, but with buffers allocated per flit (not channel). A head flit must acquire three resources at the next switch before being forwarded: ƒ channel control state (virtual channel, one per input port) ƒone flit buffer, one flit of channel bandwidth The other flits adopt the same virtual channel as the head and only compete for the buffer and physical channel, Consumes much less buffer ISSN: Page 2

3 space than cut-through routing does not improve channel utilization as another packet cannot cut in. C. DESIGN OF BUS AND CROSSBAR SWITCH The first generation of on-chip interconnects consisted of conventional bus and crossbar structures. In a bus, interconnect is mostly just wires, interconnecting IP Cores, combined with an arbiter that manages the access to the bus. System-level latency and bandwidth constraints led to a natural evolution towards multi-tiered bus architecture, typically consisting of a highperformance low-latency processor bus, a highbandwidth memory bus and a peripheral bus. Example bus architecturesare the AMBA family (AHB/APB) from ARM, Inc, and the Core Connect architecture from IBM. implemented from And-Or-Invert (AOI) gates is shown in figure 6. E. Power Reduction All FPGA devices have an internal global reset path. When the device is switched OFF and then ON, all the flip flops and memories are reset to their initial state. But when we define one more reset signal in the HDL code, Xilinx creates a second reset. This second reset is relatively low and hence not recommended. But if you still want to use them make sure it is synchronous, so that the number of the control signals in your design is low. III. RESULTS A. WEST CHANNEL DATA AND LEDOUTPUT Proposed architecture associated with four channels (east, west, north and south). Waveforms shown in figure 7 describethat data stored in fourchannels and its corresponding led output values. Figure 5 buses and crossbar approach for NOC The advent of the SoC, incorporating tens to hundreds of IP cores created a significant integration challenge. The above described busses and cross-bars are coupled solutions. The interfaces of all IP cores connected to a single bus or cross-bar must all be exactly the same, both logically (signals) and in physical design parameters (clock-frequency, timing margins). D. DESIGN OF MULTIPLEXER Figure 7 Data stored in west channel and it s led output Synthesized data stores value in north, south, east and west are in router shown figure 8, all the four channels are connected to crossbar switch because final output is taken from the crossbar. Figure 6-4x1 Multiplexer A multiplexer allows digital signals from several sources to be routed onto a single bus or line. A 'select' input to the multiplexer allows the source of the signal to be chosen. 4x1 multiplexer Figure 8 Output of final data stored in four channels from router B. MUX AND ROUTER ISSN: Page 3

4 RTL view of multiplexer, final router architecture, power consumption report and area utilization report are shown in fig. 9(a), 9(b), 10(a) and 10(b). Figure 9(a) Router architecture in NOC Figure 10(b) Area utilization on FPGA Implementation Figure 9(b) Complete final architecture of channels Figure 10(a) Shows power consumed by our architecture IV. CONCLUSION Proposed work deals with designing a fast, reliable and reconfigurable router design with objective of low power consumption and high performance operation because router is the most important for NOC design. Our NOC architecture consists of four channels (north, south, east and west) with a crossbar switch. This work has been verified using ISSN: Page 4

5 Modelsimsimulation tool. We designed multiplexer are used to control the input and output date from four channels. Proposed design has occupied only one percentage of the whole slices volume in Spartan 3e fpga hardware as shown in fig. 10(b) area report. ISSN: Page 5

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