Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA
|
|
- Pierce Foster
- 6 years ago
- Views:
Transcription
1 Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA Maheswari Murali * and Seetharaman Gopalakrishnan # * Assistant professor, J. J. College of Engineering and Technology, Tiruchirappalli, India # Principal, Oxford Engineering College, Tiruchirappalli, India Abstract Modern platform Field Programmable Gate Arrays provide larger gate count with increased performance. This feature allows realization of System On Chip on modern FPGAs. When the number of cores increases, the communication demands between cores also increases in SoCs. Hence, Network On Chip has been proposed, to meet out the challenges between the cores. In this paper, a design of low cost, low complexity router for 2D mesh topology is proposed. The low complexity router is implemented on Altera cyclone II FPGA EP2C35F672C6 device. From the implementation results, the proposed router is operated with higher speed, lower area and lower power dissipation compared with previous designs. We have also tested 2 x 2, 3 x 3 and 4 x 4 mesh for the designed router and implemented on cyclone II FPGA. From the implementation results, the proposed one gives better performance in terms of area, speed and power. Key words: FPGA, SOPC, SOC, and NOC 1 Introduction In the last decade there has been an increase in the computation requirement and the number of Intellectuel property (IP) cores for embedded systems. This has fostered the development of high performance embedded platforms that can handle the computational requirements of complex algorithms. With the advancement of semiconductor technology, now-a-days embedded platforms like modern Field Programmable Gate Arrays (FPGAs) have embedded hard and soft core processors, digital signal processors, memories, peripherals, and clock management systems. FPGAs with their Embedded memory and other specialized functionality have become feasible choice to implement a System On Chip (SOC) design in Application Specific Integrated Circuits (ASIC). But for implementation in ASIC, system complexity will increase the requirements for on-chip communication. Hence, the Network On Chip (NOC) has evolved as a solution for addressing this challenge. In addition, FPGA can also take up the NOC model in order to support more complex SOC implementations [1]. For NOC, Router and other logic can be implemented using programmable logic in FPGA, and dedicated NOC elements can lead to better performance and more efficient utilization of on chip FPGA resources [2, 3]. However a certain degree of configurability is required even for embedded NOC support within FPGA. In NOC messages are being routed through routers called switches [4]. IP cores are connected to the router through Network Interface (NI). It is shown in Fig. 1. Connecting IP cores through routers has several advantages than dedicated bus based wiring. It delivers high bandwidth, low latency, and low power [5]. This paper fi, describes a reconfigurable router for 2D mesh topology with modified architecture. Second, the design has also been tested for (2 X 2), (3 x 3) and (4 x 4) 2D mesh network. In Altera tool, SOPC builder generates softcore processor NIOS II (32 bit). The reconfigurable router is implemented using NIOS II processor. The organization of the rest of the paper is as follows: In section 2, the review of previous work related to NOC is discussed. In section 3, the router architecture and design and implementation details are discussed. In section 4, the implementation results and performance analysis are discussed. Finally section 5, summarizes conclusions. Fig X 3 mesh NOC
2 Fig.2. Router Architecture 2 Review of previous work in NOC Literature of NOC shows that most of the work in Network On Chip have been carried out using ASIC, However a few research works have been carried out using FPGA. Important contributions are made to NOC design in [7] but implementation details are not given. Highly scalable Network On Chip for reconfigurable systems has been made in [8]. In this, the design of NOC with virtual cut through switching which has low latency, and it uses large buffer which occupies more silicon area. In [9], design of a router for NOC has been tested for two applications (FFT & Matrix Multiplication). A scalable packet switch based router for 2D mesh and torus topology has been implemented in both FPGA and ASIC in [1]. R. Gindin et al proposed a design of NOC on FPGA and used a standard mesh topology. In this the reconfigurability is limited to routing schemes only. In [11], a router is designed for 2D mesh topology and it has been synthesized on Xilinx FPGA. In this, the design contains limited routing and arbitration and no applications were tested. Also the design consists of routers that evaluated with logic simulation only.this router design [11] is similar to the proposed work in this paper with minar modifications in the FSM Controller and arbitration. All the above said works have complex design. But, in this paper FSM controller is efficiently designed and it occupies less area, which reduces the complexity of the router compared to other designs discussed above. The proposed router and the mesh topologies are implemented and verified using Altera Nios II processor which fi of its kind. 3 Router Architecture Network On Chip consists of three important components Router, Processing Element, Network Interface. The router architecture is shown in Fig. 2. Routing Node is responsible for forwarding the data packets to the destination node. Each router has associated with unique XY address. In a mesh based NOC, a router has five directional channels. They are EAST, WEST, NORTH, SOUTH and a Local channel to which design core is connected. The directional channels connect the
3 router with its neighboring routers and the local channel is used to connect the Processing Element to the router. Processing Element is used to implement the computing functionality in DSP, Microcontroller or memory block, and input/output device controller. Network Interface is an interface between router and design core. It performs two way communications. Fi it collects the data from the design core, then pocketize and adds the header and it pushes the packet into the router. Second it receives the packet from the attached router and depacketizes then sends the data to the Processing Element. Fig. 2 shows the router architecture which contains input port, output port, cross bar switch, arbiter and header decoder.the function of these blocks are explained in the following subsections. 3.1 Input Port Each input port shown in fig. 2 has a FIFO buffer header decoder, and FSM controller. The diagram for input port is shown in Fig. 3(a). FIFO buffer is used to store the data packets. Header decoder is used to decode the destination address. The FSM controller is used to control all the operations. FIFO buffer is implemented using Quartus II Mega wizard function. The size of the FIFO buffer is parameterizable and use 8 bit data width and 32 locations depth to store the packets. When the request comes from neighboring router, if the FIFO buffer is empty the input port sends the acknowledgement (ACK) signal to the neighboring router, after receiving the acknowledgment the neighboring router sends the fi flit. This flit is stored in the buffer and a signal is sent to the header decoder to decode the destination address and then fi flit is sent to the header decoder. Header decoder after decoding the address send a request to an arbiter of the corresponding output port. If the destination address is matched with router address, then the particular data is for that corresponding PE. So the acknowledgement is sent to the arbiter of the local output channel. 3.2 Output Port The output port has an arbiter, and a FSM controller. The diagram for output port is shown in Fig. 3(b). Each output port has two locations depth buffer to store the flit temporarily untill it gets access from the down stream router. In Fig. 3(b), an arbiter is used to resolve the conflicts when more than one requests come to the same output port. If more than one requests comes to a particular output port, the arbiter gives access to only one input port based on round robin priority. The priority is rotated in round robin fashion. The input port which has been granted access to send the remaining flits, then sends the flits to the output port through the cross bar switch. After receiving the fi flit, the output port sends a request to the neighboring router to which it is connected. If ACK comes from neighboring router it sends the flits to next router. 3.3 Cross Bar Switch Fig. 3(b). Output Port The cross bar switch is shown fig. 2. In the proposed router, simultaneously five transmissions are possible. Hence each output port has cross bar switch, and it is implemented using Multiplexer and De-multiplexer. All the input ports are connected to the multiplexer inputs and all the De-multiplexer outputs are connected to all the output ports except its own output port. Each output channel configures the multiplexers and De- multiplexer to establish the appropriate input-output connection. 3.4 Arbiter Fig. 3(a). Input Port The arbiter is shown in fig. 2. The arbiter resolves the problem if requests come from more than one input ports to the same output port and gives access to only one input port using round robin priority. This arbiter assigns priority in round robin fashion in the order east, west, north,
4 south, and local. For example if east input port is assigned with the highest priority and then the next highest priority is assigned to west input port. The arbiter gives access to east input port fi and then west input port and so on. 3.5 Header Decoder The Header decoder in the input port is shown in fig.3(a). In this paper, XY routing algorithm is proposed. Each router has its unique coordinate as address (X,Y). When the header decoder receives the destination address (Rx, Ry), it compares local X coordinate with the destination coordinate Rx, and sends the packet through east channel if Rx > X and through west channel if Rx < X. If Rx is equal to the local X coordinate, then Y coordinate of the router is compared with destination coordinate Ry. If Ry > Y coordinate then the packet is routed through North Channel, else the packet is routed through south channel. If Ry =Y, then the packet is sent through the local channel to the Processing Element. 3.6 SOPC approach for NOC Altera System On Programmable Chip (SOPC) Builder is used to add the design element. Using SOPC builder, the proposed router and all mesh topologies are added to the Nios II processor as the custom block. The program to be executed and verified by writing in C using Nios II IDE [12]. The custom block is invoked as the function in C code. The C program is complied and the configuration bits are downloaded to the FPGA for verification. cyclone II FPGA EP2C35F672C6 device [6]. We used Quartus II 8.1 to synthesis and simulate the RTL design. The area and the speed of the single router, 2 x 2 and 3 x 3 mesh configurations are compared with the design of [11]. The proposed design occupies 2% less area and 5% higher speed. The synthesis results are shown in figure. 4. The simulation result shown in the figure. 5. The RTL schematic view of the proposed router is shown in figure Synthesis Report The implementation of the proposed router occupies 592 LUTs which is only 2% of the total Altera EP2C35F672C6 device. The area occupied by the 2 x 2, mesh is 1374 LUTs which is only 4% of the total area 3 x 3 is 2645 which is 8% of total area, and 4 x 4 mesh is 3634 which is 12% of total area. 4.2 Power Analysis From the implementation results, the power dissipation for single router, 2 x 2 and 3 x 3 are shown in figure 4. The power dissipation is measured using Power play power Analyzer tool available with Altera Quartus 8.1. The power dissipation for the single router design is found to be low compared to [11]. The proposed design consumes only 12mw of thermal power dissipation, 8mw of core static thermal power, and 38mw I/O thermal power dissipation. 4 Implementation Results & Performance Analysis The proposed router is implemented on Altera cyclone II FPGA. It has been designed by writing HDL. The buffer which is used to store the flits decides the area of the router. Hence, the proposed design uses FIFO buffer which is available in Quartus II mega wizard function. The FIFO which is used in this design is a parameterizable. The data width is 8 bit and the depth of the buffer is chosen as 32 locations for testing purpose. The flow control mechanism used is wormhole method which requires less buffer size to store the data. The proposed design uses XY routing algorithm. In the proposed design uses random number generator to generate random numbers. Fi, this random number generator is connected to all the input channels and verified the data from the output channels of a single router. Second, the 2D mesh topology is implemented with the designed router and verified using random number generator for 2 X 2 configurations. The same method has been adopted to test 3 x 3, 4 x 4 configurations of 2D mesh. The designed router has been implemented on Altera Fig. 4. Implementation Result
5 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- ack_from_core ack_from_north ack_from_south req_from_north req_from_south muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ackin_east muxin_east[7..] muxin_local[7..] muxin_west[7..] ack_from_north ackin_south req_from_north muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ack_from_south ackin_north req_from_south muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ackin_west muxin_east[7..] muxin_local[7..] muxin_west[7..] grnt_to_north req_to_core dataout_local[7..] grnt_to_local reqout_east dataout_east[7..] grnt_to_west reqout_south dataout_south[7..] grnt_to_south reqout_north dataout_north[7..] grnt_to_east reqout_west dataout_west[7..] grnt_south reqin_north grnt_from_east grnt_from_north grnt_from_south grnt_from_west reqin_local grnt_east grnt_north grnt_south reqin_west grnt_north reqin_south grnt_north grnt_south grnt_west reqin_east ack_local ackout_north req_to_local dataout_north[7..] ack_south ackout_west req_to_south dataout_west[7..] ack_to_north ackout_south req_to_north dataout_south[7..] ack_west ackout_east req_to_west dataout_east[7..] ack_to_east ackout_local req_to_east dataout_local[7..] Fig. 5. Simulation result of single router ackin_local ackin_east ackin_south ackin_north ackin_west reqin_east reqin_south reqin_west reqin_local reqin_north local_outputchannel:l1 north_inputchannel:nor1 east_outputchannel:e2 south_outputchannel:sou2 north_outputchannel:nor5 local_inputchannel:l2 west_inputchannel:w1 south_inputchannel:sou1 east_inputchannel_new:ea1 west_outputchannel_new:we1 ackout_north reqout_local dataout_local[7..] reqout_north dataout_south[7..] reqout_south dataout_east[7..] reqout_east ackout_local ackout_west ackout_south dataout_north[7..] ackout_east reqout_west dataout_west[7..] Fig. 6. RTL Schematic view of single route 5 Conclusions The proposed router has been designed for 2D mesh topology which has low complexity and high speed. The single router and 2 x 2, 3 x 3, 4 x 4 mesh topology have been implemented and tested with SOPC using NIOS II processor. From the implementation results, it is found that the proposed router is operated with higher speed and lower area and lower power dissipation compared with the previous design. Our future work is to test the signal processing application using this proposed router. 6. References [1]. Ronny Pau and Naraig Manjikian High level Specification and logic implementation of Single chip Multiprocessor system based on a configurable router IEEE, pp , 28. [2]. H.Elmiligi et al. Introducing OperaNP : A Reconfigurable NoC based platform Proc.27 IEEE Canadian Con. On Electrical and computer Engineering, pp , 27. [3]. R. Gindin et al. NoC based FPGA Architecture and routing In Proc.
6 Intet. Sympo. on Network On chip, pp , 27. [4]. W.J.Dolly and B.Towles Principles and Practices of Interconnect Networks. Morgan Kaufmann Publishers 23. [5]. T.Bjerregaard and S. Mahadevan A survey of Research Practices of Network On Chip ACM Computing Survey Vol- 38, no-1, pp. 1-51, 28. [6]. Altera Inc. http :// [7]. L.Benni and G. D Micheli Network on Chips: A new SOC Paradigm IEEE Computer, vol. 35 no.1, pp. 7-78, 22. [8]. A. Batric et al. Highly Scalable Network On Chip for reconfigurable systems In proceedings of the International Conference on Systems On Chip 23, pp , NOV. 23. [9]. Gaoming Du, Duolo Zhang et al Scalability Study on mesh based Network On Chip IEEE PAWCIIA- 28, pp , 28. [1]. Yahia SALAH, Mohamed ATRI, Rached TOURKI Design of a 2D Mesh- Torus Router for Network On Chip IEEE International Symposium on Signal Processing and Information Technology, pp , 27. [11]. Balasubramanian Sethuraman, et al LiPaR: A Light Weight Parallel Router for FPGA based Network On Chip GLSVLSI, pp , 25. [12]. G.Seetharaman and B. Venkatramani SOC implementation of wave pipelined circuits Proc. of International Conference on Field Programmable Technology, (ICFPT 27) pp.9-16, Japan, 27.
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor
More informationCHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP
133 CHAPTER 6 FPGA IMPLEMENTATION OF ARBITERS ALGORITHM FOR NETWORK-ON-CHIP 6.1 INTRODUCTION As the era of a billion transistors on a one chip approaches, a lot of Processing Elements (PEs) could be located
More informationOASIS NoC Architecture Design in Verilog HDL Technical Report: TR OASIS
OASIS NoC Architecture Design in Verilog HDL Technical Report: TR-062010-OASIS Written by Kenichi Mori ASL-Ben Abdallah Group Graduate School of Computer Science and Engineering The University of Aizu
More informationPerformance Analysis of Routing Algorithms
International Journal Scientific & Engineering Research Volume 3, Issue 12, December-2012 1 Performance Analysis Routing Algorithms Mr. Lokesh M. Heda Shri Ramdeobaba, College Engineering and Management,
More informationDesign and implementation of deadlock free NoC Router Architecture
Design and implementation of deadlock free NoC Router Architecture Rohini 1, Dr.G.R.Udupi 2, G.A.Bidkar 3 1 - Student of M. Tech in Industrial Electronics, 2-Principal, 3- Asst.Prof & HOD E&C Dept KLS
More informationDesign and Implementation of Buffer Loan Algorithm for BiNoC Router
Design and Implementation of Buffer Loan Algorithm for BiNoC Router Deepa S Dev Student, Department of Electronics and Communication, Sree Buddha College of Engineering, University of Kerala, Kerala, India
More informationDesign and Implementation of a Packet Switched Dynamic Buffer Resize Router on FPGA Vivek Raj.K 1 Prasad Kumar 2 Shashi Raj.K 3
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Design and Implementation of a Packet Switched Dynamic Buffer Resize Router on FPGA Vivek
More informationA Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing
727 A Dynamic NOC Arbitration Technique using Combination of VCT and XY Routing 1 Bharati B. Sayankar, 2 Pankaj Agrawal 1 Electronics Department, Rashtrasant Tukdoji Maharaj Nagpur University, G.H. Raisoni
More informationFCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
More informationHARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON- CHIP NETWORK
DOI: 10.21917/ijct.2012.0092 HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON- CHIP NETWORK U. Saravanakumar 1, R. Rangarajan 2 and K. Rajasekar 3 1,3 Department of Electronics and Communication
More informationDesign and Analysis of On-Chip Router for Network On Chip
Design and Analysis of On-Chip Router for Network On Chip Ms. A.S. Kale #1 M.Tech IInd yr, Electronics Department, Bapurao Deshmukh college of engineering, Wardha M. S.India Prof. M.A.Gaikwad #2 Professor,
More informationNetworks-on-Chip Router: Configuration and Implementation
Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan,
More informationDesign of Reconfigurable Router for NOC Applications Using Buffer Resizing Techniques
Design of Reconfigurable Router for NOC Applications Using Buffer Resizing Techniques Nandini Sultanpure M.Tech (VLSI Design and Embedded System), Dept of Electronics and Communication Engineering, Lingaraj
More informationHigh Performance Interconnect and NoC Router Design
High Performance Interconnect and NoC Router Design Brinda M M.E Student, Dept. of ECE (VLSI Design) K.Ramakrishnan College of Technology Samayapuram, Trichy 621 112 brinda18th@gmail.com Devipoonguzhali
More informationLow Cost Network on Chip Router Design for Torus Topology
IJCSNS International Journal of Computer Science and Network Security, VOL.17 No.5, May 2017 287 Low Cost Network on Chip Router Design for Torus Topology Bouraoui Chemli and Abdelkrim Zitouni Electronics
More informationISSN Vol.03, Issue.02, March-2015, Pages:
ISSN 2322-0929 Vol.03, Issue.02, March-2015, Pages:0122-0126 www.ijvdcs.org Design and Simulation Five Port Router using Verilog HDL CH.KARTHIK 1, R.S.UMA SUSEELA 2 1 PG Scholar, Dept of VLSI, Gokaraju
More informationDESIGN OF EFFICIENT ROUTING ALGORITHM FOR CONGESTION CONTROL IN NOC
DESIGN OF EFFICIENT ROUTING ALGORITHM FOR CONGESTION CONTROL IN NOC 1 Pawar Ruchira Pradeep M. E, E&TC Signal Processing, Dr. D Y Patil School of engineering, Ambi, Pune Email: 1 ruchira4391@gmail.com
More informationOASIS Network-on-Chip Prototyping on FPGA
Master thesis of the University of Aizu, Feb. 20, 2012 OASIS Network-on-Chip Prototyping on FPGA m5141120, Kenichi Mori Supervised by Prof. Ben Abdallah Abderazek Adaptive Systems Laboratory, Master of
More informationRouting Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip
Routing Algorithms, Process Model for Quality of Services (QoS) and Architectures for Two-Dimensional 4 4 Mesh Topology Network-on-Chip Nauman Jalil, Adnan Qureshi, Furqan Khan, and Sohaib Ayyaz Qazi Abstract
More informationDesign of Synchronous NoC Router for System-on-Chip Communication and Implement in FPGA using VHDL
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IJCSMC, Vol. 2, Issue.
More informationFPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP
FPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP 1 M.DEIVAKANI, 2 D.SHANTHI 1 Associate Professor, Department of Electronics and Communication Engineering PSNA College
More informationApplying the Benefits of Network on a Chip Architecture to FPGA System Design
white paper Intel FPGA Applying the Benefits of on a Chip Architecture to FPGA System Design Authors Kent Orthner Senior Manager, Software and IP Intel Corporation Table of Contents Abstract...1 Introduction...1
More informationSoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik
SoC Design Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik Chapter 5 On-Chip Communication Outline 1. Introduction 2. Shared media 3. Switched media 4. Network on
More informationEfficient And Advance Routing Logic For Network On Chip
RESEARCH ARTICLE OPEN ACCESS Efficient And Advance Logic For Network On Chip Mr. N. Subhananthan PG Student, Electronics And Communication Engg. Madha Engineering College Kundrathur, Chennai 600 069 Email
More informationDESIGN A APPLICATION OF NETWORK-ON-CHIP USING 8-PORT ROUTER
G MAHESH BABU, et al, Volume 2, Issue 7, PP:, SEPTEMBER 2014. DESIGN A APPLICATION OF NETWORK-ON-CHIP USING 8-PORT ROUTER G.Mahesh Babu 1*, Prof. Ch.Srinivasa Kumar 2* 1. II. M.Tech (VLSI), Dept of ECE,
More informationDeadlock-free XY-YX router for on-chip interconnection network
LETTER IEICE Electronics Express, Vol.10, No.20, 1 5 Deadlock-free XY-YX router for on-chip interconnection network Yeong Seob Jeong and Seung Eun Lee a) Dept of Electronic Engineering Seoul National Univ
More informationLecture 18: Communication Models and Architectures: Interconnection Networks
Design & Co-design of Embedded Systems Lecture 18: Communication Models and Architectures: Interconnection Networks Sharif University of Technology Computer Engineering g Dept. Winter-Spring 2008 Mehdi
More informationA VERIOG-HDL IMPLEMENTATION OF VIRTUAL CHANNELS IN A NETWORK-ON-CHIP ROUTER. A Thesis SUNGHO PARK
A VERIOG-HDL IMPLEMENTATION OF VIRTUAL CHANNELS IN A NETWORK-ON-CHIP ROUTER A Thesis by SUNGHO PARK Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements
More informationDesign And Verification of 10X10 Router For NOC Applications
Design And Verification of 10X10 Router For NOC Applications 1 Yasmeen Fathima, 2 B.V.KRISHNAVENI, 3 L.Suneel 2,3 Assistant Professor 1,2,3 CMR Institute of Technology, Medchal Road, Hyderabad, Telangana,
More informationArchitecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC
BWCCA 2010 Fukuoka, Japan November 4-6 2010 Architecture and Design of Efficient 3D Network-on-Chip for Custom Multi-Core SoC Akram Ben Ahmed, Abderazek Ben Abdallah, Kenichi Kuroda The University of Aizu
More informationA Modified NoC Router Architecture with Fixed Priority Arbiter
A Modified NoC Router Architecture with Fixed Priority Arbiter Surumi Ansari 1, Suranya G 2 1 PG scholar, Department of ECE, Ilahia College of Engineering and Technology, Muvattupuzha, Ernakulam 2 Assistant
More informationAREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP Rehan Maroofi, 1 V. N. Nitnaware, 2 and Dr. S. S. Limaye 3 1 Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur,
More informationBARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs
-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs Pejman Lotfi-Kamran, Masoud Daneshtalab *, Caro Lucas, and Zainalabedin Navabi School of Electrical and Computer Engineering, The
More informationDESIGN AND IMPLEMENTATION ARCHITECTURE FOR RELIABLE ROUTER RKT SWITCH IN NOC
International Journal of Engineering and Manufacturing Science. ISSN 2249-3115 Volume 8, Number 1 (2018) pp. 65-76 Research India Publications http://www.ripublication.com DESIGN AND IMPLEMENTATION ARCHITECTURE
More informationPERFORMANCE ANALYSES OF SPECULATIVE VIRTUAL CHANNEL ROUTER FOR NETWORK-ON-CHIP
PERFORMANCE ANALYSES OF SPECULATIVE VIRTUAL CHANNEL ROUTER FOR NETWORK-ON-CHIP Amit Kumar Lamba, M-tech Student Bharati B Sayankar Assistant professor Pankaj Agrawal Associate Professor Department of E
More informationEmbedded Systems: Hardware Components (part II) Todor Stefanov
Embedded Systems: Hardware Components (part II) Todor Stefanov Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science Leiden University, The Netherlands Outline Generic Embedded
More informationImplementation of PNoC and Fault Detection on FPGA
Implementation of PNoC and Fault Detection on FPGA Preethi T S 1, Nagaraj P 2, Siva Yellampalli 3 Department of Electronics and Communication, VTU Extension Centre, UTL Technologies Ltd. Abstract In this
More informationISSN:
113 DESIGN OF ROUND ROBIN AND INTERLEAVING ARBITRATION ALGORITHM FOR NOC AMRUT RAJ NALLA, P.SANTHOSHKUMAR 1 M.tech (Embedded systems), 2 Assistant Professor Department of Electronics and Communication
More informationDEVELOPMENT AND VERIFICATION OF AHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE
DEVELOPMENT AND VERIFICATION OF AHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE N.G.N.PRASAD Assistant Professor K.I.E.T College, Korangi Abstract: The AMBA AHB is for high-performance, high clock frequency
More informationIntroduction to the Qsys System Integration Tool
Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will
More informationDesign and Implementation of A Reconfigurable Arbiter
Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing, Beijing, China, September 15-17, 2007 100 Design and Implementation of A Reconfigurable Arbiter YU-JUNG HUANG,
More informationRASoC: A Router Soft-Core for Networks-on-Chip
RASoC: A Router Soft-Core for Networks-on-Chip Cesar Albenes Zeferino Márcio Eduardo Kreutz Altamiro Amadeu Susin UNIVALI CTTMar Rua Uruguai, 458 C.P. 360 CEP 88302-202 Itajaí SC BRAZIL zeferino@inf.univali.br
More informationDESIGN GUIDELINES FOR THE IMPLEMENTATION OF EMBEDDED NETWORK ON CHIP (NOC) IN FPGAS. Noha Gamal Mohamed
DESIGN GUIDELINES FOR THE IMPLEMENTATION OF EMBEDDED NETWORK ON CHIP (NOC) IN FPGAS By Noha Gamal Mohamed A Thesis Submitted to the Faculty of Engineering at Cairo University in Partial Fulfillment of
More informationEvaluation of NOC Using Tightly Coupled Router Architecture
IOSR Journal of Computer Engineering (IOSR-JCE) e-issn: 2278-0661,p-ISSN: 2278-8727, Volume 18, Issue 1, Ver. II (Jan Feb. 2016), PP 01-05 www.iosrjournals.org Evaluation of NOC Using Tightly Coupled Router
More informationNoc Evolution and Performance Optimization by Addition of Long Range Links: A Survey. By Naveen Choudhary & Vaishali Maheshwari
Global Journal of Computer Science and Technology: E Network, Web & Security Volume 15 Issue 6 Version 1.0 Year 2015 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More informationDLABS: a Dual-Lane Buffer-Sharing Router Architecture for Networks on Chip
DLABS: a Dual-Lane Buffer-Sharing Router Architecture for Networks on Chip Anh T. Tran and Bevan M. Baas Department of Electrical and Computer Engineering University of California - Davis, USA {anhtr,
More informationDesign and Simulation of Router Using WWF Arbiter and Crossbar
Design and Simulation of Router Using WWF Arbiter and Crossbar M.Saravana Kumar, K.Rajasekar Electronics and Communication Engineering PSG College of Technology, Coimbatore, India Abstract - Packet scheduling
More informationHardware Implementation of NoC based MPSoC Prototype using FPGA
Hardware Implementation of NoC based MPSoC Prototype using FPGA Dr. Raaed Faleh Hassan Computer Engineering Techniques, Electrical Engineering Technical college, Middle Technical University, Baghdad- Iraq.
More informationDesign of a router for network-on-chip. Jun Ho Bahn,* Seung Eun Lee and Nader Bagherzadeh
98 Int. J. High Performance Systems Architecture, Vol. 1, No. 2, 27 Design of a router for network-on-chip Jun Ho Bahn,* Seung Eun Lee and Nader Bagherzadeh Department of Electrical Engineering and Computer
More informationSimplifying Microblaze to Hermes NoC Communication through Generic Wrapper
Simplifying Microblaze to Hermes NoC Communication through Generic Wrapper Andres Benavides A. 1, Byron Buitrago P. 2, Johnny Aguirre M. 1 1 Electronic Engineering Department, University of Antioquia,
More informationAC : INTRODUCING LABORATORIES WITH SOFT PROCES- SOR CORES USING FPGAS INTO THE COMPUTER ENGINEERING CURRICULUM
AC 2012-4159: INTRODUCING LABORATORIES WITH SOFT PROCES- SOR CORES USING FPGAS INTO THE COMPUTER ENGINEERING CURRICULUM Prof. David Henry Hoe, University of Texas, Tyler David Hoe received his Ph.D. in
More informationOpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April
More informationSmall Virtual Channel Routers on FPGAs Through Block RAM Sharing
8 8 2 1 2 Small Virtual Channel rs on FPGAs Through Block RAM Sharing Jimmy Kwa, Tor M. Aamodt ECE Department, University of British Columbia Vancouver, Canada jkwa@ece.ubc.ca aamodt@ece.ubc.ca Abstract
More informationDesign and Verification of Five Port Router Network
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 13, Issue 2, Ver. II (Mar. - Apr. 2018), PP 89-96 www.iosrjournals.org Design and Verification
More informationReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
More informationQsys and IP Core Integration
Qsys and IP Core Integration Stephen A. Edwards (after David Lariviere) Columbia University Spring 2016 IP Cores Altera s IP Core Integration Tools Connecting IP Cores IP Cores Cyclone V SoC: A Mix of
More informationFast Flexible FPGA-Tuned Networks-on-Chip
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Fast Flexible FPGA-Tuned Networks-on-Chip Michael K. Papamichael, James C. Hoe
More informationDesign of Efficient Power Reconfigurable Router for Network on Chip (NoC)
Design of Efficient Power Reconfigurable Router for Network on Chip (NoC) J.dhivya 1, J.Jayanthi 1,T.Jayasri 1,G.Karthika devi 1, MrK.B.Sethupathy 2, UG Scholar 1, Assistant Professor 2, Department of
More informationOpenSMART: An Opensource Singlecycle Multi-hop NoC Generator
OpenSMART: An Opensource Singlecycle Multi-hop NoC Generator Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) OpenSMART (https://tinyurl.com/get-opensmart)
More informationDynamic Router Design For Reliable Communication In Noc
Dynamic Router Design For Reliable Communication In Noc Mr. G.Kumaran 1, Ms. S.Gokila, M.E., 2 VLSI Design, Electronics and Comm. Department, Pavai College of Technology, Pachal, Namakkal District, India
More informationMinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems
MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems Mohammad Ali Jabraeil Jamali, Ahmad Khademzadeh Abstract The success of an electronic system in a System-on- Chip is highly
More informationVLSI D E S. Siddhardha Pottepalem
HESIS UBMITTED IN ARTIAL ULFILLMENT OF THE EQUIREMENTS FOR THE EGREE OF M T IN VLSI D E S BY Siddhardha Pottepalem EPARTMENT OF LECTRONICS AND OMMUNICATION NGINEERING ATIONAL NSTITUTE OF ECHNOLOGY OURKELA
More informationInternational Journal of Research and Innovation in Applied Science (IJRIAS) Volume I, Issue IX, December 2016 ISSN
Comparative Analysis of Latency, Throughput and Network Power for West First, North Last and West First North Last Routing For 2D 4 X 4 Mesh Topology NoC Architecture Bhupendra Kumar Soni 1, Dr. Girish
More informationDesign and Verification of Configurable Multichannel
Design and Verification of Configurable Multichannel DMA controller Meet Dave 1, Santosh Jagtap 2 PG Student [VLSI], Dept. of ECE, GTU PG School, Gandhinagar, Gujarat, India 1 Design Engineer, WIPRO limited,
More informationFault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections
Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections A.SAI KUMAR MLR Group of Institutions Dundigal,INDIA B.S.PRIYANKA KUMARI CMR IT Medchal,INDIA Abstract Multiple
More informationNEtwork-on-Chip (NoC) [3], [6] is a scalable interconnect
1 A Soft Tolerant Network-on-Chip Router Pipeline for Multi-core Systems Pavan Poluri and Ahmed Louri Department of Electrical and Computer Engineering, University of Arizona Email: pavanp@email.arizona.edu,
More informationCAD System Lab Graduate Institute of Electronics Engineering National Taiwan University Taipei, Taiwan, ROC
QoS Aware BiNoC Architecture Shih-Hsin Lo, Ying-Cherng Lan, Hsin-Hsien Hsien Yeh, Wen-Chung Tsai, Yu-Hen Hu, and Sao-Jie Chen Ying-Cherng Lan CAD System Lab Graduate Institute of Electronics Engineering
More informationA Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced
More informationNoC Test-Chip Project: Working Document
NoC Test-Chip Project: Working Document Michele Petracca, Omar Ahmad, Young Jin Yoon, Frank Zovko, Luca Carloni and Kenneth Shepard I. INTRODUCTION This document describes the low-power high-performance
More informationVLSI Design of Multichannel AMBA AHB
RESEARCH ARTICLE OPEN ACCESS VLSI Design of Multichannel AMBA AHB Shraddha Divekar,Archana Tiwari M-Tech, Department Of Electronics, Assistant professor, Department Of Electronics RKNEC Nagpur,RKNEC Nagpur
More informationDesign of Router Architecture Based on Wormhole Switching Mode for NoC
International Journal of Scientific & Engineering Research Volume 3, Issue 3, March-2012 1 Design of Router Architecture Based on Wormhole Switching Mode for NoC L.Rooban, S.Dhananjeyan Abstract - Network
More informationLecture 3: Flow-Control
High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor
More informationDesign For High Performance Flexray Protocol For Fpga Based System
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) e-issn: 2319 4200, p-issn No. : 2319 4197 PP 83-88 www.iosrjournals.org Design For High Performance Flexray Protocol For Fpga Based System E. Singaravelan
More informationDesign of an Efficient FSM for an Implementation of AMBA AHB in SD Host Controller
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 11, November 2015,
More informationWhat is Xilinx Design Language?
Bill Jason P. Tomas University of Nevada Las Vegas Dept. of Electrical and Computer Engineering What is Xilinx Design Language? XDL is a human readable ASCII format compatible with the more widely used
More informationTransaction Level Model Simulator for NoC-based MPSoC Platform
Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits & Systems, Hangzhou, China, April 15-17, 27 17 Transaction Level Model Simulator for NoC-based MPSoC Platform
More informationLOW POWER REDUCED ROUTER NOC ARCHITECTURE DESIGN WITH CLASSICAL BUS BASED SYSTEM
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 5, May 2015, pg.705
More informationRe-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Re-Examining Conventional Wisdom for Networks-on-Chip in the Context of FPGAs
More informationPerformance Explorations of Multi-Core Network on Chip Router
Performance Explorations of Multi-Core Network on Chip Router U.Saravanakumar Department of Electronics and Communication Engineering PSG College of Technology Coimbatore, India saran.usk@gmail.com R.
More informationFPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
More informationModule 17: "Interconnection Networks" Lecture 37: "Introduction to Routers" Interconnection Networks. Fundamentals. Latency and bandwidth
Interconnection Networks Fundamentals Latency and bandwidth Router architecture Coherence protocol and routing [From Chapter 10 of Culler, Singh, Gupta] file:///e /parallel_com_arch/lecture37/37_1.htm[6/13/2012
More information4. Networks. in parallel computers. Advances in Computer Architecture
4. Networks in parallel computers Advances in Computer Architecture System architectures for parallel computers Control organization Single Instruction stream Multiple Data stream (SIMD) All processors
More informationISSN Vol.03,Issue.06, August-2015, Pages:
WWW.IJITECH.ORG ISSN 2321-8665 Vol.03,Issue.06, August-2015, Pages:0920-0924 Performance and Evaluation of Loopback Virtual Channel Router with Heterogeneous Router for On Chip Network M. VINAY KRISHNA
More informationConfigurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol. 2, No. 1, March 2013, pp. 27~48 ISSN: 2089-4864 27 Configurable Router Design for Dynamically Reconfigurable Systems based on the
More informationDESIGN AND PERFORMANCE EVALUATION OF ON CHIP NETWORK ROUTERS
DESIGN AND PERFORMANCE EVALUATION OF ON CHIP NETWORK ROUTERS 1 U.SARAVANAKUMAR, 2 R.RANGARAJAN 1 Asst Prof., Department of ECE, PSG College of Technology, Coimbatore, INDIA 2 Professor & Principal, Indus
More informationJUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS
1 JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS Shabnam Badri THESIS WORK 2011 ELECTRONICS JUNCTION BASED ROUTING: A NOVEL TECHNIQUE FOR LARGE NETWORK ON CHIP PLATFORMS
More informationDESIGN AND IMPLEMENTATION OF VLSI SYSTOLIC ARRAY MULTIPLIER FOR DSP APPLICATIONS
International Journal of Computing Academic Research (IJCAR) ISSN 2305-9184 Volume 2, Number 4 (August 2013), pp. 140-146 MEACSE Publications http://www.meacse.org/ijcar DESIGN AND IMPLEMENTATION OF VLSI
More informationSimulation & Synthesis of FPGA Based & Resource Efficient Matrix Coprocessor Architecture
Simulation & Synthesis of FPGA Based & Resource Efficient Matrix Coprocessor Architecture Jai Prakash Mishra 1, Mukesh Maheshwari 2 1 M.Tech Scholar, Electronics & Communication Engineering, JNU Jaipur,
More informationDesign of 3x3 router using buffer resizing technique for 1d and 2d NoC architectures
International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 6, June 214 Design of 3x3 router using buffer resizing technique for 1d and 2d NoC architectures Vivek Raj.K
More informationNOC: Networks on Chip SoC Interconnection Structures
NOC: Networks on Chip SoC Interconnection Structures COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering
More informationAn Efficient Design of Serial Communication Module UART Using Verilog HDL
An Efficient Design of Serial Communication Module UART Using Verilog HDL Pogaku Indira M.Tech in VLSI and Embedded Systems, Siddhartha Institute of Engineering and Technology. Dr.D.Subba Rao, M.Tech,
More informationA Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip
A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip Leandro Möller Luciano Ost, Leandro Soares Indrusiak Sanna Määttä Fernando G. Moraes Manfred Glesner Jari Nurmi {ost,
More informationImproving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration
Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration Hamed S. Kia, and Cristinel Ababei Department of Electrical and Computer Engineering North Dakota State University
More informationStudy of Network on Chip resources allocation for QoS Management
Journal of Computer Science 2 (10): 770-774, 2006 ISSN 1549-3636 2006 Science Publications Study of Network on Chip resources allocation for QoS Management Abdelhamid HELALI, Adel SOUDANI, Jamila BHAR
More informationDigital Systems Design. System on a Programmable Chip
Digital Systems Design Introduction to System on a Programmable Chip Dr. D. J. Jackson Lecture 11-1 System on a Programmable Chip Generally involves utilization of a large FPGA Large number of logic elements
More informationDemand Based Routing in Network-on-Chip(NoC)
Demand Based Routing in Network-on-Chip(NoC) Kullai Reddy Meka and Jatindra Kumar Deka Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Guwahati, India Abstract
More informationFinal Presentation. Network on Chip (NoC) for Many-Core System on Chip in Space Applications. December 13, 2017
Final Presentation Network on Chip (NoC) for Many-Core System on Chip in Space Applications December 13, 2017 Dr. ir. Gerard Rauwerda Gerard.Rauwerda@recoresystems.com NoC round table Network-on-Chip (NoC)
More informationReal Time NoC Based Pipelined Architectonics With Efficient TDM Schema
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam
More informationFault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies. Mohsin Y Ahmed Conlan Wesson
Fault Tolerant and Secure Architectures for On Chip Networks With Emerging Interconnect Technologies Mohsin Y Ahmed Conlan Wesson Overview NoC: Future generation of many core processor on a single chip
More informationDesign of network adapter compatible OCP for high-throughput NOC
Applied Mechanics and Materials Vols. 313-314 (2013) pp 1341-1346 Online available since 2013/Mar/25 at www.scientific.net (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/amm.313-314.1341
More information