Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA

Transcription

1 Design and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA Maheswari Murali * and Seetharaman Gopalakrishnan # * Assistant professor, J. J. College of Engineering and Technology, Tiruchirappalli, India # Principal, Oxford Engineering College, Tiruchirappalli, India Abstract Modern platform Field Programmable Gate Arrays provide larger gate count with increased performance. This feature allows realization of System On Chip on modern FPGAs. When the number of cores increases, the communication demands between cores also increases in SoCs. Hence, Network On Chip has been proposed, to meet out the challenges between the cores. In this paper, a design of low cost, low complexity router for 2D mesh topology is proposed. The low complexity router is implemented on Altera cyclone II FPGA EP2C35F672C6 device. From the implementation results, the proposed router is operated with higher speed, lower area and lower power dissipation compared with previous designs. We have also tested 2 x 2, 3 x 3 and 4 x 4 mesh for the designed router and implemented on cyclone II FPGA. From the implementation results, the proposed one gives better performance in terms of area, speed and power. Key words: FPGA, SOPC, SOC, and NOC 1 Introduction In the last decade there has been an increase in the computation requirement and the number of Intellectuel property (IP) cores for embedded systems. This has fostered the development of high performance embedded platforms that can handle the computational requirements of complex algorithms. With the advancement of semiconductor technology, now-a-days embedded platforms like modern Field Programmable Gate Arrays (FPGAs) have embedded hard and soft core processors, digital signal processors, memories, peripherals, and clock management systems. FPGAs with their Embedded memory and other specialized functionality have become feasible choice to implement a System On Chip (SOC) design in Application Specific Integrated Circuits (ASIC). But for implementation in ASIC, system complexity will increase the requirements for on-chip communication. Hence, the Network On Chip (NOC) has evolved as a solution for addressing this challenge. In addition, FPGA can also take up the NOC model in order to support more complex SOC implementations [1]. For NOC, Router and other logic can be implemented using programmable logic in FPGA, and dedicated NOC elements can lead to better performance and more efficient utilization of on chip FPGA resources [2, 3]. However a certain degree of configurability is required even for embedded NOC support within FPGA. In NOC messages are being routed through routers called switches [4]. IP cores are connected to the router through Network Interface (NI). It is shown in Fig. 1. Connecting IP cores through routers has several advantages than dedicated bus based wiring. It delivers high bandwidth, low latency, and low power [5]. This paper fi, describes a reconfigurable router for 2D mesh topology with modified architecture. Second, the design has also been tested for (2 X 2), (3 x 3) and (4 x 4) 2D mesh network. In Altera tool, SOPC builder generates softcore processor NIOS II (32 bit). The reconfigurable router is implemented using NIOS II processor. The organization of the rest of the paper is as follows: In section 2, the review of previous work related to NOC is discussed. In section 3, the router architecture and design and implementation details are discussed. In section 4, the implementation results and performance analysis are discussed. Finally section 5, summarizes conclusions. Fig X 3 mesh NOC

2 Fig.2. Router Architecture 2 Review of previous work in NOC Literature of NOC shows that most of the work in Network On Chip have been carried out using ASIC, However a few research works have been carried out using FPGA. Important contributions are made to NOC design in [7] but implementation details are not given. Highly scalable Network On Chip for reconfigurable systems has been made in [8]. In this, the design of NOC with virtual cut through switching which has low latency, and it uses large buffer which occupies more silicon area. In [9], design of a router for NOC has been tested for two applications (FFT & Matrix Multiplication). A scalable packet switch based router for 2D mesh and torus topology has been implemented in both FPGA and ASIC in [1]. R. Gindin et al proposed a design of NOC on FPGA and used a standard mesh topology. In this the reconfigurability is limited to routing schemes only. In [11], a router is designed for 2D mesh topology and it has been synthesized on Xilinx FPGA. In this, the design contains limited routing and arbitration and no applications were tested. Also the design consists of routers that evaluated with logic simulation only.this router design [11] is similar to the proposed work in this paper with minar modifications in the FSM Controller and arbitration. All the above said works have complex design. But, in this paper FSM controller is efficiently designed and it occupies less area, which reduces the complexity of the router compared to other designs discussed above. The proposed router and the mesh topologies are implemented and verified using Altera Nios II processor which fi of its kind. 3 Router Architecture Network On Chip consists of three important components Router, Processing Element, Network Interface. The router architecture is shown in Fig. 2. Routing Node is responsible for forwarding the data packets to the destination node. Each router has associated with unique XY address. In a mesh based NOC, a router has five directional channels. They are EAST, WEST, NORTH, SOUTH and a Local channel to which design core is connected. The directional channels connect the

3 router with its neighboring routers and the local channel is used to connect the Processing Element to the router. Processing Element is used to implement the computing functionality in DSP, Microcontroller or memory block, and input/output device controller. Network Interface is an interface between router and design core. It performs two way communications. Fi it collects the data from the design core, then pocketize and adds the header and it pushes the packet into the router. Second it receives the packet from the attached router and depacketizes then sends the data to the Processing Element. Fig. 2 shows the router architecture which contains input port, output port, cross bar switch, arbiter and header decoder.the function of these blocks are explained in the following subsections. 3.1 Input Port Each input port shown in fig. 2 has a FIFO buffer header decoder, and FSM controller. The diagram for input port is shown in Fig. 3(a). FIFO buffer is used to store the data packets. Header decoder is used to decode the destination address. The FSM controller is used to control all the operations. FIFO buffer is implemented using Quartus II Mega wizard function. The size of the FIFO buffer is parameterizable and use 8 bit data width and 32 locations depth to store the packets. When the request comes from neighboring router, if the FIFO buffer is empty the input port sends the acknowledgement (ACK) signal to the neighboring router, after receiving the acknowledgment the neighboring router sends the fi flit. This flit is stored in the buffer and a signal is sent to the header decoder to decode the destination address and then fi flit is sent to the header decoder. Header decoder after decoding the address send a request to an arbiter of the corresponding output port. If the destination address is matched with router address, then the particular data is for that corresponding PE. So the acknowledgement is sent to the arbiter of the local output channel. 3.2 Output Port The output port has an arbiter, and a FSM controller. The diagram for output port is shown in Fig. 3(b). Each output port has two locations depth buffer to store the flit temporarily untill it gets access from the down stream router. In Fig. 3(b), an arbiter is used to resolve the conflicts when more than one requests come to the same output port. If more than one requests comes to a particular output port, the arbiter gives access to only one input port based on round robin priority. The priority is rotated in round robin fashion. The input port which has been granted access to send the remaining flits, then sends the flits to the output port through the cross bar switch. After receiving the fi flit, the output port sends a request to the neighboring router to which it is connected. If ACK comes from neighboring router it sends the flits to next router. 3.3 Cross Bar Switch Fig. 3(b). Output Port The cross bar switch is shown fig. 2. In the proposed router, simultaneously five transmissions are possible. Hence each output port has cross bar switch, and it is implemented using Multiplexer and De-multiplexer. All the input ports are connected to the multiplexer inputs and all the De-multiplexer outputs are connected to all the output ports except its own output port. Each output channel configures the multiplexers and De- multiplexer to establish the appropriate input-output connection. 3.4 Arbiter Fig. 3(a). Input Port The arbiter is shown in fig. 2. The arbiter resolves the problem if requests come from more than one input ports to the same output port and gives access to only one input port using round robin priority. This arbiter assigns priority in round robin fashion in the order east, west, north,

4 south, and local. For example if east input port is assigned with the highest priority and then the next highest priority is assigned to west input port. The arbiter gives access to east input port fi and then west input port and so on. 3.5 Header Decoder The Header decoder in the input port is shown in fig.3(a). In this paper, XY routing algorithm is proposed. Each router has its unique coordinate as address (X,Y). When the header decoder receives the destination address (Rx, Ry), it compares local X coordinate with the destination coordinate Rx, and sends the packet through east channel if Rx > X and through west channel if Rx < X. If Rx is equal to the local X coordinate, then Y coordinate of the router is compared with destination coordinate Ry. If Ry > Y coordinate then the packet is routed through North Channel, else the packet is routed through south channel. If Ry =Y, then the packet is sent through the local channel to the Processing Element. 3.6 SOPC approach for NOC Altera System On Programmable Chip (SOPC) Builder is used to add the design element. Using SOPC builder, the proposed router and all mesh topologies are added to the Nios II processor as the custom block. The program to be executed and verified by writing in C using Nios II IDE [12]. The custom block is invoked as the function in C code. The C program is complied and the configuration bits are downloaded to the FPGA for verification. cyclone II FPGA EP2C35F672C6 device [6]. We used Quartus II 8.1 to synthesis and simulate the RTL design. The area and the speed of the single router, 2 x 2 and 3 x 3 mesh configurations are compared with the design of [11]. The proposed design occupies 2% less area and 5% higher speed. The synthesis results are shown in figure. 4. The simulation result shown in the figure. 5. The RTL schematic view of the proposed router is shown in figure Synthesis Report The implementation of the proposed router occupies 592 LUTs which is only 2% of the total Altera EP2C35F672C6 device. The area occupied by the 2 x 2, mesh is 1374 LUTs which is only 4% of the total area 3 x 3 is 2645 which is 8% of total area, and 4 x 4 mesh is 3634 which is 12% of total area. 4.2 Power Analysis From the implementation results, the power dissipation for single router, 2 x 2 and 3 x 3 are shown in figure 4. The power dissipation is measured using Power play power Analyzer tool available with Altera Quartus 8.1. The power dissipation for the single router design is found to be low compared to [11]. The proposed design consumes only 12mw of thermal power dissipation, 8mw of core static thermal power, and 38mw I/O thermal power dissipation. 4 Implementation Results & Performance Analysis The proposed router is implemented on Altera cyclone II FPGA. It has been designed by writing HDL. The buffer which is used to store the flits decides the area of the router. Hence, the proposed design uses FIFO buffer which is available in Quartus II mega wizard function. The FIFO which is used in this design is a parameterizable. The data width is 8 bit and the depth of the buffer is chosen as 32 locations for testing purpose. The flow control mechanism used is wormhole method which requires less buffer size to store the data. The proposed design uses XY routing algorithm. In the proposed design uses random number generator to generate random numbers. Fi, this random number generator is connected to all the input channels and verified the data from the output channels of a single router. Second, the 2D mesh topology is implemented with the designed router and verified using random number generator for 2 X 2 configurations. The same method has been adopted to test 3 x 3, 4 x 4 configurations of 2D mesh. The designed router has been implemented on Altera Fig. 4. Implementation Result

5 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- 8' h -- ack_from_core ack_from_north ack_from_south req_from_north req_from_south muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ackin_east muxin_east[7..] muxin_local[7..] muxin_west[7..] ack_from_north ackin_south req_from_north muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ack_from_south ackin_north req_from_south muxin_east[7..] muxin_local[7..] muxin_west[7..] muxin_north[7..] muxin_south[7..] ackin_west muxin_east[7..] muxin_local[7..] muxin_west[7..] grnt_to_north req_to_core dataout_local[7..] grnt_to_local reqout_east dataout_east[7..] grnt_to_west reqout_south dataout_south[7..] grnt_to_south reqout_north dataout_north[7..] grnt_to_east reqout_west dataout_west[7..] grnt_south reqin_north grnt_from_east grnt_from_north grnt_from_south grnt_from_west reqin_local grnt_east grnt_north grnt_south reqin_west grnt_north reqin_south grnt_north grnt_south grnt_west reqin_east ack_local ackout_north req_to_local dataout_north[7..] ack_south ackout_west req_to_south dataout_west[7..] ack_to_north ackout_south req_to_north dataout_south[7..] ack_west ackout_east req_to_west dataout_east[7..] ack_to_east ackout_local req_to_east dataout_local[7..] Fig. 5. Simulation result of single router ackin_local ackin_east ackin_south ackin_north ackin_west reqin_east reqin_south reqin_west reqin_local reqin_north local_outputchannel:l1 north_inputchannel:nor1 east_outputchannel:e2 south_outputchannel:sou2 north_outputchannel:nor5 local_inputchannel:l2 west_inputchannel:w1 south_inputchannel:sou1 east_inputchannel_new:ea1 west_outputchannel_new:we1 ackout_north reqout_local dataout_local[7..] reqout_north dataout_south[7..] reqout_south dataout_east[7..] reqout_east ackout_local ackout_west ackout_south dataout_north[7..] ackout_east reqout_west dataout_west[7..] Fig. 6. RTL Schematic view of single route 5 Conclusions The proposed router has been designed for 2D mesh topology which has low complexity and high speed. The single router and 2 x 2, 3 x 3, 4 x 4 mesh topology have been implemented and tested with SOPC using NIOS II processor. From the implementation results, it is found that the proposed router is operated with higher speed and lower area and lower power dissipation compared with the previous design. Our future work is to test the signal processing application using this proposed router. 6. References [1]. Ronny Pau and Naraig Manjikian High level Specification and logic implementation of Single chip Multiprocessor system based on a configurable router IEEE, pp , 28. [2]. H.Elmiligi et al. Introducing OperaNP : A Reconfigurable NoC based platform Proc.27 IEEE Canadian Con. On Electrical and computer Engineering, pp , 27. [3]. R. Gindin et al. NoC based FPGA Architecture and routing In Proc.

6 Intet. Sympo. on Network On chip, pp , 27. [4]. W.J.Dolly and B.Towles Principles and Practices of Interconnect Networks. Morgan Kaufmann Publishers 23. [5]. T.Bjerregaard and S. Mahadevan A survey of Research Practices of Network On Chip ACM Computing Survey Vol- 38, no-1, pp. 1-51, 28. [6]. Altera Inc. http :// [7]. L.Benni and G. D Micheli Network on Chips: A new SOC Paradigm IEEE Computer, vol. 35 no.1, pp. 7-78, 22. [8]. A. Batric et al. Highly Scalable Network On Chip for reconfigurable systems In proceedings of the International Conference on Systems On Chip 23, pp , NOV. 23. [9]. Gaoming Du, Duolo Zhang et al Scalability Study on mesh based Network On Chip IEEE PAWCIIA- 28, pp , 28. [1]. Yahia SALAH, Mohamed ATRI, Rached TOURKI Design of a 2D Mesh- Torus Router for Network On Chip IEEE International Symposium on Signal Processing and Information Technology, pp , 27. [11]. Balasubramanian Sethuraman, et al LiPaR: A Light Weight Parallel Router for FPGA based Network On Chip GLSVLSI, pp , 25. [12]. G.Seetharaman and B. Venkatramani SOC implementation of wave pipelined circuits Proc. of International Conference on Field Programmable Technology, (ICFPT 27) pp.9-16, Japan, 27.