Automatic Generation of 100 Gbps Packet Parsers from P4 Description
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1 Automatic Generation of 100 Gbps acket arsers from 4 Description avel Benáček 1 Viktor uš 1 Hana Kubátová 2 1 Liberouter CESNET 2 Faculty of Information Technology Czech Technical University in rague H 2 RC Workshop, November 2015 Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
2 Introduction OpenFlow is a very popular protocol for realization of SDN (Software Defined Networking) ros and Cons: + Allows us to decouple control and data plane + rovides a way to fill match tables of switches at runtime - Not possible to change set of supported protocols (parsers are fixed) Researchers are looking for a solution of this disadvantage 4 language is the next step in the SDN concept realization Our paper introduces a generator which transforms 4 source to the FGA parser s architecture Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
3 4 rogramming rotocol-independent acket rocessors Language with relatively simple syntax rovides a way to define packet processing functionality of network devices Defines following aspects of packet processing: 1 Header Formats 2 acket arser 3 Table Specification 4 Control rogram packet parser definition match to action mapping 5 Action Specification Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
4 arser structure Two basic types of modules are connected to pipeline 1 rotocol Analyzer - understands one protocol from the protocol stack Data extraction Computes the next protocol type in the stack Computes the next protocol starting offset 2 ipeline - used to tune the final frequency and latency Unified interface for easy connection of modules Input Eth I TC Ethernet Frame I E. 0 Ethernet Analyzer I E. 1 I Analyzer I E. 2 TC/UD Analyzer I E. 3 Eth I TC Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
5 Transformation Algorithm Structure of protocol analyzer is generated from the 4 s Header Format arser s structure is inferred from 4 s acket arser Basic idea of parser s structure identification We have to identify the latest usage of the protocol in the parser. Algorithm for the identification of the latest usage: DFS (Depth First Search) This can be done in arser Graph Representation (GR) Directed acyclic graph Represents relations between protocols Created from 4 description Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
6 Transformation Algorithm - Example ICMv6 3 Iv6 2 Unknown TC 3 Eth 0 VLAN 1 Unknown Iv4 2 UD 3 Logical model (GR) Unknown ICM 3 Unknown hysical model Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
7 Results We have tested two protocol stacks: Simple L2 - Ethernet, Iv4/Iv6, TC/UD, ICM/ICMv6 Full - Ethernet, 2x VLAN, 2x MLS, Iv4/Iv6, TC/UD, ICM/ICMv6 ossible optimizations: Automatic - Optimizations of internal parser s structure O1 - Offset bus optimization O2 - Multiplexer optimization Manual - Tweaked 4 program (O3) We performed synthesis for our implementation platform: Equipped with Xilinx Virtex 7 FGA Suports 100 Gbps Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
8 Results - Latency hand,pareto,simple L2 4,O2,pareto,simple L2 hand,pareto,full 4,O2,pareto,full 50 Latency [ns] Throughput [Gbps] Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
9 Results - Resources hand,pareto,simple L2 4,O2,pareto,simple L2 hand,pareto,full 4,O2,pareto,full Slice LUT [-] Throughput [Gbps] Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
10 Conclusion We implemented and evaluated our generator of parsers arsers are capable to process 100 Gbps From presented work we can infer following important results: 1 Ability to generate parsers with equal functionality in shorter time 2 Generated parsers aren t significantly worse than hand optimized versions created by a professional with many years of experience in HDL coding Future work: Deparser - construction of packets Match+Action tables - general processing of extracted data Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
11 Thank you for your attention avel Benáček Visit our business partner in booth #3011 Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
12 rotol Analyzer (3) Input rotocol rotocol Analyzer Data Extractor Next rotocol Decoder (6) Output rotocol (1) Input Data Data Extractor (4) Extracted Data (2) Input O set Data Extractor + Length Gen. (5) Output O set Benáček, uš, Kubátová 100 Gbps acket arser from 4 H 2 RC / 12
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