Sharing Tunable Wavelength Converters in AWG-based IP Optical Switching Nodes

Transcription

1 Sharing Tunable Wavelength Converters in AWG-based IP Optical Switching Nodes Achille Pattavina, Marica Rebughini, Antonio Sipone Dept. of Electronics and Information, Politecnico di Milano, Italy Abstract This paper deals with the design of an optical packet switch architecture adopting an arrayed waveguide grating device for packet routing. Due to the high cost of optical components, the node structure proposed here is equipped with a pool of tunable wavelength converters fully shared among all input channels. An analytical model is developed that allows us to evaluate the packet loss performance of a bufferless version of such structure. The model accuracy is assessed by means of computer simulation. Index Terms All-optical networks, arrayed waveguide grating (AWG), tunable wavelength converter (TWC), internet protocol (IP), optical packet switching (OPS). I. INTRODUCTION In the latest years due to the growth in Internet Protocol (IP) traffic and by the introduction of new broadband services, telecommunication networks have been demanding an increase of transmission capacity. Nowadays, the routing of the traffic flows in transport networks occur by processing data electronically and by transmitting them in optical fibers; optics is exclusively used at the physical layer. Considerable research is currently devoted to design IP fully-optical backbone networks, in order to relieve the capacity bottleneck of classical electronic-switched networks. In the last ten years, optical Dense Wavelength Division Multiplexing (DWDM) has been developed, which has made available commercial systems providing impressive transmission capacities: one Terabit per second per fibre, over distances on the order of 100 km are feasible nowadays. In WDM-routed networks, a wavelength is assigned to each connection so that all traffic is handled in the optical domain, without any electrical processing on transmission. Unfortunately, today optical devices used in market equipment are still too crude to allow packet-by-packet operation. An interesting solution which tries to represent a balance between circuit switching low hardware complexity and packet switching efficient bandwidth utilization is the optical burst switching [1], [2]. In an optical burst switching system, the basic units of data transmitted are bursts, made up of multiple packets, which are sent after control packets, carrying routing information, whose task is to reserve electronically the necessary resources on the intermediate nodes of the * Work supported by EU IST Network of Excellence e-photon/one. transport network. Such operation results in a lower average processing and synchronization overhead than optical packet switching, since packet-by-packet operation is not required. However packet switching has a higher degree of statistical resource sharing, which leads to a more efficient bandwidth utilization in a bursty, IP-like, traffic environment. We address here the long-term view of a full packet switching network performing IP packet transport, in which optical operations are performed as much as possible exploiting the currently available optical device technology. Apparently most of the operations related to the packet header processing need to be done nowadays in the electronic domain. This paper deals with the architecture of an optical packet switching node first proposed in Refs. [3] [4], which is equipped with a fiber delay line stage used as an input buffer for optical packets. Starting from the structure proposed in [5], we propose a modified structure of the switching core of the node equipped with tunable wavelength converters shared among the input lines. By varying the number of TWCs we will find the optimum wavelength converter pool size to minimize unit capacity cost. The paper is organized as follows. Sections II and III describe the optical network architecture we envision and the proposed architecture of an optical packet switching node. Section IV provides an analytical model for the switch and a comparison of the different switch configurations in terms of traffic performance. II. NETWORK ARCHITECTURE The architecture of the optical transport network we propose consists of N optical packet-switching nodes, which are linked together in a mesh-like topology. A number of edge systems (ES) interfaces the optical transport network with IP legacy (electronic) networks (see Fig. 1). An ES receives packets from different electronic networks and performs optical packets generation. The optical packet is composed of a simple optical header, which comprises the bit destination address, and of an optical payload made of a single IP packet, or, alternatively, of an aggregate of IP packets. The optical packets are then buffered and routed through the optical transport network to reach their /05/$20.00/ 2005 IEEE 229

2 Fig. 2. Optical packet-switching node general architecture. Fig. 1. The optical transport network architecture. destination ES, which delivers the traffic it receives to its destination electronic networks. At each intermediate node in the transport network, packet headers are received and electronically processed, in order to provide routing information to the control electronics, which will properly configure the node resources to switch packet payloads directly in the optical domain. The transport network operation is asynchronous; that is, packets can be received by nodes at any instant, with no time alignment. The internal operation of the optical nodes, on the other hand, is synchronous or slotted,since the behaviour of packets in an unslotted node is less regulated and more unpredictable, resulting in a larger contention probability. Header and payload of a packet are transmitted serially, where header duration is equal to T H and payload duration to T P. At each intermediate node in the transport network, packet headers are received and electronically processed, in order to provide routing information to the control electronics, which will properly configure the node resources to switch packet payloads directly in the optical domain. The guard times (T G ) are needed in order to avoid payload/header superposition, because of the clock jitter in the transmission phase. Hence, the total overhead time is equal to T OH = T H + 2T G. Both header and payload are assumed to be transmitted at 10 Gb/s rate. An overhead time T OH = 8 ns has been chosen, with header duration T H = 6 ns and guard times T G = 1 ns. Consequently, an interval of 8 ns is available to perform switching, and a 10-bit jitter at 10 Gb/s is tolerated in header regeneration. Furthermore, this value of T OH implies a 60 bit header. In [6], a 10 Gb/s optical packet receiver is demonstrated, using a 40 bit long preamble. Therefore, the remaining 20 bits will carry packet information: 5 bits are reserved for packet length (expressed in time slots, for a maximum value of = 31 time slots), and the remaining 15 bits for the destination ES address (up to a maximum of 2 15 edge systems). In our model we choose a time slot duration (T ) equal to the duration of an optical packet whose payload consists of the smallest transmission control protocol TCP/IP packet (i.e., 320 bits, the size of an IP packet carrying a TCP acknowledgement). Time-slot duration is therefore equal to T = T OH + 32 = 40 ns. Due to our assumption of slotted operation, it takes a number (T OH + T P )/T of slots to switch (and transmit) an optical packet with overhead time T OH and payload time T P. Under these assumptions, a 1500-byte packet (i.e., the maximum Ethernet payload length) will fill in a 31 time-slot long optical packet. III. NODE ARCHITECTURE The general architecture of a network node is shown in Fig. 2. It consists of three stages: a first stage of channel demultiplexing, a second stage of switching and a third stage of channel multiplexing. The node is fed by N incoming fibers each having W wavelengths. In the first stage the incoming fiber signals are demultiplexed and G wavelengths from each input fiber are fed into each one of the W/G second-stage switching planes, which constitute the switching fabric core (W/G = 2 in Fig. 2). Once signals have been switched in one of the parallel planes, packets can reach every output port through multiplexing carried out in the third stage using any of the G wavelengths that are directed to each output fiber. We note that the number of inlets of each third-stage multiplexer varies, depending on the specific structure of the switching planes. Wavelength conversion must be used for contention resolution, since at most G packets can be concurrently transmitted by each second-stage plane on the same output link. The detailed structure of one of the W/G parallel switching planes is presented in Fig. 3. It consists of three main blocks: an input synchronization unit, as the node is slotted and incoming packets need to be slot-aligned, a fiber delay lines (FDL) unit, used to store packets for contention resolution, and a switching matrix unit, adopted to achieve the switching of signals. 230

3 Fig. 3. Detailed structure of one of the W/G parallel switching planes. These three blocks are all managed by an electronic control unit which carries out the following tasks: optical packet header recovery and processing; managing the synchronization unit in order to properly set the correct path through the synchronizer for each incoming packet; managing the tunable wavelength converters inside the switching matrix, in order to properly delay and route incoming packets. The details of the synchronization and of the FDL unit can be found in [5]. We simply recall here that the delay lines are used as an optical scheduler. This policy uses the delay lines in order to schedule the transmission of the maximum number of packets onto the correct output link. Given the maximum achievable delay slot, for each switch input + 1 delay lines are needed, with delays growing from 0 to. Moreover, NW multiplexers and demultiplexers with + 1 input and output ports are needed to perform packet buffering. Once packets have left the FDL unit, they enter the switching matrix stage in order to be routed to the desired output port. This is achieved using a set of tunable wavelength converters combined with an arrayed waveguide grating (AWG) wavelength router [7]. By using optical delay lines (ODL) we can further delay the packets that have already arrived in the switching matrix unit, by thus accomplishing shared queueing. This solution, if carefully implemented, enables a more efficient node resource utilization and also allows us to introduce different priority classes of service for packets flowing in the network. In fact, if a high priority packet contends with a low priority packet for an output, it is possible to further delay the latter packet, even if it has already left the fiber delay line unit. This feature is very important, since the need for management different priority classes is growing, due to the increase of new applications. Now we deal with delay lines management. Every delay line introduces a constant delay equal to D rec slots. A packet is delayed by D in slots in the FDL unit and it can be stored r times in the shared buffer, therefore making at most r loops in the output delay lines. The scheduling algorithm tries to minimize the sum D in + rd rec, starting from r = 1 and stepping up to r if necessary: it looks for the values of D in, rd rec which let the packet be transmitted as soon as possible. The search goes on until: the packet is transmitted because, for a certain value of r, a valid value of the couple (D in, rd rec ) is found; the packet is lost because there are no valid values of the couple (D in, rd rec ), for any of the possible values of r with 1 r r max, being r max the maximum number of loops permitted. Moreover in order to avoid that long packets engage more than one loop port at a given time, only packets shorter than the ODLs can use the shared buffer more than once. Because of the great utilization and the high cost of tunable wavelength converters (TWC) in this structures, this work is aimed at analyzing a switch architecture in which the TWCs are shared among the inputs fibers. The number of TWCs may be minimized so that only those TWCs strictly needed to achieve given performance requirements are employed. In the following sections we will consider single-plane structures, that is W = G, in which the switching matrix has N W inlets and N W outlets. The extension to multi-plane nodes is easily achieved for the first structure by selecting W = W/G. Before proceeding to structures description we remark that, assuming r (with r NW ) as the total number of shared TWCs in the pool, if more than r packets arrive to AWG inputs events of packet 231

4 1 N Fig. 4. pool. Fully Shared TWC pool R G G TWC: Tunable Wavelength Converter AWG (NG+R)x(NG+R) R G G Fiber delay lines Structure B switching matrix with shared buffer and shared TWC blocking occur because we assume that every packet needs wavelength conversion. The simplest basic (B) switching matrix structure proposed in Ref. [5] and extended in Ref. [3] to accomplish shared buffering is modified here introducing a pool of shared TWCs and is shown in figure 4. It consists of at most 2NW + R TWCs (some of them can be shared) and of an AWG with size (NW +R) (NW +R), being R the reserved AWG ports for optical delay lines. The number of output WDM channels in this switching plane remain unchanged compared with structure without ODLs. Only one packet is routed to each AWG outlet and this packet, if addressed to an output fiber, must finally be converted to one of the wavelengths used in the WDM channel, paying attention to avoid contention with other packets of the same channel. Obviously, by setting R = 0 a B structure without ODLs is obtained. More complex and efficient switch structures based on AWG can be considered, by exploiting for example the concurrent wavelength routing capability of each AWG input port (see, e.g., [5]). Evaluation of such enhanced architectures is carried out in [8]. IV. PERFORMANCE EVALUATION In order to evaluate the traffic performance of the switch architecture, we will first examine the packet loss probability of a simple configuration, where an analytical model can easily be obtained. We will later evaluate the performance of buffered structures by means of computer simulation. A. Switching Capability We develop now an analytical model of the structure B of switching matrix described in the previous section. In 1 N order to evaluate the switching capabilities of the switch, the following assumptions are made: no input or output buffering is performed; packet length is constant, equal to the time-slot duration; every packet needs to be converted to a different wavelength in order to be transmitted. We can express the packet loss probability P loss as follows [9]: P loss = E[N k l ] E[N k o ] (1) where E[x] denotes the expected value of the random variable x and No k is the number of packets offered to the output port k; it is easy to show that: E[N k o ] = W ρ (2) Nl k is the number of lost packets offered to the output k; Since r (0 r N W ) represents the total number of TWCs, for E[Nl k ] we can write by applying the total probability theorem with and E[N k l ] = NW x=0 t=0 r E[Nl k A k = x, C k = t] Pr{C k = t} Pr{A k = x} (3) Pr{A k = x} = β(nw, x, ρ/n) (4) E[N k l A k = x, C k = t] = x min(t,w) (5) where C k and A k respectively represent the number of TWCs available and the number of incoming packets addressed to the output fiber k. Assuming C k and A k statistically independent we can express C k considering that the available number of TWCs depend on the selection order with which the manager of the pool of TWCs selects the fiber: Pr{C k = t} = N Pr{C k = t D k = j}pr{d k = j} (6) j=1 where D k is the random variable indicating the selection order of the output fiber k by the manager of the pool of shared TWCs. If we assume that the selection is accomplished according to a uniform distribution, we can write: Pr{D k = j} = 1 j = 1,..., N. (7) N The conditional probability appearing in Eq. (6) changes according to the selection order of the output fiber and 232

5 Pr{C k = t/d k = j} = NW x i=r 1 if j = 1 and t = r 0 if j = 1 and t < r Pr{ j 1 f=1 A f = r t} if j > 1 Pr{ j 1 f=1 A f = i} if j > 1 and t = 0 and r > 0 1 if j > 1 and t = 0 and r = 0 (8) Node B, AWG 16x16, N = 2, W = 8, P len = 320 bit Node B, AWG 16x16, N = 2, W = 8, P len = 320 bit 10-5 Analytical, ρ=0.2 Analytical, ρ=0.4 Analytical, ρ=0.6 Analytical, ρ=0.8 Simulation, ρ=0.2 Simulation, ρ=0.4 Simulation, ρ=0.6 Simulation, ρ= Analytical, WCR=25% Analytical, WCR=50% Analitycal, WCR=75% Analytical, WCR=100% Simulation, WCR=25% Simulation, WCR=50% Simulation, WCR=75% Simulation, WCR=100% Load Fig. 5. versus the number of TWCs. Fig. 6. versus the average load per wavelength. the available number of TWCs; its expression is given by Eq. (8). (P loss ) of the proposed structure B is now evaluated using the previous analytical model and computer simulation. The size of each TWC pool is denoted by the ratio between the number of TWCs in the pool and the maximum number NW of TWCs; such ratio is denoted as Wavelength Converter Ratio (WCR) [10]. Figs. 5 and 6 show the loss probability as a function, respectively, of the number of TWCs and of the average load per wavelength, when employing a single-plane structure with N = 2 fibers and W = 8 wavelengths each. Logically the overall trend is that P loss decreases by increasing the employed number of TWCs. Nevertheless, this effect gradually slows down in the region where the number of TWCs is sufficiently high. These plots also allow us to remark how the point where the asymptote for loss probability begins shift according to the offered load per wavelength: in particular a shift towards higher number of TWCs corresponds to the increase in the load. This behaviour is justified by the fact that by increasing the load of the network will imply a higher number of TWCs in order to reach the asymptote. At the same way a decrease in the number of converters (considering the hypothesis of high load) corresponds to a sharp increase in loss probability. We can now analytically calculate the equation of the asymptote on which the loss probability curves converge when increasing the number of TWCs until to their maximum number for the examined structure. By reconsidering the loss probability definition of Eq. 1, we can see that the average number of offered packets does not change (Eq. 2), while the average number of lost packets varies: NW E[Nl k ] = E[Nl k X = i]pr{x = i} (9) i=0 any single element in the sum can be further expressed as: { E[Nl k X = i] = 0 if i W (10) i W if i > W while Pr{X = i} = β(nw, i, ρ/n) (11) By using the expressions given in Eqs. 10 and 11 we can rewrite the equation of asymptote as follows: NW i=w +1 (i W )β(nw, i, ρ/n) P loss = (12) W ρ B. Performance Results Now we show some traffic performance results given by the different node architecture configurations obtained through computer simulation. Packet interarrival has been modelled as a Poisson process with negative exponential interarrival times. Based on measurement of real IP traffic [11], 233

6 Node B, AWG 8x8, N = 2, W = 4, = 0, R = 0 Node B, AWG 8x8, N = 2, W = 4,, R = 0 WCR = 25 % WCR = 50 % WCR = 75 % WCR = 100 % WCR = 25 % WCR = 50 % WCR = 75 % WCR = 100 % Offered load, ρ Offered load, ρ Fig. 7. versus load with = 0. Fig. 8. versus load with. the following packet length distribution has been assumed: p 0 = P (L = 40 bytes) = 0.6 p 1 = P (L = 576 bytes) = 0.25 p 2 = P (L = 1500 bytes) = 0.15 In this traffic model, the resulting average packet length is 393 bytes. 1) Structure B without ODLs: In this section we only consider switching matrix without the implementation of ODLs, therefore we analyze structures with the TWCs pool and input buffer, whose delay capability is denoted by D in. Figures 7, 8 and 9 show the packet loss probability varying the offered load for increasing sizes of maximum buffer depth = {0, 2T, 8T }. As we can see, when the offered load is kept sufficiently low, e.g. below ρ = 0.3, 75% of WCR ratio is enough to get almost all of the performance gain given by wavelength conversion. Using more TWCs would become useless. In the following figures 10, 11 and 12, we represent packet loss probability varying the number of TWCs for different load levels, i.e. ρ = 0.2, 0.4, 0.6. In this way the input buffer role clearly emerges: only when WCR exceeds 50% the input buffer allows an improvement in performance. 2) Structure B with ODLs: We consider now an 12x12 AWG for structure B with N = 2, and W/G = 2 switching plane. The packet loss performance as a function of the offered load is shown in figure 13 with WCR=100%. Comparing different configurations with various shared buffer depth, we note a better performance when the buffer increases its depth. Nevertheless we note that a node without buffer gives better result for medium loads. This fact can be explained considering that in the bufferless structure the contention resolution in wavelength domain is more likely to occur than in a buffered one; so the effect of the shared buffer becomes important especially Node B, AWG 8x8, N = 2, W = 4,, R = Offered load, ρ WCR = 25 % WCR = 50 % WCR = 75 % WCR = 100 % Fig. 9. versus load with. = 0 = T Node B, AWG 8x8, N = 2, W = 4, R = 0, ρ = Fig. 10. versus number of TWCs for ρ =

7 Node B, AWG 8x8, N = 2, W = 4,R = 0, ρ = 0.4 Node B, AWG 12x12, N = 2, W=12,, WCR = 100 % = 0 = T G = 6, R = Offered Load, ρ Fig. 11. versus number of TWCs for ρ = 0.4. Fig. 13. versus load with WCR = 100%. Node B, AWG 8x8, N = 2, W = 4, R = 0, ρ = Node B, AWG 12x12, N=2, W=12, 12 G = 6, R = 0 = 0 = T Average delivered packets delay [T] Fig. 12. versus number of TWCs for ρ = Offered Load, ρ Fig. 14. Average delivered packets delay for structure B. when load increases. In fact the channel grouping benefits become greater when the offered load decreases. On the other hand, for D rec, node performance has a marked improvement for all values of the offered traffic. In this case, the large buffer capacity is able to balance the reduced capability of the contention resolution in the wavelength domain. However, this loss probability improvement is paid through a notable increase of average delivered packets delay, as shown in fig. 14. In fig. 15, where the packet loss probability is represented as a function of number of wavelength converters for a fixed load (ρ = 0.4), we note that rising WCR to 75% no significant improvement is obtained expanding the buffer depth. V. CONCLUSIONS In this work we have considered a switch architecture for IP optical switching whose main feature is the sharing Node B, AWG 12x12, N = 2, W=12, R = 6,, ρ = 0.4 D rec D rec D rec D rec Fig. 15. versus number of TWCs for ρ =

8 of tunable wavelength converters. An analytical model for this structure has been developed; the numerical results of this model follows nicely simulations results. Buffering has also been considered, accomplishing either input or shared queueing. We have shown that it is possible to use a shared wavelength converter pool reducing implementation cost of nodes, preserving same performances. Further studies are still to be carried out to evaluate how sharing of wavelength converters affect different structures of the switching node. REFERENCES [1] M. Yoo and C. Qiao, Just-Enough-Time(JET): A High Speed Protocol for Bursty Traffic in Optical Networks. in Proc. IEE/LEOS Tech. for a Global Info Infrastructure, Aug. 1997, pp [2] C. Qiao, Labeled Optical Burst Switching for IP-over-WDM Integration, IEE Commun. Mag., pp , Sep [3] S. Bregni, G. Guerra, and A. Pattavina, Optical Packet Switching of IP Traffic, in Proceedings of 6 th Working Conference on Optical Network Design and Modeling (ONDM), [4], Node Architecture Design for All-Optical IP Packet Switching, in Proceedings of Globecom, Nov [5], Architectures and Performance of AWG-Based Optical Switching Nodes for IP Networks. IEEE Journal on Selected Areas in Communications, vol. 21, no. 7, pp , Sep [6] H. Nishizawa, Y. Yamada, K. Habara, and T. Ohyama, Design of a 10-Gb/s Burst-Mode Optical Packet Receiver Module and Its Demonstration in a WDM Optical Switching Network, IEEE Journal of Lightwave Technology, vol. 20, no. 7, pp , Jul [7] C. Parker and S. Walker, Design of Arrayed-Waveguide Gratings Using Hybrid Fourier-Fresnel Transform Techniques. IEE Journal on Selected Topics in Quantum Electronics, vol. 5, pp , [8] A. Pattavina, M. Rebughini, and A. Sipone, Optical Switching Nodes for IP Traffic Based on AWG and Shared Wavelength Conversion, submitted for publication. [9] V. Eramo and M. Listanti, Packet Loss in a Bufferless Optical WDM Switch Employing Shared Tunable Wavelength Converters. IEEE Journal of Lightwave Technology, vol. 18, no. 12, pp , Dec [10] M. Nord, Waveband Based Multi-Plane Optical Packet Switch With Partially Shared Wavelength Converters. in Proceedings of 6 th Working Conference on Optical Network Design and Modeling (ONDM), 2004, pp [11] K. Thompson, G. J. Miller, and R. Wilder, Wide-Area Internet Traffic Patterns and Characteristics, IEEE Network Magazine, pp , Nov