Heterogeneous, Distributed and Scalable Cache-Coherent Interconnect

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1 Heterogeneous, Distributed and Scalable Cache-Coherent Interconnect Scale system performance faster than Moore s Law will currently allow K. Charles Janac MSoC Conference 2016 Nara, Japan, July 13, 2016 resident and CEO, Arteris Copyright 2016 Arteris

2 Arteris customers and their SoCs Current as of 8 June 2016 Very Large SoC Maker Major Automotive OEM Major Auto & CE SoC Maker NX Major System OEM Toshiba Japan System OEM Automotive SoC Maker Japan Tier 1 SoC Maker Large Drone Maker Major SSD Vendor Major I rovider Defense Contractor Defense Contractor Major SSD Vendor Defense Contractor Silicon Foundry 241 Design Starts 108 SoCs Shipping 500M+ SoCs Units in Systems M M M 48 M 509 M Copyright 2016 Arteris 2

3 Arteris Interconnect I: The easiest and most cost effective way to build differentiated SoCs CU Subsystem A57 A57 A57 A57 A53 A53 A53 A53 Design-Specific Subsystems GU Subsystem 3D Graphics DS Subsystem (A/V) I I I FlexWay Interconnect I Application I Subsystem I I FlexWay Interconnect AES 2D GR. MEG L2 cache L2 cache I I I I I I Etc. Ncore Cache Coherent Interconnect FlexNoC Interconnect InterChip Links TM Memory Scheduler Memory Controller Wide IO HY L DDR DDR3 HY USB 3 USB 2 HY 3.0, 2.0 Subsystem Interconnect CIe HY High Speed Wired eripherals Ethernet HY WiFi GSM LTE LTE Adv. Wireless Subsystem CRI Crypto Firewall (CF+) RSA- SS Cert. Engine HDMI MII Display MU JTAG Memory Subsystem Arteris Interconnect I roducts Security Subsystem I/O eripherals Copyright 2016 Arteris, Strictly Confidential 3

4 Cache Coherency rimer Copyright 2016 Arteris 4

5 Cache coherency concept Coherent Agent Coherent Agent Cache Coherency Cache Memory Resource Source: Wikipedia Copyright 2016 Arteris 5

6 Coherent read example cache hit ❶ Coherent Read Consumer Cache ($) Cache ($) Cache ($) ❸ Data send roducer Coherent Agent Directory Coherent Agent ❷ (s) Coherent Agent roxy Cache ($) Bridge Coherent Memory CCTI Coherent Memory Bridge Subsystem Copyright 2016 Arteris 6

7 Coherent read example cache miss Consumer ❶ Coherent Read Cache ($) Cache ($) Cache ($) Coherent Agent Directory ❹ Data Send ❷ (s) Coherent Agent Coherent Memory CCTI ❸ Memory Read Coherent Agent Coherent Memory roxy Cache ($) Bridge Bridge Subsystem Memory Copyright 2016 Arteris 7

8 Who needs heterogeneous cache coherency? Copyright 2016 Arteris 8

9 How did we get here? Sources: ITRS, Gartner, ARM We can t improve performance and economics by transistor scaling. No more free lunch! Copyright 2016 Arteris 9

10 Cache coherency has been available Copyright 2015 Arteris 10

11 Keep this in mind Software Simplicity rocessors & Accelerators Subsystems SoC Architecture Input/Outputs Interconnects Moore s Law Copyright 2016 Arteris 11

12 Copyright 2016 Arteris 12

13 Copyright 2016 Arteris 13

14 We need parallel computing to squeeze the most out of a process node System Software Hardware HW + SW efficiency Acceleration / CU offload Bandwidth & latency efficiency Simplicity: Single view of memory Reuse existing SW Software yield : Useful work per LOC Optimize for dissimilar HW data sharing Efficiency: Useful work per area (or mah) But we need to address systemic complexity in addition to scale complexity Copyright 2016 Arteris 14

15 Heterogeneous cache coherency enables simpler parallel computing Multiple Coherence Models I from different vendors / teams Logical coherence protocols / models Generic system coherence model using lightweight messaging layer Dissimilar Caching Agents hysical cache organization, transaction table sizes Multiple configurable snoop filters save area I as coherent peers Data sharing between noncoherent agents and coherent agents Data sharing between noncoherent agents Multiple configurable proxy caches minimize communication through DRAM Copyright 2016 Arteris 15

16 Where is heterogeneous cache coherency relevant? Next generation automotive (ADAS) Mobility applications processors Virtual reality IoT Servers and others Arteris Confidential 16

17 Heterogeneous Cache Coherency Implementation Copyright 2016 Arteris 17

18 Ncore Cache Coherent Interconnect I Coherent Agents Agents CU Cluster Cache ($) GU Cache ($) Image rocessing Display rocessing Subsystems eripherals Agents DRAM SRAM Memory Agents Copyright 2016 Arteris 18

19 Ncore interconnect architecture Cache ($) Cache ($) Directory Coherent Agent Coherent Agent roxy Cache ($) Bridge Coherent Memory CCTI Coherent Memory roxy Cache ($) Bridge Subsystem Copyright 2016 Arteris 19

20 True heterogeneous coherency With multiple configurable snoop filters Directory Cache ($) Cache ($) Coherent Agent Coherent Memory Cache coherent agents can have very different behaviors Cache organization Coherent Agent Coherency models Workloads Coherent Memory roxy Cache ($) Bridge(s) Associating caching agents that share CCTI common properties with individual Domain snoop filters can consume less die area than a monolithic snoop filter Copyright 2016 Arteris 20

21 Multiple snoop filters are more area-efficient than one A B Cache ($) Cache ($) C Cache ($) D Cache ($) Traditional Approach Ncore Approach REQ Monolithic (X) A B C D REQ #1 (Y) #2 (Z) A B C D Multiple snoop filters are smaller: area(y+z) < area (X) Copyright 2016 Arteris 21

22 Higher performance with non-coherent I Sharing between non-coherent & coherent agents Using configurable proxy caches Consumer Cache ($) Cache ($) ❷ roducer ❸ ❶ Directory Coherent Agent Coherent Agent ❺ roxy Cache ($) Bridge ❹ Coherent Memory CCTI Coherent Memory roxy Cache ($) Bridge Subsystem Copyright 2016 Arteris 22

23 Sharing between non-coherent agents Using configurable proxy caches ❷ roducer Consumer Cache ($) Cache ($) ❶ ❸ Directory Coherent Agent Coherent Agent roxy Cache ($) Bridge ❹ Coherent Memory CCTI Coherent Memory roxy Cache ($) Bridge Subsystem Copyright 2016 Arteris 23

24 V voltage power A async F firewall G2D VidDec VidEnc HDMI Modem GU DMA DS Q A Q A A A A53/0 A53/1 A72/0 A72/1 MMU BT WiFi Debug USB2 USB3 Audio MCU Crypto CIe SI MMU Vid NCTI MMU MMU MMU ACELite CAIU ACE CAIU ACE CAIU ACE CAIU ACE CAIU A A A A A A A A A A A A A Q interconnect subsystem OBS NCBU +proxy $ Coherent interconnect subsystem CCTI DIRU 0 F CSR DIRU 1 CSI DSI IS CU little dbg CU big dbg SatNav USB3 WiFi NVM BT NFC SATA emmc Flash Sys ctrl Other IO UFS Sensor CMIU OBS ROB F F F F F Sched 0 Sched 1 Mem NCTI Sched 2 Sched 3 SRAM DRAM DRAM DRAM DRAM

25 LL dbg MCU DDR HY 3 Sched 3 LL sat nav DDR HY 1 Sched 2 crypto UFS LL sensor USB 3 USB 2 CIe video decode video encode audio MU Vreg modem CU little CU big other I/O sys ctrl HDMI CSI DSI SI IS DMA Sched 1 GU G2D NVM SRAM proxy $ DIRU 1 Sched 0 ROB DS DIRU 0 SATA Flash emmc NFC LL DDR HY 2 WiFi LL DDR HY 0 BT LL

26 Heterogeneous cache coherency required to maintain system power/performance trends Ncore Cache Coherent Interconnect I is targeted at heterogeneous SoCs. Benefits Scalability Configurability Area efficiency High performance Optimal power consumption Major Technologies Multiple configurable snoop filters Multiple configurable proxy caches Modular distributed architecture RESULT: Custom-configured interconnect I that meets exact system requirements Copyright 2016 Arteris 26

27 What s next? Copyright 2016 Arteris 27

28 Upcoming challenges and trends Management of physical constraints Consolidation/de-consolidation of coherency protocols Hardware layer security Hardware layer resilience Lower power, lower power, lower power High performance Off-chip coherency 2.5/3D Constantly lowering the cost of coherency Copyright 2016 Arteris 28

29 Copyright 2016 Arteris 29

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