Signal Integrity Analysis

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1 Mixed Signal Expands Channel SI Horizon Modeling for Signal Integrity Analysis Saliou DIEYE Agilent EESOF EDA Riccardo GIACOMETTI Agilent EESOF EDA Page

2 Agenda Analog Modeling DSP Modeling Mixed domain (analog + DSP) co-simulation Page

3 Typical Channel (DSP and ANALOG component models) Transmit Bits Encoder / Pre-Emphasis/ Serializer/ TX Signal pre-conditioning (DSP components) Die Package Card Driver Driver I/O (ANALOG active) RX Signal Recovery (DSP components) Card Die Package Card High speed Connectors Receiver Physical Interconnects ANALOG PASSIVES Physical Channel Received Bits Equalizer/CDR/ De-Serializer/ RX (I/O ANALOG active) Page

4 Modeling Analog devices Passive components Passives Die Driver Trace PCB Trace Receiver Die Package & Balls PCB For passive structures S-parameters Can be obtained from Measurement or EM simulation Analytical models obtained from software package libraries IBIS models where available. SPICE models lumped component based models Page 4

5 Transmission Line models for PCB traces Account for impedance, delay, conductor loss, dielectric loss, and crosstalk Analytical microstrip, stripline models Multilayer Interconnect Models use a built-in field-solver Page 5

6 Measurement based modeling 0 (54mm) 5 (8mm) 0 (508mm) 0 (76mm) 40 (06mm) Touchstone Files CITI Files MDIF Files TDR or VNA Measurements Page 6

7 EM based modeling: D Planar EM Simulation Efficient, accurate simulation of board interconnects mesh density = 50, 80, 00, 0, 50 strip via slot Accurate simulation of Via holes now possible with Method of Moments Planar EM Page 7

8 EM Based Models: D Full Wave EM simulation Fast and accurate electromagnetic simulation of arbitrary D passive components including: Traces, vias, and transitions Connectors and packages Modeling wire bonds Page 8

9 Modeling Analog Active Components Active devices Die Driver Receiver Die Package Package PCB For Analog active devices, IC vendors provide IBIS behavioral modeling of I/O buffers HSPICE models transistor level models, can protect vendor IP VerilogA transistor level or behavioral model Page 9

10 I/O Driver + Interconnect Modeling I/O simulation with Xilinx Virtex-II Pro IBIS Models Page 0

11 Page VerilogA IBIS Macro Models

12 Analog Components of a Channel Transmission Lines Via Holes High Speed Connectors Package I/O IBIS models and Transistor level models DSP Components in a Channel Decision Feedback Equalizer Feed Forward Equalizer Clock and Data Recovery Gain Controls SERDES Models Can I mix DSP and ANALOG models in a single simulation? Page

13 Modeling Pre-emphasis and Equalization Transmit Bits Received Bits Encoder / Pre-Emphasis/ Serializer/ Equalizer / CDR / De-Serializer / Physical Channel DSP components can be represented in different ways: C/C++, System C, MATLAB, HDL Page

14 DSP Behavioral Models Pre-Emphasis Equalization Page 4

15 I O DSP and ANALOG co-simulation Pre-channel Interactive Measurements TkEye T4 Label="Pre Channel Eye" NumSamplesPerSymbol=Samples_per_clock NumSymbols= Amplitude= R R6 R=50 Ohm TimedToFloat T TkPlot T Label="Pre Channel scope" xtitle="waveform" ytitle="amplitude" xrange="0 000" yrange="- " Style=connect TimedSink Pre_channel_t SplitterRF S8 SplitterRF S6 Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=Data_Collection_time nsec ControlSimulation=YES Pre-emphasis in DSP Bit-stream Transmitter with Pre-emphasis Pre-channel measurements SpectrumAnalyzer Pre_channel Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=Data_Collection_time nsec Window=Kaiser WindowConstant=0.0 Bipolar signal, +, - Pre-Emphasis X6 This upsample sets measurement resolution Repeat R5 NumTimes=Samples_per_clock BlockSize= FloatToTimed F TStep=Sample_step sec ANALOG Equalization Channel Model Del ay D N= Post Eq Interactive Measurements TkEye T7 Label="Eye Eq" NumSamplesPerSymbol=Samples_per_clock NumSymbols= Amplitude=.5 Bits B Type=Random ProbOfZero=0.5 LFSR_Length= LFSR_InitState= DF DF Var Eqn LogicToNRZ L5 Amplitude=.0 VAR VAR Clock=.8e9 Samples_per_clock= Sample_rate=Clock*Samples_per_clock Sample_step=/Sample_rate Data_Collection_time=40 Data_Collection_start=4 Tk Sli der Sc ale Low= High= Value= Identifier="Pre-emphasis Gain" PutInControlPanel =YES Granul ari ty =00 Typical Pre-emphasis is progrmaple in steps from 5% to 5% This equates to.05 to.5 on this controller. PTOLEMY-SPICE CO-SIM SI CHANNEL WITH TX PRE-EMPHASIS AND RX EQUALIZATION (Using the "drive_lines" channel example) Add A Mpy M FIR F4 Decimation= DecimationPhase=0 Interpolation= RateLimiter R8 RMax=4e0 Tk Sl ider Sc al e Low=0 Adding noise or other artefacts to the Hi gh= signal can be done in this fashion. Val ue=0 Identifier="Added Noise" PutInControl Panel=YES Granularity =00 IID_Gaussian I Mean=0 Variance=. Adding Noise SplitterRF S4 drive_lines_cosim_sub_sp X7 Trace_Spacing= Trace_Spacing sets the distance betwen line pairs as a multiple of intrapair spacing. SplitterRF S TimedToFloat T6 R R R=50 Ohm LMS_TkPlot L4 Taps=" " Decimation= DecimationPhase=0 StepSize=0.0 ErrorDelay= SaveTapsFile="tapsout.tap" Identifier="LMS filter taps" Post-channel Interactive Measurements TkPlot T7 Label="Post Channel scope" xtitle="waveform" ytitle="amplitude" xrange="0 000" yrange="- " Style=connect Receiver with Equalization For the histograms to be correct the phase needs to be set to the correct bit slice sample delay. ( will work for the default design). DownSample D Factor=Samples_per_clock Phase= Const C Level=0.0 The SampleDelay of will work for the default design. If the Channel is changed this delay can be set via a slider in the Tk controller. Set the slider to the same delay as the Eye delay slider when the widest part of the eye is at t=0 on the eye plot. TkEye T5 Sub S9 Label="Eye Post Channel " NumSamplesPerSymbol=Samples_per_clock NumSymbols= Amplitude=.5 TkHistogram T Label="Bit Slice Histogram" Top=.5 Bottom=-.5 NumberOfBars= DataPoints=0000 TkConstellation T0 Label="Bit Slice" NumSamplesPerSymbol=Samples_per_clock Amplitude=.5 SampleDelay=0 Style=dot DownSample D Factor=Samples_per_clock Phase= For the histograms to be correct the phase needs to be set to the correct bit slice sample delay. ( will work for the default design). TimedToFloat T R R7 R=50 Ohm Const C Level=0.0 Post Eq measurements TkHistogram T9 Label="Bit Slice Histogram Eq" Top=.5 Bottom=-.5 NumberOfBars= DataPoints=0000 The SampleDelay of will work for the default design. If the Channel is changed this delay can be set via a slider in the Tk controller. Set the slider to the same delay as the Eye delay slider when the widest part of the eye is at t=0 on the eye plot. TkConstellation T8 Label="Bit Slice Eq" NumSamplesPerSymbol=Samples_per_clock Amplitude=.5 SampleDelay=6 Style=dot TimedSink Post_Eq_t Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=Data_Collection_time nsec ControlSimulation=YES SplitterRF S7 SpectrumAnalyzer Post_channel Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=Data_Collection_time nsec Window=Kaiser WindowConstant=0.0 Post-channel measurements TimedSink Post_channel_t Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=Data_Collection_time nsec ControlSimulation=YES Page 5

16 Channel Model Aggressor Lines Channel Sub-network Page 6

17 Bit Error Ratio Simulation BER as a function of sampling position Page 7

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