QUICKSWITCH PRODUCTS 2.5V / 3.3V 8:1 MUX / DEMUX HIGH BANDWIDTH BUS SWITCH
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1 QUICKSWITCH PRODUCTS 2.5V / 3.3V 8:1 MUX / DEMUX HIGH BANDWIDTH BUS SWITCH IDTQS3VH251 FEATURES: N channel FET switches with no parasitic diode to VCC Isolation under power-off conditions No DC path to VCC or GND 5V tolerant in OFF and ON state 5V tolerant I/Os Low RON - 4Ω typical Flat RON characteristics over operating range Rail-to-rail switching 0-5V Bidirectional dataflow with near-zero delay: no added ground bounce Excellent RON matching between channels VCC operation: 2.3V to 3.6V High bandwidth - up to 500MHz LTL-compatible control Inputs Undershoot Clamp Diodes on all switch and control Inputs Low Demux capacitance, 4pF typical Available in QSOP and TSSOP packages DESCRIPTION: The QS3VH251 HotSwitch Quad 2:1 multiplexer/demultiplexer is a high bandwidth bus switch. The QS3VH251 has very low ON resistance, resulting in under 250ps propagation delay through the switch. The Select (Sx) input controls the data flow. The multiplexers/demultiplexers are enabled when the Enable (E) input is low. In the ON state, the switches can pass signals up to 5V. In the OFF state, the switches offer very high impedence at the terminals. The combination of near-zero propagation delay, high OFF impedance, and over-voltage tolerance makes the QS3VH251 ideal for high performance comminucation applications. The QS3VH251 is characterized for operation from -40 C to +85 C. APPLICATIONS: Hot-swapping Multiplexing/demultiplexing Low distortion analog switch Replaces mechanical relay ATM 25/155 switching FUNCTIONAL BLOCK DIAGRAM S0 S1 S2 E Y I0 I1 I2 I3 I4 I5 I6 I7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEBRUARY c 2014 Integrated Device Technology, Inc. DSC-5944/11
2 PIN CONFIGURATION I3 I2 I1 I0 Y NC E GND QSOP/ TSSOP TOP VIEW FUNCTION TABLE (1) VCC I4 I5 I6 I7 S0 S1 S2 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit ERM (2) SupplyVoltage to Ground 0.5 to +4.6 V ERM (3) DC Switch Voltage VS 0.5 to +5.5 V ERM (3) DC Input Voltage VIN 0.5 to +5.5 V VAC AC Input Voltage (pulse width 20ns) 3 V IOUT DC Output Current (max. sink current/pin) 120 ma TSTG Storage Temperature 65 to +150 C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25 C, F = 1MHz, VIN =, VOUT = ) Symbol Parameter (1) Typ. Max. Unit CIN Control Inputs 3 5 pf CI/O Quickswitch Channels Demux 4 6 pf (Switch OFF) Mux CI/O Quickswitch Channels Demux pf (Switch ON) Mux NOTE: 1. This parameter is guaranteed but not production tested. NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedence Select E S2 S1 S0 Y Function H X X X Z Disable L L L L I0 S2 - S0 = 0 L L L H I1 S2 - S0 = 1 L L H L I2 S2 - S0 = 2 L L H H I3 S2 - S0 = 3 L H L L I4 S2 - S0 = 4 L H L H I5 S2 - S0 = 5 L H H L I6 S2 - S0 = 6 L H H H I7 S2 - S0 = 7 PIN DESCRIPTION Pin Names I/O Description I0 - I7 I Data Inputs S0 - S2 I Select Input E I Enable Input Y O Data Outputs 2
3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40 C to +85 C, VCC = 3.3V ±0.3V Symbol Parameter Test Conditions Min. Typ. (1) Max. Unit VIH Input HIGH Voltage Guaranteed Logic HIGH VCC = 2.3V to 2.7V 1.7 V for Control Inputs VCC = 2.7V to 3.6V 2 VIL Input LOW Voltage Guaranteed Logic LOW VCC = 2.3V to 2.7V 0.7 V for Control Inputs VCC = 2.7V to 3.6V 0.8 IIN Input Leakage Current (Control Inputs) VIN VCC ±1 μa IOZ Off-State Current (Hi-Z) VOUT 5V, Switches OFF ±1 μa IOFF Data Input/Output Power Off Leakage VIN or VOUT to 5V, VCC = ±1 μa VCC = 2.3V VIN = ION = 30mA 6 8 RON Switch ON Resistance Typical at VCC = 2.5V VIN = 1.7V ION = 15mA 7 9 Ω VCC = 3V VIN = ION = 30mA 4 6 VIN = 2.4V ION = 15mA 5 8 NOTE: 1. Typical values are at VCC = 3.3V and TA = 25 C. TYPICAL ON RESISTANCE vs VIN AT VCC = 3.3V RON (ohms) VIN (Volts) 3
4 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ. Max. Unit ICCQ Quiescent Power Supply Current VCC = Max., VIN = GND or VCC, f = ma ΔICC Power Supply Current (2,3) per Input HIGH VCC = Max., VIN = 3V, f = 0 per Control Input 30 μa ICCD Dynamic Power Supply Current (4) VCC = 3.3V, A and B Pins Open, Control Inputs See Typical ICCD vs Enable Frequency graph below 50% Duty Cycle NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per input driven at the specified level. Mux/demux pins do not contribute to ΔIcc. 3. This parameter is guaranteed but not tested. 4. This parameter represents the current required to switch internal capacitance at the specified frequency. The mux/demux inputs do not contribute to the Dynamic Power Supply Current. This parameter is guaranteed but not production tested. TYPICAL ICCD vs ENABLE FREQUENCY CURVE AT VCC = 3.3V 6 4 ICCD (ma) ENABLE FREQUENCY (MHz) 4
5 SWITCHING CHARACTERISTICS OVER OPERATING RANGE TA = -40 C to +85 C VCC = 2.5 ± 0.2V (1) VCC = 3.3 ± 0.3V (1) Symbol Parameter Min. (4) Max. Min. (4) Max. Unit tplh Data Propagation Delay (2,3) ns tphl Y to Ix or Ix to Y tsel Select Time ns Sx to Y tpzh Enable Time ns tpzl S to Ix tphz Disable Time ns tplz S to Ix tpzh Enable Time ns tpzl E to Y or Ix tphz Disable Time ns tplz E to Y or Ix feorsx Operating Frequency - Enable (2,5) MHz NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. This parameter is guaranteed but not production tested. 3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.2ns at CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 4. Minimums are guaranteed but not production tested. 5. Maximum toggle frequency for Sx or E control input (pass voltage > VCC, VIN = 5V, RLOAD 1MΩ, no CLOAD). 5
6 SOME APPLICATIONS FOR HOTSWITCH PRODUCTS 0 to +5V NFET 0 to +5V Vcc = 3.3V CHARGE PUMP +6.5V OE DRIVER SINGLE HOT SWITCH Rail-to-Rail Switching MULTIPLEXING CONTROL CIRCUITRY 1 MEMORY CPU 8 BANKS 8 MEMORY Multiplexing/Demultiplexing PLUGGABLE CARD/ LIVE SYSTEM ZERO DOWN TIME SYSTEM CARD I/O ON CARD LOGIC CONNECTOR QS3VHXXX CPU CARD I/O ON CARD LOGIC CONNECTOR QS3VHXXX RAM BUS Hot-Swapping 6
7 TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC (1) = 3.3V ± 0.3V VCC (2) = 2.5V ± 0.2V Unit VLOAD 6 2 x Vcc V VIH 3 Vcc V 1.5 VCC/2 V VLZ mv VHZ mv CL pf SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh Propagation Delay tphl tphl VIH VOH VOL VIH (1, 2) Pulse Generator VIN RT VCC D.U.T. VOUT CL Test Circuits for All Outputs 500Ω 500Ω DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tf 2.5ns; tr 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tf 2ns; tr 2ns. VLOAD Open GND CONTROL INPUT OUTPUT SWITCH NORMALLY CLOSED LOW tpzh OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH OPEN VLOAD/2 DISABLE tphz tplz VIH VLOAD/2 VOL + VLZ VOL VOH VOH -VHZ NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Enable and Disable Times SWITCH POSITION Test tplz/tpzl tphz/tpzh tpd Switch VLOAD GND Open 7
8 ORDERING INFORMATION QS XXXXX XX Device Type Package X Blank 8 Tube or Tray Tape and Reel QG PAG QSOP - Green TSSOP - Green 3VH V / 3.3V 8:1 Mux/Demux High Bandwidth Bus Switch Datasheet Document History 09/01/08 Pg. 4, 8 Revise ICCQ Typ. and Max. Remove non green package version and updated the ordering information by removing the IDT notation. 02/24/14 Pg. 8 Updated the Ordering Information by Adding Tape and Reel information. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax:
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SN54ALS20A, SN54AS20, SN74ALS20A, SN74AS20 DUAL 4-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These devices contain two independent -input positive-nand
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and
74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS
Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 500-mA Typical Latch-Up Immunity
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 INPUT REGISTER WRITE CONTROL LOGIC
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72205LB, IDT72215LB, IDT72225LB, IDT72235LB, IDT72245LB LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead SOT- and MSOP packages
The S1F77330 series is the bus switch suitable for USB applications. The adopted CMOS process technology characterizes
OVERVIEW Power Bus Switch IC 2 to 1 Bus Switch The S1F77330 series is the bus switch suitable for USB applications. The adopted CMOS process technology characterizes the S1F77330 series by low power consumption.
SEMICONDUCTOR TECHNICAL DATA
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PI74FCT373T PI74FCT573T Octal Transparent Latches
ctal Transparent Latches Fast CMS ctal Transparent Latches Features: PI74FCT373/573T are pin compatible with bipolar FAST Series at a higher speed and lower power consumption TTL input and output levels
2.5 V/3.3 V, 2-Bit, Individual Control Level Translator Bus Switch ADG3243
2.5 V/3.3 V, 2-Bit, Individual Control Level Translator Bus Switch ADG3243 FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.5 Gbps 2.5 V/3.3 V Supply
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family 5PB11xx DATASHEET Description The 5PB11xx is a high-performance LVCMOS Clock Buffer Family. It has best-in-class Additive Phase Jitter of 50fsec
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR FEATURES DESCRIPTION 300ps typical propagation delay
AS6C K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access
LY68L M Bits Serial Pseudo-SRAM with SPI and QPI
REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0 FEATURES GENERAL
IDTVP386. General Description. Features. Block Diagram DATASHEET ADVANCE INFORMATION 8/28-BIT LVDS RECEIVER FOR VIDEO
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CW211 Specification High-Speed USB2.0(480Mbps)DPDT Switch
CW211 Specification High-Speed USB2.0(480Mbps)DPDT Switch Chipwiser Technology Co.Ltd Copyright@2009,Chipwiser Technology Co.Ltd All right reserved Chipwiser Technology 1/9 GENERAL DESCRIPTION CW211 is
Rev. No. History Issue Date Remark
Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
SEIKO EPSON CORPORATION
Power Bus Switch IC 1 to 1 Bus Switch OVERVIEW The S1F77310 series is the bus switch suitable for USB applications. The adopted CMOS process technology characterizes the S1F77310 series by low power consumption.
HIGH-SPEED 4K x 8 FourPort TM STATIC RAM
Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory
PAL22V10 Family, AmPAL22V10/A
FINAL COM L: -7//5 PAL22V Family, AmPAL22V/A 24-Pin TTL Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS As fast as 7.5-ns propagation delay and 9 MHz fmax (external) Macrocells
EFA PAEA WCLKB WENB1 WENB2 FFA WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC RSB
3.3 VOLT DUAL CMOS SyncFIFO DUAL 256 X, DUAL 512 X, DUAL 1,24 X, DUAL 2,48 X, DUAL 4,6 X, DUAL 8,12 X LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 218 FEATURES: The IDT72V81 is
8K X 8 BIT LOW POWER CMOS SRAM
February 2007 FEATURES Access time :55ns Low power consumption: Operation current : 15mA (TYP.), VCC = 3.0V Standby current : 1µ A (TYP.), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully Compatible
2.5 V/3.3 V, 8-Bit, 2-Port Level Translating, Bus Switch ADG3245
V/3.3 V, 8-Bit, 2-Port Level Translating, Bus Switch ADG3245 FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps V/3.3 V Supply Operation Selectable
SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04 HEX INVERTERS
SNALS0B, SNAS0, SN7ALS0B, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
2.5 V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch ADG3247
V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps V/3.3 V Supply Operation Selectable Level
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
Integrated evice Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 124 X 9, 248 X 9 and 496 x 9 IT72421 IT7221 IT72211 IT72221 IT72231 IT72241 FEATURES: 64 x 9-bit organization (IT72421) 256 x 9-bit
3.3 VOLT LOGIC CHARACTERISTICS AND APPLICATIONS
Integrated Device Technology, Inc. 3.3 VOLT LOGIC CHARACTERISTICS AND APPLICATIONS APPLICATION NOTE AN-124 INTRODUCTION To increase the performance and density of digital electronic systems while decreasing
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
T1/E1 CLOCK MULTIPLIER. Features
DATASHEET ICS548-05 Description The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT s patented analog/digital
AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb
REVISION HISTORY Revision Description Issue Date 1.0 Initial issue Feb 2007 2.0 Add-in industrial temperature option for 28-pin 600 July 2017 mil PDIP. Standby current(isb1) reduced to be 20uA for I-grade
STMLS05 Applications Description Features Table 1: Device summary I2C base Package Order code address marking
Enhanced five-channel PMOS load switches Datasheet - production data Applications Smart phones Tablets Mobile device accessories Wearable devices Features Five-channel PMOS switches Input/output voltage
2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
128Kx8 CMOS MONOLITHIC EEPROM SMD
128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
NOT RECOMMENDED FOR NEW DESIGNS SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
NOT RECOMMENDED FOR NEW DESIGNS Micrel, Inc. SINGLE SUPPLY QUAD PECL/TTL-TO-PECL FEATURES Quad PECL version of popular ECLinPS E Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock
ZLED7002. Toggle (Side-Step) Dual-Channel LED Driver. Datasheet. Features. Brief Description. Benefits. Available Support. Physical Characteristics
Toggle (Side-Step) Dual-Channel LED Driver ZLED7002 Datasheet Brief Description The ZLED7002 toggle (side-step) dual-channel LED driver is one of our ZLED family of LED control ICs. It operates in the
3.3 VOLT CMOS SyncBiFIFO TM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2. Mail 1. Register. RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36
FEATURES Memory storage capacity: IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running and may
A4711 SINGLE SPDT ANALOG SWITCH 2.7Ω, LOW-VOLTAGE
DESCRIPTION The is a Single Wide-Bandwidth, fast single-pole double-throw (SPDT) CMOS switch featuring an On-Resistance of 2.7 ohm at VCC=5.0V and wide power supply range from 1.8V to 5.5V. It can be used
A4732 DPDT ANALOG SWITCH LOW-POWER, TWO-PORT, HIGH-SPEED, USB2.0 (480Mbps)
DESCRIPTION The is a Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) double pole double-throw (DPDT) Analog Switch featuring an On-Resistance of 4.5 ohm at VCC=3V and a Low On Capacitance 3.7pf Typical.
512K bitstwo-wire Serial EEPROM
General Description The provides 524,288 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 65,536 words of 8 bits each. The device is optimized for use in many