Design and Simulation of ZIGBEE Transmitter Using Verilog

Transcription

1 22 Design and Simulation of ZIGBEE Transmitter Using Verilog Abstract: The past several years have witnessed a rapid development in the wireless network area. So far wireless networking has been focused on high-speed and long range applications. Zigbee technology was developed for a Wireless Personal Area Networks (WPAN), aimed at control and military applications with low data rate and low power consumption. Zigbee is a standard defines the set of communication protocols for low-data-rate short-range wireless networking. Zigbee-based wireless devices operate in 868 MHz, 915 MHz, and 2.4 GHz frequency bands. The maximum data rate is 250K bits per second. Zigbee is mainly for battery-powered applications where low data rate, low cost, and long battery life are main requirements. This paper explores Verilog design for various blocks in Zigbee Transmitter architecture for an acknowledgement frame. The word digital has made a dramatic impact on our society. Developments of digital solutions have been possible due to good digital system design and modeling techniques. Further developments have been made and introduced VLSI in order to reduce size of the architecture, to improve speed of operation, improvements in predictability of the circuit behavior. Digital Zigbee Transmitter comprises of Cyclic Redundancy Check, Bit-to-Symbol block, Symbol-to-chip block, Modulator and Pulse shaping block. The work here is to show how we can design Zigbee transmitter with its specifications by using Verilog with less number of slices and Look up tables (LUTs). Keywords: Zigbee, CRC, LUTs, occupied slices. I. INTRODUCTION Zigbee is a specification for a suite of high level communication protocols using small, low-power digital radios based on an IEEE 802 standard for personal area networks. Zigbee devices are often used in mesh network form to transmit data over longer distances, passing data through intermediate devices to reach more distant ones. This allows Zigbee networks to be formed ad-hoc, with no centralized control or high-power transmitter/receiver able to reach all of the devices. Any Zigbee device can be tasked with running the network. A.Mohammed Mian and Divyabharathi.R are with Dept. ECE, C.Abdul Hakeem College of Engineering & Technology, Melvisharam, s: divyabarathi.r@rediffmail.com, ammian79@gmail.com Zigbee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in Europe, 915 MHz in the USA and Australia, and 2.4 GHz in most jurisdictions worldwide. Data transmission rates vary from 20 to 900Kbits/second. Zigbee builds upon the physical layer and medium access control defined in IEEE standard (2003 version) for low-rate WPANs. The specification goes on to complete the standard by adding four main components: network layer, application layer, Zigbee device objects (ZDOs) and manufacturer-defined application objects which allow for customization and favor total integration. Zigbee is not intended to support power line networking but to interface with it at least for smart metering and smart appliance purposes. Because Zigbee nodes can go from sleep to active mode in 30 ms or less, the latency can be low and devices can be responsive, particularly compared to Bluetooth wake-up delays, which are typically around three seconds. Because Zigbee nodes can sleep most of the time, average power consumption can be low, resulting in long battery life. II. OBJECTIVE OF THE WORK Zigbee Transmitter can be designed with analog components. Designing an analog transmitter is easier than digital. But in analog design, data transmission will be poor and the components also bigger and more. This will not allow accurate data transmission. In designing with digital, accurate data transmission will be obtained and power supply voltage range will be smaller. One way of designing digital Zigbee transmitter is with the help of Verilog HDL and VHDL through Xilinx. The objective is to design and to synthesis the Zigbee transmitter using Verilog which will result in lesser numbers of slices and Look-up-Tables (LUTs) utilized and lossless data transmission. With lesser number of components the power utilized shall be reduced. A. Specifications III. ZIGBEE TRANSMITTER Zigbee digital transmitter in 2.4GHz band is designed using Verilog for acknowledgement frame. The PHY layer supports three frequency bands: a 2.45 GHz band with 16 channels, a 915 MHz band with 10 channels and an 868 MHz band with 1 channel. This paper focuses only on 2.45 GHz band which is used worldwide, with the data rate of 250 Kbps. The MAC layer defines two types of nodes: Reduced Function Devices (RFDs) and Full Function Devices (FFDs). RFDs can only act as end-devices and are equipped with sensors or actuators like transducers, light switches and lamps. They may only interact with a single FFD. FFDs are equipped with a full set of MAC layer

2 23 functions, which enables them to act as a network coordinator or a network end-device. Table. 1 Specifications PARAMETER Data rate No. of channels Operating frequency Channel spacing Spread spectrum Chip rate Modulation SPECIFICATION 250 Kbps GHz 5 MHz Direct Sequence Spread Spectrum 2 Mega chips per second OQPSK with Half sine Pulse shaping The IEEE defines four MAC frame structures: beacon, data, acknowledgement and MAC command frames. The beacon frame is used by a coordinator to transmit beacons. The function of beacons is to synchronize the clock of all the devices within the same network. The data frame is used to transmit data. Meanwhile, the acknowledgment frame is used to confirm successful frame reception. The MAC commands are transmitted using a MAC command frame. B. Architecture The acknowledge frame used contains 11 octets (i.e. 88 bits) of physical protocol data unit (PPDU). The binary data from the PPDU packet are inserted into the cyclic redundancy check block to detect errors during transmission. Every four bits of PPDU octet are mapped onto one data symbol, which will take place in bit-to-symbol block. The symbols will be spread into 32-chip PN sequence by utilizing Direct Sequence Spread Spectrum method in Symbol-to-chip block. Then, the chips will be modulated using OQPSK technique. C. Existing system The Zigbee digital transmitter is designed for an acknowledgment frame which is shown in Figure based on IEEE standard. This is the simplest MAC frame format and does not carry any MAC payload. This frame is constructed from MAC header (MHR) and MAC footer (MFR). The frame control field and direct sequence number (DSN) form the MHR. The MFR is composed of 16-bit frame check sequence (FCS). Both MHR and MFR are known as PHY service data unit (PSDU), which becomes the PHY payload. The PHY payload is prefixed with the synchronization header (SHR) comprised of preamble sequence, start of frame delimiter (SFD), and PHY header (PHR). Together with the SHR, PHR and PHY payload form the PHY protocol data unit (PPDU). Fig. 1 The Acknowledgement frame In existing work, the resultant signal from the general architecture was then be amplified and transmitted, which will undergo inter symbol interference. This will result in erroneous information transmission. Fig. 2 Transmitter Architecture E. Proposed system A Zigbee transmitter is to be designed for PHY and MAC layer for an acknowledgement frame. This design is going to be modeled using Verilog HDL and simulated through Xilinx. The area and performance of operation of the proposed design should satisfy the theoretical specifications and will be verified with the simulation results. Fig. 3 Proposed Transmitter Architecture Since the output of the modulator is not assured to be transmitted without error. So, in order to avoid such distortions, we need to add Pulse shaping block at the output of OQPSK modulator. This will avoid Inter symbol Interference and some transmission noises. IV. DESIGN METHODOLOGY A. Cyclic redundancy check Error detection is the process of monitoring data transmission and determining when errors have occurred. Error-detection techniques neither correct errors nor identify which bits are in error they indicate only when an error has occurred. The purpose of error detection is not to prevent errors from occurring but to prevent undetected errors from occurring. The most common error-detection techniques are redundancy checking, which includes vertical redundancy checking, checksum, longitudinal redundancy checking, and cyclic redundancy checking. B. CRC polynomial The most reliable redundancy checking technique for error detection is a convolutional coding scheme called cyclic redundancy checking (CRC). With CRC, approximately % of all transmission errors are

3 24 detected. In CRC-16, 16 bits are used for the block check sequence. Here, the entire data stream is treated as a long continuous binary number. Because the Block Check Sequence (BCS) is separate from the message but transported within the same transmission, CRC is considered a systematic code. Cyclic block codes are often written as (n, k) cyclic codes where n = bit length of transmission and k = bit length of message. Therefore, the length of the Block Check Character (BCC) in bits is BCC = n k (1) A CRC-16 BCC is the remainder of a binary division process. A data message polynomial G(x) is divided by a unique generator polynomial function P(x), the quotient is discarded, and the remainder is truncated to 16 bits and appended to the message as a BCS. The generator polynomial must be a prime number. With CRC generation, the division is not accomplished with standard arithmetic division. Instead, modulo-2 division is used, where the remainder is derived from an exclusive OR (XOR) operation. In the receiver, the data stream, including the CRC code, is divided by the same generating function P(x). If no transmission errors have occurred, the remainder will be zero. CRC-16 detects Any single-bit errors All double-bit errors All odd number of bit errors All error bursts of 16 bits or less 99.9% of error bursts greater than 16 bits long C. Bit-to-symbol block All the 88 bits from the CRC block is inserted into the bitto-symbol block. This binary information is mapped into the data symbol. The 4 LSBs (b0, b1, b2, b3) of each octet is mapped into one data symbol and the 4 MSBs (b4, b5, b6, b7) of each octet is mapped into the next data symbol. Each octet of PPDU is processed through the bit-to-symbol block sequentially, beginning with the Preamble field and ending with the last octet of the PSDU. For the final result, 22 symbols will be the output of the bit-to-symbol block. D. Results and discussion Mathematically, CRC can be expressed as Fig. 5 CRC Verilog module G(x) = Q(x) + R(x) P(x) (2) Where, G(x) = message polynomial P(x) = generator polynomial Q(x) = quotient R(x) = remainder Fig. 6 CRC Simulation Waveform The generator polynomial for CRC-16 is P(x) = x + x + x + x 0 (3) From the Figure 6.3, the output data consists of 16 digits represented by crc16_o[15:0]. At 510ns, with 25 bits of input data, output CRC code is obtained. Fig. 4 CRC-16 Generating circuit Fig. 7 BIT-TO-SYMBOL Verilog module A CRC generating circuit requires one shift register for each bit in the BCC. A review of CRC creation process is as follows: Get the raw frame Left shift the raw frame by n bits and then divide it by P. The remainder of the last action is the FCS. Append the FCS to the raw frame. The result is the frame to transmit.

4 25 Fig. 12 BIT-TO-SYMBOL VHDL architecture Fig. 8 BIT-TO-SYMBOL Simulation Waveform Fig. 9 Integrated Verilog module Fig. 13 BIT-TO-SYMBOL Simulation Waveform Fig. 14 Transmitter VHDL architecture Fig. 10 Simulation Waveform Fig. 15 Simulation Waveform Fig. 11 CRC VHDL architecture BIT-TO-SYMBOL BLOCK Fig. 16 Verilog Device Utilization Summary

5 26 slices required is 8 out of 4656 and using VHDL it is 15 out of The remaining part of the transmitter will be designed and synthesized in future. Fig.17 VHDL Device Utilization Summary The digital transmitter was partially designed and synthesized for Spartan 3E with a speed grade of 5. From the simulation waveform shown before shows the output data for the corresponding inputs. From the Synthesis report shown above, it is obvious that the number of slices utilized using VHDL is more than Verilog HDL. V. FUTURE WORK PLAN The Bit-to-Symbol output has to be verified in order to feed the next block. Otherwise this block has been synthesized and number of slices to be utilized has got. To study and design Symbol-to-Chip Mapper. This part has to be designed with the help if Direct Sequence Spread Spectrum Technique. To study and design Offset Quadrature Phase Shift Keying (O-QPSK) modulation technique. This modulation technique alone is suitable for 2.4GHz band of Zigbee transmitter. To study and design Pulse shaping block for modulated output, which will reduce the Inter Symbol Interference (ISI). VI. CONCLUSION This paper shows the Verilog based design of digital transmitter for 2.4GHz band Zigbee applications. The behavior of CRC and Bit-to-symbol were characterized using Verilog as well as using VHDL. From the discussion, so far, part of the Zigbee transmitter is alone is characterized and synthesized. Both the results and synthesis report were compared and discussion has made for the design methodology. Thus, using Verilog, Number of occupied REFERENCES [1] Khalifa. O, Islam. MDR and Khan. S, Cyclic redundancy encoder for error detection in communication channels, RF and Microwave Conference, [2] Matloff.N, Cyclic redundancy checking, Department of Computer Science, University of California, [3] Rafidah Ahmad, Othman Sidek, Wan Md. Hafizi Wan Hassin, Shukri Korakkottil Kunhi Mohd, and Abdullah Sanusi Husain, Verilog-Based design and implementation of Design Tansmitter for Zigbee Applications, International Journal of Emerging Sciences, , December 2011, ISSN: , IJES. [4] Rahmani.E, Zigbee/IEEE , University of Tehran, [5] Shuaib.K, Alnuaimi.M, Boulmalf.M, Jawhar.I, Sallabi.F and Lakas.A, Performance evaluation of IEEE : Experimental and simulation results, Journal of Communications, 2, 4(2007): [6] Sunil Shukla, Neil W.Bergmann, Single bit error correction implementation in CRC-16 on FPGA, Proceedings of IEEE International Conference on Field-Programmable Technology [7] Ting Ting Meng, Chen Zhang, Peter Athanas, An FPGA- Based Zigbee Receiver on the Harris Software Defined Radio SIP, SDR Forum Technical Conference, Denver, Colorado, [8] Wayne Tomasi, Advanced Electronic Communication System, 6 th Edition, Pearson Education. [9] Zigbee Alliance, available at: A.Mohammed Mian is Associate Professor of Electronics and Communication Engineering at C.Abdul Hakeem College of Engineering and Technology, Melvisharam. Mr.Mian is involved in research in the field of Very Large Scale Integration and same is his area of interest. Divyabharathi.R currently pursuing her Master Degree in Applied Electronics at C.Abdul Hakeem College of Engineering and Technology, Melvisharam.