Architecture and Automated Design Flow for Digital Network on chip for Analog/RF Building Block Control

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1 Architecture and Automated Design Flow for Digital Network on chip for Analog/RF Building Block Control Wolfgang Eberle, PhD IMEC Bioelectronic Systems Bridging software and analog/rf Software defined radio SW controlling analog/rf through digital means One way of doing it Is this straight forward? Keep digital out there, avoid long wires, match, be compatible with our floorplan, don t disturb analog/rf, allow late modifications, no errors, 1

2 Outline Motivation Digital communication network for analog/rf Concept Architecture Design flow Design flow automation Examples Scaldio 1a SDR Scaldio 1b SDR Neural recording & stimulation front end (Preview) Increase in control complexity FM transmitter 1 tuning knob (C9) {WLAN, GSM, UMTS, WiMAX, } SDR transceiver 2

3 Compatibility with analog/rf Analog friendly operation, architecture, layout Compatibility with analog/rf floorplan & design flow State of the art doesn t match SDR needs Origin: Backplane, PCB, and IC level SPI = (3+n) wire P2P and P2MP (common!) I2C = 2 wire NoC as found in SoCs Busses Meshes Source: NXP AN , I2C Manual & DesignCon

4 Avoiding rat s nests in telecom Origin: Telecom network infrastructure Scalable ring based architecture Scalability in topology Ring topology Multi master Scalability in throughput & delay: Serial communication Short and long packets Analog friendly Inactive during sensitive analog operations 3 wire interface across the whole chip Low voltage possible Predictability in area, floorplanning: Node templates Routing channels 4

5 Packet format adapted to operational requirements Single long packet: Fast control loops (within a standard): control all distributed relevant bits at once Multiple short packets: Start up, standard change: setting all parameters may take Scaldio 1a: 40 MHz clock, more time Scaldio 1b: 100 MHz clock Template based implementation VHDL template for master node slave node Modular design: Modrx,modtx: physical Modmac: MAC Modbitdec: logical Modbufstg: phy analog Basis for further automation From specification Towards layout 5

6 Why automation? Fast design cycle: reuse Late design changes (quick iterations) Adding & dropping parameters Change in floorplan (e.g. interference) Avoiding spec2design errors and better testability Spec as input Floorplan as input Synthesized blocks as output Programming: Software controllable parameters as starting point Excel sheet with programming parameters format & properties (grouping, fast/slow, default value) Tool extracts pins, groups, properties 6

7 Analog/RF: floorplan as starting point Analog designer designates target area (setq *noc layout* '( (RXRF ( ) ("RXLNA_Pup" :top "ME7" ) ("RXMIX_Pup" :top "ME7" ) ("RXLNA_HG<0>" :left "ME5" ) ("RXLNA_HG<1>" :left "ME5" ) ("RXLNA_HG<2>" :left "ME5" ) ) )) Tool extracts pins and their coordinates Easy to use interface Embeds entire flow into a single GUI Hides different non classical tools underneath Usable by any designer (system, analog, software, ) 7

8 Example cases: SDR front end Example case: SDR Digital control network for two multi standard SDR transceivers designs 0.13 mm 1.2V CMOS IC direct conv. Rx, Tx, 2 synth. for FDD Standards covered: UMTS, 3GPP LTE, HSDPA, e, a/b/g/j/n, /4, DAB/ DMB/DVB H RF: 100 MHz 6 GHz, BW: 1 40 MHz, Power: mw Scaldio 1b vs 1a: 19% more flexibility [Craninckx, ISSCC 2007] [Ingels, ESSCIRC 2007] 8

9 Overall topology & synthesized node Reduced silicon area Logic synthesis: 0.25 mm 2 vs 9mm 2 overall area Area increase due to logic area: 2.7 % Reduction in routing area compared to P2P: > 95% 9

10 Preview neural stimulation & recording front end Neuro electronics for brain implants 10

11 Architectural refinement reveals parameter control complexity A closer look Wise et al., Proc. IEEE, Jan 2004 Recording Stimulation Challenges Technology change? 0.13 um 0.35 um Expected # programming bits for current feature set Minimum: ~ 170 bit Maximum: ~ 820 bit Similar to SDR front end: calibration needs, AGC, DCO Significant increase in # blocks to control and spatial spread over the layout Consider data read out using same route Approach Reuse same methodology & tool Optimize protocol parameters for the application 11

12 C nclusi n Concept for digital control of analog/rf front ends Novel ring based topology Analog friendly architecture Full path from specification to floorplanning Complete implementation from specification to logic synthesis & layout Full design automation support User guided spec to layout tool automation Compatible with standard tools (Cadence) Example cases Fully (40 MHz, 420 bits) and (100 MHz, 499 bits) in two state of the art multi standard SDR transceiver designs Successful design reuse case, late design change Preview reuse case: neural stimulation & recording front end 12

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