Memory Hierarchy. Advanced Optimizations. Slides contents from:
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1 Memory Hierarchy Advanced Optimizations Slides contents from: Hennessy & Patterson, 5ed. Appendix B and Chapter 2. David Wentzlaff, ELE 475 Computer Architecture. MJT, High Performance Computing, NPTEL.
2 Advanced Cache Optimizations Reducing hit time Small L1, Way prediction Increasing cache bandwidth Pipelined caches, multibanked caches, non-blocking caches Reducing the miss penalty Critical word first, merging write buffers Reducing the miss rate Compiler optimizations Reducing the miss penalty or miss rate via parallelism Hardware and compiler prefetchng
3 Small and Simple L1 Caches Low latency and low power Critical timing path: Indexing, tag comparison, select correct set Lower associativity reduces power because fewer cache lines are accessed CAD tools to estimate hit time and power CACTI Input parameters: Feature size, cache size, associativity, number of read/write ports.
4 Small and Simple L1 Caches Lower Associativity Fewer cache lines are accessed Lesser power consumption Higher Associativity 2 cycle L1 hit time Larger access delays can be tolerated Cache size = Page Size x Associativity VIPT caches keep the TLB out of the critical path Multithreading increases conflict misses Higher hit ratio
5 L1 Cache Access Time Access Time vs. size and associativity
6 L1 Cache Energy per Read Energy per read vs. size and associativity
7 Way Prediction Improves hit time Extra bits per cache block Mis-prediction gives longer hit time Prediction accuracy 90% for two-way, 80% for four-way I-cache has better accuracy than D-cache Today: ARM Cortex-A8 Way selection Access only the predicted block Saves access power Increases mis-prediction penalty Difficult to pipeline caches
8 Pipelined Cache Access Pipeline cache access to improve bandwidth Pentium: 1 cycle, Pentium Pro Pentium III 2 cycles, Pentium 4 Core i7: 4 cycles. High bandwidth, fast clock cycle time Large hit time Increase branch misprediction penalty Make it easier to increase associativity
9 Nonblocking (Lockup-free) Cache Allow hits before previous misses complete Hit under miss Hit under multiple misses
10 Multibanked Caches Cache block is divided into banks Banks can be simultaneously accessed Sequential Interleaving Spread addresses of the block sequentially
11 Critical Word First and Early Restart Processor needs only one word at a time Critical word first: Request missed word from memory first Send it to the processor as soon as it arrives Early restart: Request words in normal order Send missed word to the processor as soon as it arrives Effectiveness of this strategy depends on block size and likelihood of another access to the portion of the block that has not yet been fetched
12 Merging Write Buffer When storing to a block that is already pending in the write buffer, update write buffer Reduces stalls due to full write buffer Write buffer without merging Write buffer after merging
13 Compiler Optimizations Loop interchange Swap nested loops to access memory in sequential order Blocking Instead of accessing entire rows or columns, subdivide matrices into blocks Requires more memory accesses but improves locality of accesses
14 Storage Order of Arrays 2D matrices storage order in memory Compiler's decision Row major order Elements stored row-wise C, C++ Column major order Elements are stored columnwise FORTRAN
15 2D Matrix Sum double A[1024][1024], B[1024][1024]; for (j=0;j<1024;j++) for (i=0;i<1024;i++) B[i][j] = A[i][j] + B[i][j]; Load A[0][0] Load B[0][0] Store B[0][0] Load A[1][0] Load B[1][0] Store B[1][0] Load A[0][1] Load B[0][1] Store B[0][1] Load A[0][2] Load B[0][2] Store B[0][2] Load A[0][0] is a Cold Start miss Cache Block contains A[0][0] A[0][3] Reference order is different from Storage order! Every Row: Cold miss, Cold Miss, Hit Hit ratio: 33%
16 Loop Interchange double A[1024][1024], B[1024][1024]; for (i=0;i<1024;i++) for (j=0;j<1024;j++) B[i][j] = A[i][j] + B[i][j]; Load A[0][0] Load B[0][0] Store B[0][0] Load A[0][1] Load B[0][1] Store B[0][1] Load A[1][0] Load B[1][0] Store B[1][0] Load A[1][0] Load B[1][0] Store B[1][0] Cache Block contains A[0][0] A[0][3] Hit Ratio: 83.3%
17 Matrix Multiplication double X[N][N], Y[N][N], Z[N][N]; for (i=0;i<n;i++) for (j=0;j<n;j++) for (k=0;k<n;k++) X[i][j] += Y[i][k] * Z[k][j]; Y[0,0], Z[0,0], Y[0,1], Z[1,0], Y[0,2], Z[2,0],... X[0,0] Y[0,0], Z[0,1], Y[0,1], Z[1,1], Y[0,2], Z[2,1],... X[0,1]... Y[1,0], Z[0,0], Y[1,1], Z[1,0], Y[1,2], Z[2,0],... X[1,0]
18 Blocking Make full use of the elements of Z when they are brought into the cache (0,0) (0,1) (0,0) (0,1) (1,0) (1,1) (1,0) (1,1) Y Z X Y x Z 0,0 0,0 x 0,0 + 0,1 x 1,0 1,0 1,0 x 0,0 + 1,1 x 1,0
19 Blocking double X[N][N], Y[N][N], Z[N][N]; for (i=0;i<n;i++) for (j=0;j<n;j++) for (k=0;k<n;k++) X[i][j] += Y[i][k] * Z[k][j]; double X[N][N], Y[N][N], Z[N][N]; for (J=0;J<N;J+=B) for (K=0;K<N;K+=B) for (i=0;i<n;i++) for (j=j;j<min(j+b,n);j++) for (k=k,r=0;k<min(k+b,n);k++) r += Y[i][k] * Z[k][j]; X[i][j] += r;
20 Hardware Prefetching Fetch two blocks on miss (include next sequential block) Pentium 4 Pre-fetching
21 Compiler Prefetching Insert prefetch instructions before data is needed Non-faulting: prefetch doesn t cause exceptions Register prefetch Loads data into register Cache prefetch Loads data into cache Combine with loop unrolling and software pipelining
22 Summary
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