Integrated Approach. Operating Systems COMPUTER SYSTEMS. LEAHY, Jr. Georgia Institute of Technology. Umakishore RAMACHANDRAN. William D.

Transcription

1 COMPUTER SYSTEMS An and Integrated Approach f Architecture Operating Systems Umakishore RAMACHANDRAN Georgia Institute of Technology William D. LEAHY, Jr. Georgia Institute of Technology PEARSON Boston Columbus Indianapolis New York San Francisco Up-pev Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto.. Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo

2 Contents Preface 5 Chapter 1 Introduction What Is Inside a Box? Levels of Abstraction in a Computer System The Role of the Operating System What Is Happening Inside the Box? Launching an Application on the Computer Evolution of Computer Hardware Evolution of Operating Systems Roadmap of the Rest of the Book 42 Exercises 42 Bibliographic Notes and Further Reading 43 Chapter 2 Processor Architecture What Is Involved in Processor Design? How Do We Design an Instruction Set? A Common High-Level Language Feature Set Expressions and Assignment Statements Where To Keep the Operands? How Do We Specify a Memory Address in an Instruction? How Wide Should Each Operand Be? Endianness Packing of Operands and Alignment of Word Operands 60

3 16 Contents 2.5 High-Level Data Abstractions Structures Arrays Conditional Statements and Loops If-Then-Else Statement Switch Statement Loop Statement Checkpoint Compiling Function Calls State of the Caller Remaining Chores with Procedure Calling Software Convention Activation Record Recursion Frame Pointer Instruction-Set Architectural Choices Additional Instructions Additional Addressing Modes Architecture Styles Instruction Format LC-2200 Instruction Set Instruction Format LC-2200 Register Set Issues Influencing Processor Design Instruction Set Influence of Applications on Instruction Set Design Other Issues Driving Processor Design 96 Summary 98 Exercises 98 Bibliographic Notes and Further Reading 102 Chapter 3 Processor Implementation Architecture versus Implementation What Is Involved in Processor Implementation? Key Hardware Concepts Circuits 106

4 3.3.2 Hardware Resources of the Datapath Edge-Triggered Logic Connecting the Datapath Elements Toward Bus-Based Design Finite State Machine (FSM) Datapath Design ISA and Datapath Width Width of the Clock Pulse Checkpoint Control Unit Design ROM Plus State Register FETCH Macro State DECODE Macro State EXECUTE Macro State: ADD Instruction (Part of R-Type) EXECUTE Macro State: NAND Instruction (Part of R-Type) EXECUTE Macro State: JALR Instruction (Part of J-Type) EXECUTE Macro State: LW Instruction (Part of l-type) EXECUTE Macro State: SW and ADDI Instructions (Part of l-type) EXECUTE Macro State: BEQ Instruction (Part of l-type) Engineering a Conditional Branch in the Microprogram DECODE Macro State Revisited Alternative Style of Control Unit Design Microprogrammed Control Hardwired Control Choosing Between the Two Control Design Styles 149 Summary 150 Historical Perspective 150 Exercises 152 Bibliographic Notes and Further Reading 156 Chapter 4 Interrupts, Traps, and Exceptions Discontinuities in Program Execution Dealing with Program Discontinuities Architectural Enhancements to Handle Program Discontinuities Modifications to FSM A Simple Interrupt Handler 165

5 20 Contents Historical Perspective 301 Exercises 303 Bibliographic Notes and Further Reading 304 Chapter 7 Memory Management Techniques Functionalities Provided by a Memory Manager Simple Schemes for Memory Management Memory Allocation Schemes Fixed-Size Partitions Variable-Size Partitions Compaction Paged Virtual Memory Page Table Hardware for Paging Page Table Setup Relative Sizes of Virtual and Physical Memories Segmented Virtual Memory Hardware for Segmentation Paging versus Segmentation Interpreting the CPU-Generated Address 334 Summary 336 Historical Perspective 337 MULTICS 339 Intel's Memory Architecture 340 Exercises 342 Bibliographic Notes and Further Reading 343 Chapter 8 Details of Page-Based Memory Management Demand Paging Hardware for Demand Paging Page Fault Handler Data Structures for Demand-Paged Memory Management Anatomy of a Page Fault 348

6 8.2 Interaction Between the Process Scheduler and Memory Manager Page Replacement Policies Belady's Min Random Replacement First In First Out (FIFO) Least Recently Used (LRU) Second Chance Page Replacement Algorithm Review of Page Replacement Algorithms Optimizing Memory Management Pool of Free Page Frames Thrashing Working Set Controlling Thrashing Other Considerations Translation Lookaside Buffer (TLB) Address Translation with TLB Advanced Topics in Memory Management Multi-Level Page Tables Access Rights As Part of the Page Table Entry Inverted Page Tables 377 Summary 377 Exercises 378 Bibliographic Notes and Further Reading 380 Chapter 9 Memory Hierarchy The Concept of a Cache Principle of Locality Basic Terminologies Multilevel Memory Hierarchy Cache Organization Direct-Mapped Cache Organization Cache Lookup Fields of a Cache Entry Hardware for a Direct-Mapped Cache Repercussion on Pipelined Processor Design 397

7 22 Contents 9.8 Cache Read/Write Algorithms Read Access to the Cache from the CPU Write Access to the Cache from the CPU Dealing with Cache Misses in the Processor Pipeline Effect of Memory Stalls Due to Cache Misses on Pipeline Performance Exploiting Spatial Locality to Improve Cache Performance Performance Implications of Increased Block Size Flexible Placement Fully Associative Cache Set Associative Cache Extremes of Set Associativity Instruction and Data Caches Reducing Miss Penalty Cache Replacement Policy Recapping Types of Misses Integrating TLB and Caches Cache Controller Virtually Indexed Physically Tagged Cache Recap of Cache Design Considerations Main Memory Design Considerations Simple Main Memory Main Memory and Bus to Match Cache Block Size Interleaved Memory Elements of Modern Main Memory Systems Page Mode DRAM Performance Implications of Memory Hierarchy 443 Summary 444 Memory Hierarchy of Modern Processors An Example 446 Exercises 447 Bibliographic Notes and Further Reading 450 Chapter 10 Input/Output and Stable Storage Communication Between the CPU and the I/O Devices Device Controller Memory Mapped I/O 453

8 Contents Programmed I/O DMA Buses I/O Processor Device Driver An Example Peripheral Devices Disk Storage The Saga of Disk Technology Disk Scheduling Algorithms First-Come-First-Served (FCFS) Shortest Seek Time First (SSTF) SCAN (Elevator Algorithm) C-SCAN (Circular Scan) LOOK and C-LOOK Disk Scheduling Summary Comparison of the Algorithms Solid State Drive Evolution of I/O Buses and Device Drivers Dynamic Loading of Device Drivers Putting it All Together 491 Summary 494 Exercises 494 Bibliographic Notes and Further Reading 496 Chapter 11 File System Attributes Design Choices in Implementing a File System on a Disk Subsystem Contiguous Allocation Contiguous Allocation with Overflow Area Linked Allocation File Allocation Table (FAT) Indexed Allocation Multilevel Indexed Allocation 513

9 24 Contents Hybrid Indexed Allocation Comparison of the Allocation Strategies Putting It All Together i-node Components of the File System Anatomy of Creating and Writing Files Interaction Among the Various Subsystems Layout of the File System on the Physical Media In Memory Data Structures Dealing with System Crashes File Systems for Other Physical Media A Glimpse of Modern File Systems Linux Microsoft Windows 543 Summary 545 Exercises 546 Bibliographic Notes and Further Reading 548 Chapter 12 Multithreaded Programming and Multiprocessors Why Multithreading? Programming Support for Threads Thread Creation and Termination Communication Among Threads Read-Write Conflict, Race Condition, and Nondeterminism Synchronization Among Threads Internal Representation of Data Types Provided by the Threads Library Simple Programming Examples Deadlocks and Livelocks Condition Variables A Complete Solution for the Video Processing Example Discussion of the Solution Rechecking the Predicate 584

10 12.3 Summary of Thread Function Calls and Threaded Programming Concepts Points to Remember in Programming with Threads Using Threads as Software Structuring Abstraction POSIX pthreads Library Calls Summary OS Support for Threads User Level Threads Kernel-Level Threads Solaris Threads: An Example of Kernel-Level Threads Threads and Libraries Hardware Support for Multithreading in a Uniprocessor Thread Creation, Termination, and Communication Among Threads Inter-Thread Synchronization An Atomic Test-and-Set Instruction Lock Algorithm with Test-and-Set Instruction Multiprocessors Page Tables Memory Hierarchy Ensuring Atomicity Advanced Topics OS Topics Architecture Topics The Road Ahead: Multicore and Many-Core Architectures 638 Summary 640 Historical Perspective 640 Exercises 642 Bibliographic Notes and Further Reading 645 Chapter 13 Fundamentals of Networking and Network Protocols Preliminaries Basic Terminologies Networking Software 654

11 13.4 Protocol Stack Internet Protocol Stack OSI Model Practical Issues with Layering Application Layer Transport Layer Stop-and-Wait Protocols Pipelined Protocols Reliable Pipelined Protocol Dealing with Transmission Errors Transport Protocols on the Internet Transport Layer Summary Network Layer Routing Algorithms Internet Addressing Network Service Model Network Routing versus Forwarding Network Layer Summary Link Layer and Local Area Networks Ethernet CSMA/CD IEEE Wireless LAN and IEEE Token Ring Other Link-Layer Protocols Networking Hardware Relationship Between the Layers of the Protocol Stack Data Structures for Packet Transmission TCP/IP Header Message Transmission Time Summary of Protocol-Layer Functionalities Networking Software and the Operating System Socket Library Implementation of the Protocol Stack in the Operating System Network Device Driver Network Programming Using UNIX Sockets Network Services and Higher-Level Protocols 734

12 Summary 736 Historical Perspective 737 From Telephony to Computer Networking 737 Evolution of the Internet 740 PC and the Arrival of LAN 741 Evolution of LAN 741 Exercises 743 Bibliographic Notes and Further Reading 746 Chapter 14 Epilogue: A Look Back at the Journey Processor Design Process Virtual Memory System and Memory Management Memory Hierarchy Parallel System Input/Output Systems Persistent Storage Network 751 Concluding Remarks 751 Appendix: Network Programming with UNIX Sockets 752 Bibliography 764 Index 770