Design principles in parser design

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1 Design principles in parser design Glen Gibb Dept. of Electrical Engineering Advisor: Prof. Nick McKeown

2 Header parsing? 2

3 Header parsing? Identify headers & extract fields A???? B???? C?? Field Field Field Field Field 2

4 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. 2

5 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. Next Hop

6 Header parsing? Identify headers & extract fields A???? B???? C?? Field Field Field Dest. Source Dest. Field Field Field Proto. Next Hop

7 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. Host X can talk to host Y Next Hop Field Dest. Firewall ALLOW DENY ALLOW except via HTTP 2

8 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. Host X can talk to host Y Next Hop Field Dest. Firewall ALLOW DENY ALLOW except via HTTP 2

9 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. Host X can talk to host Y Next Hop Field Dest. Field Source Field Dest. Field Proto. Firewall ALLOW DENY ALLOW except via HTTP 2

10 Header parsing? Identify headers & extract fields A???? B???? C?? Field Source Field Dest. Field Field Field Proto. Host X can talk to host Y Next Hop Field Dest. Field Source Field Dest. Field Proto. Firewall ALLOW DENY ALLOW except via HTTP > 1 billion packets / second New packet every ns 2

11 Almost no prior work 3

12 Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System C. Kozanitis, J. Huber, S. Singh, & G. Varghese INFOCOM 2010 Programmable parser Parses multiple headers per cycle Receives all headers before parsing high latency 4

13 400 Gb/s Programmable Packet Parsing on a Single FPGA M. Attig & G. Brebner ANCS 2011 Language to describe header sequences Compile into efficient designs on FPGA FPGA-centric commercial switches are ASICs Extremely deep pipeline (100+ stages) 5

14 Neither paper analyzes design trade-offs or presents design principles 6

15 Outline 1. Packet parsing 2. Understanding parser design 3. Providing flexibility 7

16 Packet parsing Network review Parsing process 8

17 Internet 9

18 9

19 9

21 Packet Color Output Port

22 Packet Color Output Port

23 Packet 11

24 Header 1 Header 2 Packet Header 3 Payload 11

25 Header 1 Header 2 Packet Header 3 Payload Field 1 Field 2 Field 3... Field n 11

26 (Ethernet) (VLAN) (IPv4) Header 1 Header 2 Packet Header 3 Payload Field 1 Field 2 Field 3... Field n (Source Address) (Destination Address) 11

27 (Ethernet) (VLAN) (IPv4) Header 1 Header 2 Packet Header 3 Payload Field 1 Field 2 Field 3... Field n (Source Address) (Destination Address) Destination Port A 1 B 2 C 3 D 4 11

28 Header fields Match Tables Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets 12

29 Ethernet VLAN IP TCP Src MAC Dst MAC Eth Type VLAN ID Src IP Dst IP Protocol Priority Src Port Dst Port Header fields Match Tables Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets 12

30 Ethernet VLAN IP TCP Src MAC Dst MAC Eth Type VLAN ID Src IP Dst IP Protocol Priority Src Port Dst Port In Parser Src MAC Dst MAC Eth Type VLAN ID Header fields Ethernet Forwarding Eth Type Dst IP IP Routing Src MAC Dst MAC Eth Type VLAN ID Src IP Dst IP Protocol Priority Match Tables Access Control List Src Port Dst Port Action Processing Queues Out Packets 12

31 Packet parsing Network review Parsing process 13

32 Parsing: identify headers & extract fields 14

33 Parsing: identify headers & extract fields A B C A D A B B 14

34 Parsing: identify headers & extract fields A B C A D A B B?????????? 14

35 Parsing: identify headers & extract fields A B C A D A B B A?????????? 14

36 Parsing: identify headers & extract fields A B C A D A B B Next: B A?????????? 14

37 Parsing: identify headers & extract fields A B C A D A B B Next: B A?????????? 14

38 Parsing: identify headers & extract fields A B C A D A B B Next: B A?????? B???? 14

39 Parsing: identify headers & extract fields A B C A D A B B Next: B Len: 20B Next: C A?????? B???? 14

40 Parsing: identify headers & extract fields A B C A D A B B Field Next: B Len: 20B Next: C A?????? B???? 14

41 Parsing: identify headers & extract fields A B C A D A B B Field Next: B Len: 20B Next: C A???? B?????? 14

42 Parsing: identify headers & extract fields A B C A D A B B Field Next: B Len: 20B Next: C Field Field A???? B?????? 14

43 Parsing: identify headers & extract fields A B C A D A B B Field Next: B Len: 20B Next: C Next: Field Field Field A???? B???? C?? 14

44 Parsing: identify headers & extract fields A B C A B B A D Next Hop Next: B Len: 20B Next: C Next: Field Field Field Field A???? B???? C?? 14

45 Parse graphs A B C D E F 15

46 Parse graphs A B C A C D F D E F 15

47 Parse graphs A Extract fields: 1, 2 B Extract fields: 2 C Extract fields: 1 D Extract fields: 2, 4 E Extract fields: 2 F Extract fields: 1, 2 15

48 Parse graphs A Extract fields: 1, 2 B Extract fields: 2 C Extract fields: 1 Parse graph is D E Extract fields: 2, 4 Extract fields: 2 the state machine F Extract fields: 1, 2 15

49 Parse graphs in the field ARP/RARP Ethernet IPv4 VLAN IPv6 VLAN Ethernet IPv4 VLAN VLAN Ethernet TCP UDP ICMP Enterprise TCP VXLAN UDP GRE Ethernet ARP/RARP NVGRE MPLS Data center MPLS MPLS Ethernet MPLS ARP IPv4 IPv6 RARP MPLS IPv4 IPv6 Service provider 16 TCP UDP SCTP GRE IPsec AH IPsec ESP Enterprise edge

50 Parse graphs in the field Ethernet VLAN (802.1ad) PBB (802.1ah) ARP VLAN (802.1Q) EoMPLS RARP ICMPv6 VLAN (802.1Q) MPLS IPv6 MPLS MPLS IPv4 MPLS MPLS GRE IPsec ESP IPsec AH SCTP UDP TCP ICMP NVGRE IPv6 IPv4 VXLAN Ethernet 16

51 What makes parsing hard? 17

52 What makes parsing hard? Ethernet Many headers Many paths VLAN (802.1ad) PBB (802.1ah) ARP VLAN (802.1Q) EoMPLS RARP ICMPv6 VLAN (802.1Q) MPLS IPv6 MPLS MPLS IPv4 MPLS MPLS Variable path lengths Ethernet GRE IPsec ESP IPsec AH SCTP UDP NVGRE IPv6 IPv4 VXLAN TCP ICMP 17

53 What makes parsing hard? Ethernet Many headers Many paths VLAN (802.1ad) PBB (802.1ah) ARP VLAN (802.1Q) EoMPLS RARP ICMPv6 VLAN (802.1Q) MPLS IPv6 MPLS MPLS IPv4 MPLS MPLS Variable path lengths Ethernet GRE IPsec ESP IPsec AH SCTP UDP NVGRE IPv6 IPv4 VXLAN TCP ICMP Variable header lengths Ethernet Len: 14B IPv4 Len: 20-60B TCP Len: 20-60B Payload Header identified by previous Next: IPv4 Len: 20B Next: TCP Len: 20B 17

54 What makes parsing hard? Ethernet Many headers Many paths VLAN (802.1ad) PBB (802.1ah) ARP VLAN (802.1Q) EoMPLS RARP ICMPv6 VLAN (802.1Q) MPLS IPv6 MPLS MPLS IPv4 MPLS MPLS Variable path lengths Ethernet GRE IPsec ESP IPsec AH SCTP UDP NVGRE IPv6 IPv4 VXLAN TCP ICMP Variable header lengths Ethernet Len: 14B IPv4 Len: 20-60B TCP Len: 20-60B Payload Header identified by previous Next: IPv4 Len: 20B Next: TCP Len: 20B Line rate Aggressive latency Area & power constrained 17

55 What makes parsing hard? Ethernet Many headers Many paths VLAN (802.1ad) PBB (802.1ah) ARP VLAN (802.1Q) EoMPLS RARP ICMPv6 VLAN (802.1Q) MPLS IPv6 MPLS MPLS IPv4 MPLS MPLS Variable path lengths Ethernet GRE IPsec ESP IPsec AH SCTP UDP NVGRE IPv6 IPv4 VXLAN TCP ICMP Variable header lengths Ethernet Len: 14B IPv4 Len: 20-60B TCP Len: 20-60B Payload Header identified by previous Next: IPv4 Len: 20B Next: TCP Len: 20B Line rate Aggressive latency Area & power constrained 64 x 10 Gb/s switch: 1 billion pkts/sec 250ns port-to-port 40W 17

56 Implementing a parser 18

57 Implementing a parser A B C D E F 18

58 Implementing a parser A Header Identification B C D F E Header types & locations Field Extraction Extracted Field Buffer Packet data 18 Extracted fields

59 Implementing a parser A Field (Source) Field (Dest) Field Field Header Identification Field (Proto)?????????? B D C Field (Source) F Field (Dest) E Field (Proto) Access Control ALLOW Header types DENY & locations Field ALLOWExtraction Extracted Field Buffer Packet data 18 Extracted fields

60 Implementing a parser B A D Field (Source) C Field (Source) F Field (Dest) E Field (Dest) Field (Proto) Field Field Header Identification Access Control ALLOW Header types DENY & locations Field ALLOWExtraction Field (Proto) A?????????? Extracted Field Buffer Packet data 18 Extracted fields

61 Implementing a parser A Field Field Header Identification Field (Proto) A?????????? B D C Field (Source) F Field (Dest) E Field (Proto) Extracted Field Buffer Access Control ALLOW Header types DENY & locations Field ALLOWExtraction Extracted Field Buffer Packet data 18 Extracted fields

62 Implementing a parser A???? B???? C?? B A D C Field (Source) F Field (Dest) E Field (Proto) Extracted Field Buffer Header Identification Access Control ALLOW Header types DENY & locations Field ALLOWExtraction Extracted Field Buffer Packet data 18 Extracted fields

63 Implementing a parser A Header Identification B C D F E Header types & locations Field Extraction Extracted Field Buffer Packet data 19 Extracted fields

64 Implementing a parser A Header Identification B C D F E State Machine Header types & locations Field Extraction Extracted Field Buffer Packet data 19 Extracted fields

65 Implementing a parser A Header Identification B C D F E State Machine Header types & locations Field Extraction Header Extract Fields A A1, A2 B B1 C C2, C4 Extracted Field Buffer Packet data 19 Extracted fields

66 Data processing width????????????? 20

67 Data processing width????????????? A B C D E F 20

68 Data processing width????????????? Packet position (B) B A D C E B A D C E F F 20

69 Data processing width????????????? Packet position (B) B A D C E B A D C E F F 20

70 Data processing width????????????? Packet position (B) B A D C E B A D C E F F 4 cycles, 1 decision/cycle 20

71 Data processing width????????????? Packet position (B) B A D C E B A D C E F F 4 cycles, 1 decision/cycle 20

72 Data processing width????????????? Packet position (B) B A D C E B A D C E F F 4 cycles, 1 decision/cycle 20 2 cycles, 2 decisions/cycle

73 21

74 Processing width: 1B Processing width: 2B Processing width: 3B Processing width: 16B 21

75 Parser construction Processing width: 1B Prototype: 2 months Processing width: 2B Processing width: 3B Processing width: 16B 21

76 Parser construction Processing width: 1B Prototype: 2 months Processing width: 2B Processing width: 3B Processing width: 1B Processing width: 2B Rate: 10 Gb/s Rate: 20 Gb/s Processing width: 16B Processing width: 2B Rate: 100 Gb/s 21

77 Understanding parser design Parser generator Trade-offs in parser design 22

78 Parse graph Clock Processing width Parsers per chip Parser Generator.v Parser (Verilog) Synthesis Netlist Layout Reports: 23 area, power, timing

79 Parse graph Clock Processing width Parsers per chip Parser Generator.v Parser (Verilog) Synthesis Netlist Layout Reports: 24 area, power, timing

80 Parse graph Clock Processing width Parsers per chip Parser Generator Genesis [Shacham et. al., IEEE Micro 10] Architectural Template Per-Application Configuration A = 1 B = 12 + Design Instance.v Parser (Verilog) Synthesis Netlist Layout Reports: 24 area, power, timing

81 Parse graph Clock Processing width Parsers per chip Parser Generator //; foreach my $header { //; my $hdrparser = generate('hdr_parser', //; "hdr_parser_". $n++, //; Header => $header); `$hdrparser->instantiate()` (.pkt_data (pkt data), Parser architectural template: mixed Perl/Verilog Genesis [Shacham et. al., IEEE Micro 10] Architectural Template Per-Application Configuration A = 1 B = 12 + Design Instance.v Parser (Verilog) Synthesis Netlist Layout Reports: 24 area, power, timing

82 Parse graph Processing Width Parser Generator.v Parser design 25

83 Parse graph Processing Width Parser Generator.v Parser design header { name: fields: extract: next-header: }... Parse Graph & Header Formats 25

84 Parse graph Processing Width Parser Generator.v Parser design header { name: fields: extract: next-header: } A... Parse Graph & Header Formats B D C E F 25

85 Parse graph Processing Width Parser Generator.v Parser design header { name: fields: extract: next-header: } A... Parse Graph & Header Formats B D C E F 25

86 Parse graph Processing Width Parser Generator.v Parser design header { name: fields: extract: next-header: } A A A B A C... Parse Graph & Header Formats B D C E F 25

87 Parse graph Processing Width Parser Generator.v Parser design header { name: fields: extract: next-header: } A A A B A C... C Parse Graph & Header Formats B D C F E D D F C D C E E E F 25

88 A B Next Header C D 26

89 A A B Next Header B Next Header C D C D 26

90 A A B Next Header Requires buffering to delay processing B Next Header C D C D Process all data by packet end more data some cycles 26

91 Meeting throughput needs 27

92 Meeting throughput needs r = f w throughput (rate) frequency data width 27

93 Meeting throughput needs r = f w throughput (rate) frequency data width width: w Parser width: w/n Parser 1 width: w/n Parser n 27

94 Meeting throughput needs r = f w throughput (rate) frequency data width r = n f w/n width: w Parser width: w/n Parser 1 width: w/n Parser n 27

95 Understanding parser design Parser generator Trade-offs in parser design 28

96 Data processing width? Fixed for switch r = n f w width: w width: w Parser 1 Parser n Single instance: Build a single parser of rate r (r = const n = 1 f 1/w) Multiple instances: Build multiple parsers with total rate r (r = const f = const n 1/w) 29

97 Single parser instance 10 Gb/s Big parse graph 8 M 6 M Gates Power Gates 4 M 300 Power (mw) 2 M M Processing width (B) 30 0

98 Single parser instance 10 Gb/s Big parse graph 8 M 6 M Gates Power Gates 4 M 300 Power (mw) 2 M M Processing width (B) 30 0

99 Single parser instance 10 Gb/s Big parse graph 8 M 6 M Gates Power Gates 4 M 300 Power (mw) 2 M Area: narrow width M Power: slow clock Processing width (B) 30 0

100 Aggregating parsers 2M 640 Gb/s Big parse graph M 450 Gates 1M Size Power 300 Power (mw) 0.5M 150 0M Rate (Gb/s) per instance 31

101 Aggregating parsers 2M 640 Gb/s Big parse graph M 450 Gates 1M Size Power 300 Power (mw) 0.5M 150 0M Rate (Gb/s) per instance 31

102 Aggregating parsers 2M 640 Gb/s Big parse graph M 450 Gates 1M Size Power Area: independent of instance rate 300 Power (mw) 0.5M and count 150 Power: prefer fewer fast parsers 0M Rate (Gb/s) per instance 31 0

103 Parse graph impacts area 32

104 Parse graph impacts area Enterprise Enterprise Edge Service Provider Big 32

105 Parse graph impacts area Enterprise Enterprise Edge Service Provider Big 2 M 1.5 M Gates 1 M 0.5 M 0 M 10 Gb/s 20 Gb/s 40 Gb/s 80 Gb/s Rate per instance 32

106 Parse graph impacts area Enterprise Enterprise Edge Service Provider Big 2 M 640 Gb/s aggregate 1.5 M Gates 1 M 0.5 M 0 M 10 Gb/s 20 Gb/s 40 Gb/s 80 Gb/s Rate per instance 32

107 Parse graph impacts area Enterprise Enterprise Edge Service Provider Big 2 M 1.5 M 640 Gb/s aggregate Why? Gates 1 M 0.5 M 0 M 10 Gb/s 20 Gb/s 40 Gb/s 80 Gb/s Rate per instance 32

108 Extracted fields dominate area 2 M 1.5 M 640 Gb/s 40 Gb/s per instance Header Identification Field Extraction Field Result Buffer Gates 1 M 0.5 M 0 M Enterprise Enterprise Edge Service Provider Composite 33

109 Extracted fields dominate area 2 M 1.5 M 640 Gb/s 40 Gb/s per instance Header Identification Field Extraction Field Result Buffer Gates 1 M 0.5 M 0 M 672 b 888 b 688 b 1664 b Enterprise Enterprise Edge Service Provider Composite 33

110 672b 888b 688b 1672b 34

111 672b 2 M 888b 688b 640 Gb/s 40 Gb/s per instance 1672b 1.5 M Gates 1 M 0.5 M 0 M Field Result Buffer Width (b) 34

112 672b 2 M 888b 688b 640 Gb/s 40 Gb/s per instance 1672b 1.5 M Gates 1 M 0.5 M 0 M Field Result Buffer Width (b) 34

113 672b 888b 2 M 688b 640 Gb/s 40 Gb/s per instance 1672b 1.5 M Gates 1 M 0.5 M 0 M 3 headers Extracted fields: 1672b Field Result Buffer Width (b) 34

114 672b 888b 2 M 688b 640 Gb/s 40 Gb/s per instance 1672b 1.5 M Gates 1 M 0.5 M 0 M 3 headers Extracted fields: 1672b Field Result Buffer Width (b) 34

115 672b 2 M Area 888b determined by 688b 640 Gb/s 40 Gb/s per instance 1672b extracted field buffer size 1.5 M Gates 1 M 0.5 M 0 M Field Result Buffer Width (b) 34 3 headers Extracted fields: 1672b

116 Design principles Single parser instances area minimize by reducing width power minimize by reducing clock Aggregating instances for throughput area independent of instance rate & count power minimize using few fast instances Extracted field buffer dominates area Area determined by extracted field size total 35

117 Providing flexibility RMT model Programmable parser Generating parse table entries 36

118 Parser specific to one parse graph 37

119 Parser specific to one parse graph Parser 37

120 Parser specific to one parse graph Parser 37

121 Parser specific to one parse graph Parser 37

122 Parser specific to one parse graph Parser S1 37

123 Parser specific to one parse graph Parser Switch = S1 S1 37

124 38

125 Header fields Match Tables Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets 38

126 Header fields Match Tables Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets CPU GPU FPGA OpenFlow/SDN? 38

127 Header fields Match Tables Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets 39

128 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets 39

129 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

130 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

131 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

132 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

133 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing

134 Header fields Match Tables Multiple Match Table (MMT) Queues In Parser Ethernet Forwarding IP Routing Access Control List Action Processing Out Packets Reconfigurable Multiple Table (RMT) Reconfigurable Match + Action Tables Queues In Programmable Parser Recombine Out Packets 39

135 RMT architecture Stage 1 Stage n IN DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

136 RMT architecture Stage 1 Stage n ta IN H DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

137 RMT architecture Stage 1 Stage n IN Data DATA HEADER H Match Table Action Match Table Action Recombine Output Queues OUT 40

138 RMT architecture Stage 1 Stage n IN Data DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

139 RMT architecture Stage 1 Stage n IN Data DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

140 RMT architecture Stage 1 Stage n IN Data DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

141 RMT architecture Stage 1 Stage n IN DATA HEADER Match Table Action Match Table Action Data Recombine Output Queues OUT 40

142 RMT architecture Stage 1 Stage n IN DATA HEADER Match Table Action Match Table Action Recombine Output Data Queues H OUT 40

143 RMT architecture Stage 1 Stage n IN DATA HEADER Match Table Action Match Table Action Recombine Output Queues OUT 40

144 RMT Match Tables Physical Stage 1 Physical Stage 2 Physical Stage n Logical Table 1 Logical Table 3 6 Logical Table

145 Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN P. Bosshart, G.Gibb, H.S. Kim, G. Varghese, N. McKeown, M. Izzard, F. Mujica & M. Horowitz SIGCOMM 2013 [to appear] 42

146 Providing flexibility RMT model Programmable parser Generating parse table entries 43

147 Providing programmability C Header Identification C D C E D D F Header types & locations Field Extraction Header Extract Fields A A1, A2 B B1 C C2, C4 Extracted Field Buffer B A C E E F Packet data Extracted fields D E 44 F

148 Providing programmability Replace hard-coded C Header Identification logic with C D programmable logic C E D D F Header types & locations Field Extraction Header Extract Fields A A1, A2 B B1 C C2, C4 Extracted Field Buffer B A C E E F Packet data Extracted fields D E 44 F

149 Providing programmability C Header Identification C D Curr. State Match Values Next State A A1, A2 B B B1 -- C C2, C4 D D C E D F Header types & locations Field Extraction Header Extract Fields A A1, A2 B B1 C C2, C4 Extracted Field Buffer B A C E E F Packet data Extracted fields D E 44 F

150 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

151 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

152 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

153 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

154 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

155 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

156 A B C D E F Current State Match Values Next State A 11 (A B) B A A C C C C D, D F F C C E E 45

157 Parser state table 46

158 Parser state table Current State Match Values Next State 46

159 Parser state table TCAM or RAM RAM Current State Match Values Next State 46

160 Parser state table TCAM or RAM RAM Current State Match Values Next State Header Length 46

161 Parser state table TCAM or RAM RAM Current State Match Values Next State Header Length Next Match Offsets 46

162 Parser state table TCAM or RAM RAM Current State Match Values Next State Header Length Next Match Offsets Next header location Next match locations 46

163 Parser state table TCAM or RAM RAM Optional Current State Match Values Next State Header Length Next Match Offsets Next header location Next match locations 46

164 Parser state table TCAM or RAM RAM Optional Current State Match Values Next State Header Length Next Match Offsets Next Lookup Mask Next header location Next match locations 46

165 Parser state table TCAM or RAM RAM Optional Current State Match Values Next State Header Length Next Match Offsets Next Lookup Mask Extract Fields Next header location Next match locations 46

166 Cost of programmability Extracted Field Buffer TCAM (State Table) Hdr Ident/Field Extract RAM (State Table) 47

167 Cost of programmability Extracted Field Buffer TCAM (State Table) Hdr Ident/Field Extract RAM (State Table) 7 M 5.25 M Gates 3.5 M 1.75 M 0 M Fixed Programmable 47

168 Cost of programmability Extracted Field Buffer TCAM (State Table) Hdr Ident/Field Extract RAM (State Table) 7 M 5.25 M Gates 3.5 M 1.75 M 0 M Fixed Programmable 47

169 Cost of programmability Extracted Field Buffer TCAM (State Table) Hdr Ident/Field Extract RAM (State Table) 7 M 4.4mm 2 Gates 5.25 M 3.5 M 2.6mm M 0 M Fixed Programmable 47

170 Cost of programmability Extracted Field Buffer TCAM (State Table) Hdr Ident/Field Extract RAM (State Table) Programmability costs 1.5-3x 7 M 4.4mm 2 Gates State 5.25 M table size determines area 3.5 M 2.6mm 2 increase 1.75 M 0 M Fixed Programmable 47

171 Take-aways Cost of programmability 1.5-3x fixed parser area State table dominates additional area area minimize TCAM and RAM Parse graph edge count determines table size 48

172 Providing flexibility RMT model Programmable parser Generating parse table entries 49

173 Naïve generation of state table entries 50

174 Naïve generation of state table entries 150 TCAM table size (Kb) Processing width (B) 50

175 Naïve generation of state table entries 150 TCAM table size (Kb) Processing width (B) 50

176 State table entry generation A Current State Match Values Next State B C A 11 (A B) B D E A A C C C C D, D F F F C C E E 51

177 State table entry generation A Current State Match Values Next State B C A 11 (A B) B D E A A C C C C D, D F F F C C E E 51

178 State table entry generation A Current State Match Values Next State B C A 11 (A B) B D E A A C C C C D, D F F F C C E E Merge nodes to minimize edges 51

179 State table entry generation A Current State Match Values Next State B C A 11 (A B) B D E A A C C C C D, D F F F C C E E Merge nodes to minimize edges Problem: graph clustering is NP-hard 51

180 Kangaroo Intuition: iteratively identify minimal edge clustering starting at leaves 52

181 Kangaroo Intuition: iteratively identify minimal edge clustering starting at leaves 52

182 Kangaroo Intuition: iteratively identify minimal edge clustering starting at leaves 52

183 Kangaroo Intuition: iteratively identify minimal edge clustering starting at leaves 52

184 Kangaroo Intuition: iteratively identify minimal edge clustering starting at leaves Kangaroo s algorithm: access to data anywhere in header region non-minimal solutions for non-trees 52

185 Improving solution for non-trees 53

186 Improving solution for non-trees 53

187 Improving solution for non-trees 53

188 Improving solution for non-trees Two independent solutions 53

189 Improving solution for non-trees Solution: solve shared regions independently Two independent solutions 53

190 Improving solution for non-trees Solution: solve shared regions independently Two independent solutions 53

191 Improving solution for non-trees Solution: solve shared regions independently Two independent solutions 53

192 Improving solution for non-trees Solution: solve shared regions independently Two independent solutions 53

193 Improving solution for non-trees Solution: solve shared regions independently Two independent solutions 53

194 Streaming-aware algorithm Kangaroo: Streaming: 54

195 Streaming-aware algorithm Kangaroo: Streaming: 54

196 Streaming-aware algorithm Kangaroo: Streaming: 54

197 Streaming-aware algorithm Kangaroo: Streaming: 54

198 Streaming-aware algorithm Kangaroo: Streaming: Next Hdr Next Hdr 54

199 Streaming-aware algorithm Kangaroo: OPT(n, b) = min c2clusters(n) 1 X OPT(j,...) A j2fringe(c) 55

200 Streaming-aware algorithm Kangaroo: OPT(n, b) = min c2clusters(n) 1 X OPT(j,...) A j2fringe(c) Streaming: OPT(n, b, w) = min c2clusters(n,w) X j2fringe(c) 1 OPT(j,..., NewLoc(w, j, c)) A 55

201 Streaming-aware algorithm Kangaroo: OPT(n, b) = min c2clusters(n) 1 X OPT(j,...) A j2fringe(c) Streaming: OPT(n, b, w) = min c2clusters(n,w) X j2fringe(c) 1 OPT(j,..., NewLoc(w, j, c)) A New parameter: window location 55

202 Streaming-aware algorithm Kangaroo: OPT(n, b) = min c2clusters(n) 1 X OPT(j,...) A j2fringe(c) Streaming: OPT(n, b, w) = min c2clusters(n,w) X j2fringe(c) 1 OPT(j,..., NewLoc(w, j, c)) A New parameter: window location Node clusters restricted by: windows location window size 55

203 Streaming-aware algorithm Kangaroo: OPT(n, b) = min c2clusters(n) 1 X OPT(j,...) A j2fringe(c) Streaming: OPT(n, b, w) = min c2clusters(n,w) X j2fringe(c) 1 OPT(j,..., NewLoc(w, j, c)) A New parameter: window location Node clusters restricted by: windows location window size Updated location for subgraphs 55

204 Algorithm performance O( E V d k ) Method Naive Algorithm (excluding non-tree logic) Algorithm 40b TCAM (8b state + 2 x 16b inputs) 342 entries 0.48s 177 entries 2.6s 112 entries 128.7s 56b TCAM (8b state + 3 x 16b inputs) 641 entries 0.48s 170 entries 5.5s 106 entries 207.6s 56

205 Benefits of parallel lookups? Table entries required Lookups Data arrival rate (bits/cycle) 57

206 Benefits of parallel lookups? Table entries required Lookups Data arrival rate (bits/cycle) 57

207 Benefits of parallel lookups? Table entries required Unable to process at arrival rate Lookups Data arrival rate (bits/cycle) 57

208 Benefits of parallel lookups? 8000 TCAM bits required Table entries required Unable to process at arrival rate Lookups Data arrival rate (bits/cycle) 57

209 Benefits of parallel lookups? 8000 TCAM bits required Table entries required Minimize parallel lookups 0 Unable to process at arrival rate for single instance Data arrival rate (bits/cycle) 57 Lookups

210 Contributions Parser generator Parser design trade-off analysis & principles Fixed parsers Single parser instances area minimize by reducing width power minimize by reducing clock Aggregating instances for throughput area independent of instance rate & count power minimize using few fast instances Extracted field buffer dominates area Programmable parsers Cost of programmability is low (1.5-3x) State table dominates area increase RMT model State table generation algorithm 58

211 Publications Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN Bosshart, P., Gibb, G., et. al. SIGCOMM 2013 [to appear] Outsourcing network functionality Gibb, G., Zeng, H., and McKeown, N., HotSDN '12. Initial Thoughts on the Waypoint Service Gibb, G., Zeng, H., and McKeown, N., WISH '11. Can the Production Network be the Testbed? Sherwood, R., Gibb, G., et. al, OSDI '10. A Packet Generator on the NetFPGA platform Covington, G.A., Gibb, G., et. al. FCCM '09,. NetFPGA An Open Platform for Teaching How to Build Gigabit-rate Network Switches and Routers Gibb, G., et. al. IEEE Transactions on Education 08. NetFPGA: Reusable Router Architecture for Experimental Research Naous, J., Gibb, G., et. al. PRESTO '08. Building a RCP (Rate Control Protocol) Test Network Dukkipati, N., Gibb, G. et. al. Hot Interconnects 07. NetFPGA An Open Platform for Gigabit- Rate Network Switching and Routing Lockwood, J., et. al. MSE '07 59

Slicing a Network. Software-Defined Network (SDN) FlowVisor. Advanced! Computer Networks. Centralized Network Control (NC)

Slicing a Network. Software-Defined Network (SDN) FlowVisor. Advanced! Computer Networks. Centralized Network Control (NC) Slicing a Network Advanced! Computer Networks Sherwood, R., et al., Can the Production Network Be the Testbed? Proc. of the 9 th USENIX Symposium on OSDI, 2010 Reference: [C+07] Cascado et al., Ethane: