Taking the Right Turn with Safe and Modular Solutions for the Automotive Industry
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1 Taking the Right Turn with Safe and Modular Solutions for the Automotive Industry
2 A Time-Triggered Middleware for Safety- Critical Automotive Applications Ayhan Mehmet, Maximilian Rosenblattl, Wilfried Steiner Software Architect
3 General ADAS Architecture Sensors Preprocessing Fusion Application Actuation Front Camera Surround View Map Fusion L3/4 Drive Pilot Power Train Radar Laser Object Fusion Lane Assist Parking Brake Steering... Ultrasonic, Nano Radar e-horizon Function X Central Fusion ECU (Raw Data Processing) 3
4 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM`s Demand for fast system development 4
5 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM s Demand for fast system development 5
6 The Challenge: ADAS Need Safety and Performance Sensor processing and data fusion need highest performance levels Steering and braking require up to ASIL-D + Today s automotive safety controllers do not fulfill the high computing performance and memory requirements of usual ADAS applications 6
7 FlexRay CAN Ethernet Ethernet FR CAN Joining Safety and Performance Multi-µC-ECU Control, ASIL C/D Fusion, ASIL B/C/D Sensor processing, ASIL A/B, QM Automotive µc Performance SoC Performance SoC Performance SoC (Deterministic) Ethernet Switch Communication, Synchronisation 7
8 SWC 1 SWC 2 SWC 3 SWC n SWC k SWC l Functional Safety Memory Protection Timing/State Supervision RTE RTE RTE RTE Autosar OS BSW VxWorks E2E Communication Protection Linux Middleware Middleware Middleware MCAL Automotive µc MCAL Performance SoC MCAL Performance SoC Safe Execution Platform: SEooC acc. ISO Memory Protection, Communication Protection, Timing and State Supervision, Diagnostics up to ASIL D
9 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM s Demand for fast system development 9
10 SWC 1 SWC 2 SWC 3 SWC n SWC k SWC l Time-Triggered Communication, Deterministic Scheduling RTE AUTOSAR OS BSW MCAL Automotive µc RTE VxWorks MCAL RTE Performance SoC Linux MCAL RTE Middleware Middleware Middleware Performance SoC Jitter- and collision-free communication Deterministic, collision-free SWC schedule Deterministic data flows and latencies Deterministic Ethernet Switch
11 Integration on an Event-Based Platform 4. Iterative rework until system runs stable 1. Platform configuration 2. Single SWC test without consideration of other SWCs 3. Integration shows conflicts und collisions 11
12 Integration Process on a Time-Triggered Platform Robustness through clean allocation of resources Parallel integration accelerates SW development All software runs without jitter or variation 1. Platform configuration and application scheduling 2. Single SWC test within configured schedule 3. SWCs are instantly running together ( composability ) 12
13 Integration Process on a Time-Triggered Platform Integration process massively accelerated Iterations are avoided 1. Platform configuration and application scheduling 2. Single SWC test within configured schedule 3. SWCs are instantly running together ( composability ) 13
14 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM s Demand for fast system development 14
15 TTA Task Scheduling Model T R t A t A : activation point t D : deadline T R : runtime; to be allocated T R < t D - t A? t D time 15
16 TTA Task Scheduling Model A Task τ i is characterized as following WCET C i period T i C i offset (phase) φ i 0 window of schedulability φ i D i T i t deadline D i priority P i CPU affinity A i The TTA scheduler solves a variable assignment problem 16
17 TTA Task Scheduling Model n i=1 T i = T R < t D t A T 1 T 2... T n t A t T t A : activation point t T : trigger point t D : deadline T 1, T 2,, T n : allocated CPU time T R : runtime t D time 17
18 Soft-TTA Task Scheduling Model Utilizing unused CPU time of dedicated slices is the key mechanism of the Soft TTA Approach: Case 1: SW-C 1 finishes within the dedicated time window Inp Msg SW-C 1 slice 1 slice 2 Out Msg Inp Msg SW-C 2 Out Msg SW-C 1 soft deadline violation and preemption Unused CPU time is used by SW-C 1 at lower priority slice 1 slice 2 Case 2: SW-C 1 finishes in leftover time Inp Msg Task A SW-C 1 Out Msg Inp Msg SW-C 2Karten fusion Out Msg SW-C 1 Out Msg 18
19 Soft-TTA Task Scheduling Model T TYP < n i=1 T i = T R < T WCET T 1 B T 2 B T n B t A t T t SDL t D =t HDL t A : activation point t T : trigger point t SDL : Soft Deadline (t SDL t HDL ) t HDL : Hard Deadline (t HDL = t D ) t D : deadline T 1, T 2,, T n : allocated CPU time time T R : runtime T WCET : worst case execution time T TYP : typical execution time 19
20 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM s Demand for fast system development 20
21 CPU RAM Flash CPU RAM Flash CPU RAM Flash CPU RAM Flash End-to-End Communication Latency Guarantees runnable runnable Sensor Input Period Period runnable runnable Output Actuator Period Period Scheduled Δt end-to-end latency constraint t Scheduling of runnables with defined maximal end-to-end latency Static schedule as timing model allows to compute worst case latency easily Timing supervision: effective model verification during runtime 21
22 E2E Latency Guarantees Scheduling Perspective Definition: sequence of runnables with a given maximal end-toend latency Static schedule tables allow to easily compute worst case latency End-to-end latency can be optimized by specifying additional constraints for involved tasks Example: Task A jitters and runs in wrong point of time: set jitter constraint and/or activation and deadline constraint A B C Position of Task B and C is acceptable: use activation and deadline constraints to fix them in place for next task schedule iteration 22
23 E2E Latency Guarantees Scheduling Perspective Definition: sequence of runnables with a given maximal end-toend latency Static schedule tables allow to easily compute worst case latency End-to-end latency can be optimized by specifying additional constraints for involved tasks Example: A B C 23
24 Host A Actual Schedule with End-to-End Latencies Host B 24
25 The ADAS Challenges ADAS need safety and performance Demand for high-performance safety-capable µcs # Functions > # HW resources Demand for integration concept Multiple periods Demand for Scheduling concept End-to-end latency requirements Demand for accurate timing model OEM s Demand for fast system development 25
26 The Challenge Demand for more services Increased number of ECUs Growth in sharing software and functionality between the ECUs Diversity of the hardware and communication standards Re-development of the software High: Complexity, development time and cost 26
27 The solution Following the AUTOSAR software architecture Application Software SW-C SW-C SW-C standardized AUTOSAR HW-specific Hardware Decoupling of Application SW from HW AUTOSAR IF AUTOSAR RTE Basic SW (Transport layer, system services,.. ) Microcontroller Abstraction ECU HW Modularity, Scalability, Re-usability, 27
28 Conclusions To fulfill the safety and performance requirements of today s ADAS systems an integration platform must support seamless integration of safety- and performance microcontrollers A time-triggered architecture explicitly models the temporal properties of SW-Cs, which supports the prediction of temporal characteristics of event chains (no worst-case analysis necessary) reduction of integration testing efforts (no side-effects caused by SW-C microtiming, re-use of test results) 28
29 Vienna, Austria (Headquarters) office@tttech-automotive.com Germany office@tttech-automotive.com USA usa@tttech.com Japan office@tttech.jp China china@tttech.com Copyright TTTech Computertechnik AG. All rights reserved.
30 Development Perspective Good Limitations Development is a creative process For defined quality, there have to be limitations That is the basic idea behind MISRA HIS The V-model (used in ISO26262) Every development guideline
31 Development Perspective Good Limitations Inherent property of limitations in the development context: Limited development possibilities draw attention to the limits and raise additional thoughts early in the development process
32 Development Perspective Good Limitations In a non-tta system, all software components together have limited runtime TTA introduces limited runtime for every single software component
33 Development Perspective Typical Questions Typically, the following questions are raised immediately by customers, developers, What about interrupt load? What about memory wait states? What happens when my SW misses the deadline? etc.
34 Development Perspective Typical Questions These problems usually arise late in the development process The integration test phase or The system test phase TTA forces the developers (SW-C and system) to think about that early more time for solutions
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