100GbE Architecture - Getting There... Joel Goergen Chief Scientist
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1 100GbE Architecture - Getting There... Joel Goergen Chief Scientist April 26, 2005
2 100GbE Architecture - Getting There Joel Goergen Force10 Networks joel@force10networks.com Subject : 100GbE Architecture Getting There Abstract : This presentation examines the technical approach to 100 gigabit Ethernet interface at the front end, as well as the back end needed to support the in flow and out flow of data. Date : 26 April 2005 rev01
3 Overview Identify Board-Level Technical Concerns Bandwidth Requirements Power Noise Reflections Loss Connectors Signaling BER (Bit Error Rate) EMI (Electro Magnetic Interference) Memory ASIC Technology 100GbE Front-End Starting the Call for Interest Define Architecture Define Mechanicals SERDES Back-End Starting the Call for Interest Define SERDES Block
4 Overview N+1 Redundant Fabric - BP Front End Line Card SPI4 L1 Front End Line Card SPI4 Ln+1 Passive Copper Backplane N+1 Switch Fabric Nth Switch Fabric 1st Switch Fabric L1 Ln+1
5 Overview A/B Redundant Fabric - BP Front End Front End SPI4 SPI4 Line Card Line Card A B A B Passive Copper Backplane A Fabric A B Fabric B
6 Band Width Requirements Back Plane Channel Design 2Ghz to 3Ghz Band Width Supports 2.5Gps NRZ 8B10B 2Ghz to 4Ghz Band Width Supports 3.125Gps NRZ 8B10B 2Ghz to 5Ghz Band Width (4Ghz low FEXT) Supports 6.25Gps PAM4 Supports 3.125Gps NRZ 8B10B or Scrambling 2Ghz to 6.5Ghz Supports 6.25Gps NRZ 8B10B Limited Scrambling Algorithms 2Ghz to 7.5Ghz Supports 12Gps Limited Scrambling Algorithms 2Ghz to 9Ghz Supports 25Ghz multi-level / duo-binary
7 Power Noise Line Card Architecture Optical or Copper Media Media Forwarding Engine Reserved for Power Network Processor S E R D E S S E R D E S Backplane Architecture: Clean trace routing. Good power noise control. Analog target 60mVpp ripple Digital target 150mVpp ripple Excellent SERDES to connector signal flow to minimize ground noise.
8 Power Noise Switch Fabric Architecture Reserved for Power S E R D E S S E R D E S Digital Cross Bar S E R D E S S E R D E S Architecture: Clean trace routing. Good power noise control. Analog target 30mVpp ripple Digital target 90mVpp ripple Excellent SERDES to connector signal flow to minimize ground noise.
9 Power Noise Design Criteria 3oz or 4oz copper foil distribution from A/B inputs to all cards in an internal 48volt power distribution. Input filter: Return Loss Rejection Insertion Loss Rejection Current flow paths sized for 15DegC max rise, 5DegC typical. Distribution thru-holes support 200% loading at 30DegC. Provides for the case when the incorrect drill size is selected in the drilling machine and escapes computer comparison. Unlikely case but required in carrier applications.
10 Power Noise Clean Digital Ground Clean DGND is achieved by using the correct thickness copper foil to prevent the return ground skin depth of one side of a differential pair from interfering with the return ground skin depth of the conjugate differential pair. L &&& HS1 1 oz. Cu 6.3 2X3313 rc: 50.6% L &&&&&&&&&&&&&&&&&&&&& GND 1 oz. Cu 7.5 Core 2x3313 rc: 50.6% L &&& HS2 1 oz. Cu
11 Power Noise Clean Chassis Ground Employ edge guard bands. Cover top and bottom with cross hatch. Stitch top and bottom CGND layers with appropriate spaced thru-holes. Connect DGND and CGND with a single DC connection on the back plane. Connect DGND and CGND on line cards and switch fabrics with a DC-blocked connection. This concept is referred to as Single Point Grounding
12 Reflections Worst Launch Conditions Case 1 TP4 TP5 Informative trace trace trace dogbone 24mil 24milx32mil 12mil 24milx32mil 24mil AG 24mil 6 21mil BGA 13mil Drill 13mil Drill 13mil Drill 24mil 24mil 24mil trace to BP 34mil Anti Pad trace Poor Signal Integrity SDD11/22/21 Standard Cad Approach Easiest / Lowest Cost to Implement
13 Reflections - Stub Effect and Low Zo S11 SDD21 SDD11 SDD22 CH12 AGGR2 N db SDD21 XAUI Force10 SDD Freq in MHZ
14 Loss - Channel Length 24inches SDD21 SDD11 SDD22 CH7_7_10_7in N db SDD21 Force10 SDD Freq in MHZ
15 Connector Back Plane Requirements 9Ghz Band Width. Loss < 4dB. Pair Crosstalk within: MDNEXT = *LOG(f/20000); f in MHz MDFEXT = *LOG(f/20000); f in MHz f = 50Mhz to 15000Mhz No band width limiting bends in pair routing. Pad clearance supports 6mil, 7mil, or 8mil trace geometry.
16 Connector Internal Routing
17 Connector Floor Planning
18 Signaling / Coding Considerations Channel Coding: 8B10B Scrambling Signaling: PAM4 or PAMx NRZ
19 BER The BER goal is 10E-15. Simulate to 10E-17. Tested in the lab for weeks at a time. Current SERDES support 10E-13. Effective 10E-15 is obtained by both power noise control and channel model integrity. The key is to set high standards on the analog rail voltage ripple by employing a power filter structure with excellent rejection.
20 Designing For EMI Treat each slot as a unique chamber. Use metal carriers to shield each slot.. Use honeycomb top and bottom. Seal the back plane / mid plane. Use high insertion loss gasketing. Provide multiple connections at each mating surface. Bury all nets, using outer layers as pads only. Avoid return ground cross-over from plane to plane, preventing current from passing through decoupling caps. This allows the decoupling caps to be effective power filters.
21 Memory Advanced CAMs Less power per search 4 times more performance enhanced our flexible table management schemes Memories Replacing SRAMs with DRAMs when performance allows Quad Data Rate III SRAMs Serdes based DRAMs for buffer memory
22 ASIC Technology High Speed Interfaces Interfaces to Macs, Backplane, Buffer Memory are all SERDES based. SERDES all the way SERDES to reduce pin count and gate count Smaller Process Geometry Definitely 0.09 micron or lower More gates(100% more gates over 0.13 micron process) Better performance(25% better performance) Lower power(1/2 the 0.13 micron process power) Use power optimized libraries Hierarchical Placement and Layout of the Chips Flat placement is no longer a viable option
23 Starting the Call for Interest 100GbE Gather interest from several companies. This is already in process. Determine market potential and required technology. Present to January Requires 4 to 5 years.
24 Front-End Architecture 1 25Gbit by 4λ XAUI-type Ethernet 4x4x6.25Gig 4x25Gig MAC SFI / 4lane Gearbox Lane Align, CDR, & Buffering 4λ O/E MAC SFI / 4lane Gearbox Lane Partitioning & Buffering 4λ E/O
25 4x3.125Gig Front-End Architecture 2 10GbE by 10λ 1x10Gig MAC 1ofn SERDES O/E 1ofnλ nλx10gig MAC 10 SERDES O/E 10λ
26 Optical Parameters SMF or MMF?? Likely SMF Distance: 40Km 10Km 300m 50m electrical to be replaced by 50m/100m STP Coding/signaling in process today F10 to demonstrate basic blocks by year end.
27 Front-End Mechanical Concept SFI-5p2 Interface Mechanical form of 300pin MSA small form factor transponder module. Electrical connection yet to be defined.
28 Starting the Call for Interest 25GbE Back Plane Gather interest from several companies. This is already in process. Both market potential and technology are available today to support this. Present to mid Requires 4 to 5 years.
29 25Gigabit Serdes Requires OIF interface CEI/SFI-5 to run 6.25Gig 4x6.25Gigabit parallel to 25Gigabit serial 6.25Gig coding: NRZ or PAM-4 25Gig coding: Duo-Binary Channel model available today
30 Summary Design technology is the key to successful 100gig. 25Gig back-end channels allow slot capacity to reach 500Gig. 25Gig back-end channels match to 25Gigx4λ frontend connections. MAC breakdown into 6.25Gig lanes match to 25Gigx4λ front-end connections. Electrical and Optical components available today for experimentation. High Capacity slots are the stepping block to low cost / high density 10Gig Ethernet ports in excess of 1000 per system.
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