FlexRay International Workshop. Protocol Overview

Transcription

1 FlexRay International Workshop 4 th March 2003 Detroit Protocol Overview Dr. Christopher Temple - Motorola

2 FlexRay principles Provide a communication infrastructure for future generation highspeed control applications in vehicles such as advanced powertrain, chassis, and by-wire systems. Provide architectural flexibility as key enabler to serve the diverse requirements ranging from flexible to restrictive Provide scalability to address techno-economical constraints Provide functional alternatives within one conceptual framework to address multiple application fields Reuse of understanding, tools, concepts, system architectures for different applications Provide architecture support for the integration process to address migration over different platforms page 2

3 FlexRay architecture s Level 1 interface Interface Topology interface Channel interface Channel A Channel B Network topology overview Physical layer presentation by Philips page 3

4 Network topology overview Bus Multiple star Single channel reduced wire-harness, experience, cost Dual channel tolerates one faulty channel passive medium, most experience, cost efficient allows for high data rates, increases error containment Electrical & optical physical layer page 4

5 FlexRay architecture s Level 2 interface Interface interface Channel interface Interface overview Physical layer presentation by Philips Topology Channel A Channel B page 5

6 Interface overview FlexRay supports bus guardian at physical interface enforces error containment in the time domain performs error detection in the time domain Bus guardian interacts with communication controller - signal monitoring - synchronization host processor - configuration - activation / deactivation - error signalling page 6

7 FlexRay architecture s Level 3 interface interface Protocol basics Protocol timing Frame format Communication modes Protocol services Interface Channel interface Physical layer Channel A Channel B page 7

8 Protocol timing Protocol timing related to the schedule of the communication cycle communication cycle t static segment dynamic segment symbol window network idle time arbitration grid static slot minislot macrotick action point macrotick microtick microtick page 8

9 Frame format FlexRay frame Header section (5 bytes) Network management indication bit - 1 bit Null frame indicator bit - 1 bit Synchronization frame bit - 1 bit Frame ID - 12 bit (1 4095) Frame length in words - 7 bit (0 127) Header CRC - 11 bit Cycle counter - 6 bit (0 63) Payload section (0 254 bytes) Message ID (optional) - 16 bit ( ) Network management vector (optional) - variable Payload data - variable Trailer section (3 bytes) Frame CRC - 24 bit page 9

10 Communication modes static slots static & dynamic slots Time-triggered mode distributed synchronization Event-triggered mode (Powertrain) 1 static & dynamic slots communication cycle triggered periodically by synchronized timebase single master synchronization communication cycle triggered by external trigger-event page 10

11 FlexRay architecture s Level 3 interface Interface interface Channel interface Protocol basics Protocol services Message exchange Synchronization Startup Error management Symbol Wakeup Diagnosis Physical layer Channel A Channel B page 11

12 processor interface Protocol engine Physical layer Message exchange service Messages exchanged within frames Frame flow Payload data flow Header data flow Interface Transmission CHI Control data flow Status data flow Interface Reception Frames sent within the recurring communication cycle Frame scheduling performed autonomously by the protocol engine Statically scheduled frames Repetitive message transfer with bounded communication latency Example: distributed control loops Dynamically scheduled frames Spontaneous message transfer Example: diagnosis information page 12

13 Statically scheduled frames slot counter channel A channel A Frame ID 1 Frame ID 2 t channel B Frame ID slot counter channel B static slot 1 static slot 2 static slot 3 static segment Frames of static length assigned uniquely to slots of static duration Frame sent when assigned slot matches slot counter Multiple slots per node assignable / message content variable Decouple agreement/diagnosis cycles from communication cycle Support intra-cycle application agreement BG protection of static slots page 13

14 Dynamically scheduled frames slot counter channel A minislot m m+1 m+2 m+3 m+4 m+5 channel A Frame ID m Frame ID m+3 Frame ID m+5 t channel B Frame ID m+3 Frame ID m+7 m m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+8 slot counter channel B dynamic slot without transmission dynamic slot with transmission dynamic segment Dynamic bandwidth allocation per node as well as per channel Collision-free arbitration via unique IDs and minislot counting Frame sent when scheduled frame ID matches slot counter No BG protection within dynamic segment page 14

15 processor interface Protocol engine Physical layer Synchronization service Provision of synchronized time base Frame flow Payload data flow Header data flow Interface Transmission CHI Control data flow Status data flow Interface Reception on macrotick basis Across all nodes of the cluster Fault-tolerance for fault type - Symmetric / asymmetric - Transient / permanent Scalable and variable number of participants - Cross-platform integration Worst-case deviation between two clocks within 1us achievable Synchronization performed autonomously by the protocol engine Based on sync frames sent by dedicated nodes page 15