198:231 Intro to Computer Organization. 198:231 Introduction to Computer Organization Lecture 14

Transcription

1 98:23 Intro to Computer Organization Lecture 4 Virtual Memory 98:23 Introduction to Computer Organization Lecture 4 Instructor: Nicole Hynes nicole.hynes@rutgers.edu Credits: Several slides courtesy of R. Bryant and D. O Hallaron, CMU

2 98:23 Intro to Computer Organization Lecture 4 Typical Computer Memory Hierarchy L: Registers CPU registers hold words retrieved from L cache Smaller, faster, costlier per byte L2: L: L cache (SRAM) L2 cache (SRAM) L cache holds cache lines retrieved from L2 cache L2 cache holds cache lines retrieved from main memory Larger, slower, cheaper per byte L4: L3: Main memory (DRAM) Local secondary storage (local disks) Main memory holds disk blocks retrieved from local disks Local disks hold files retrieved from disks on remote network servers L5: Remote secondary storage (tapes, distributed file systems, Web servers) 2

3 98:23 Intro to Computer Organization Lecture 4 Caching Caching - Revisited Employed at various levels of the memory hierarchy L cache (or multi-level caches) is used to copy blocks of main memory for quick access by the CPU Similarly, main memory is used to copy blocks of executable files on disk Provide the illusion of a large main memory than actually exists virtual memory Allow sharing on main memory among multiple processes (running programs) CPU Executable File Cache (SRAM) Main memory (DRAM) Disk 3

4 98:23 Intro to Computer Organization Lecture 4 Creating an Executable Program (Review) Compiler Source code Library code Other objects Executable Program Reloc Object code Linker Disk storage Main memory Compiler translates source program(s) into relocatable object code. Linker combines object code with libraries and other objects and outputs executable program on disk. Loader is invoked when executable program is run creates a run-time image, portions of which are loaded into main memory. Loader Run-time Image 4

5 Run-time image: 98:23 Intro to Computer Organization Lecture 4 Unix/Linux Run-Time Image Defines the virtual address space of the program i.e., the set of addresses that the CPU may reference in the program (shown is for a 32-bit Unix/Linux system). Includes: data, text, bss and other segments user stack run-time heap shared libraries Certain portions of the image may be unused or dynamically allocated when the program is running (e.g., user stack, run-time heap). xc x4 x848 Kernel virtual memory User stack (created at runtime) Memory-mapped region for shared libraries Run-time heap (created by malloc) Read/write segment (.data,.bss) Read-only segment (.init,.text,.rodata) Unused Memory invisible to user code %esp (stack pointer) brk Loaded from the executable file 5

6 98:23 Intro to Computer Organization Lecture 4 Virtual and Physical Address Spaces Virtual Address Space Set of addresses that the CPU references during program execution Size of virtual address space is N = 2 n For 32-bit systems n = 32 (4 gigabytes) For 64-bit systems n = 64 ( bytes = 6 exabytes!) Virtual address space consists of addresses {,,..., N-} In practice, ordinary user programs can only reference a subset of the virtual address space (rest is reserved for the OS) Physical Address Space Set of addresses in physical main memory Size of physical address space is M = 2 m Typically M << N (M s of gigabytes) Physical address space consists of addresses {,,..., M-} Clearly, not enough space in physical main memory to accommodate the virtual address space of a single program, let alone several programs. 6

7 98:23 Intro to Computer Organization Lecture 4 Locality to the Rescue Again! Code and data references tend to cluster: Spatial locality: When a virtual address (code or data) is referenced, subsequent references will likely be to items at nearby addresses. Temporal locality: When a virtual address is referenced, it will likely be referenced again in the near future. Virtual addresses Time 7

8 98:23 Intro to Computer Organization Lecture 4 Motivation for Virtual Memory No need to load entire virtual address space of a running program (process) all at once. Because of principle of locality, can dynamically load/unload blocks of the virtual address space as the program is running. Main Memory Disk 8

9 98:23 Intro to Computer Organization Lecture 4 Virtual Memory Techniques Computer systems nowadays employ virtual memory techniques to manage memory: Basic idea: Virtual memory (VM) system transfers blocks of the process virtual address space to/from main memory. VM techniques: Paging: Uses system-defined fixed-size blocks called pages. Segmentation: Uses programmer-defined variable-size blocks called segments. Paging is the dominant virtual memory technique used in contemporary computer systems. Will only discuss paging at an introductory level. Operating systems course (CS 443) covers this topic in depth. 9

10 Key Ideas 98:23 Intro to Computer Organization Lecture 4 Paging Virtual address space is divided into equal-sized blocks called virtual pages. Physical address space is similarly divided into equal-sized blocks called physical pages. A virtual page and a physical page have the same page size P = 2 p bytes. Virtual pages and physical pages are numbered sequentially starting from zero. Virtual Address Space VP VP 2 p bytes Physical Address Space PP PP VP 2 n-p - N- M- PP 2 m-p - Virtual pages (VPs) Physical pages (PPs)

11 98:23 Intro to Computer Organization Lecture 4 How Paging Works Paging When a program is first run, VM system loads the virtual page containing the program s entry point (i.e., main ) into an empty physical page in main memory. As the program is running, the CPU will reference virtual addresses of instructions and data. So long as these virtual addresses belong to the virtual page that is in main memory (page hit), the CPU can access the contents of these virtual addresses from main memory. When the CPU references a virtual address belonging to a virtual page that is currently not in main memory, a page fault occurs. The VM system then fetches the referenced virtual page from disk and loads it into main memory. The CPU then resumes program execution. Thus, paging is nothing more than using main memory as a (DRAM) cache for executable programs residing on disk.

12 98:23 Intro to Computer Organization Lecture 4 Paging At run-time the set of virtual pages of a program can be partitioned into three disjoint subsets: Unallocated: Pages that have not yet been allocated or created by the VM system e.g., unused portions of the user stack or run-time heap. Cached: Allocated pages that are currently cached in physical main memory. Uncached: Allocated pages that are not cached in physical memory. Virtual memory Physical memory VP VP Unallocated Cached Uncached Unallocated Empty Empty PP PP Cached VP 2 n-p - Uncached Cached Uncached N- M- Empty PP 2 m-p - Virtual pages (VPs) stored on disk Physical pages (PPs) cached in DRAM 2

13 98:23 Intro to Computer Organization Lecture 4 Page Table Page Tables In-memory data structure maintained by the VM system to keep track of the state (cached/uncached/ unallocated) and location of each virtual page. One page table entry (PTE) per virtual page. Valid bit: means virtual page is currently cached in physical memory. means virtual page in not cached in physical memory. Location: If valid = (cached), specifies physical page number to which virtual page is mapped. If valid = (uncached), specifies disk address of virtual page if allocated. If virtual page is unallocated, location = NULL. Valid PTE PTE PTE 2... Location (Physical page number or disk address) Memory resident page table (DRAM) 3

14 98:23 Intro to Computer Organization Lecture 4 Page Table - Illustration Assume 8 virtual pages VP VP 7 VPs and 5 are unallocated Page Tables VPs, 2, 4, 7 are cached; VPs 3 and 6 are not Valid PTE PTE PTE 2 PTE 3 PTE 4 PTE 5 PTE 6 PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 PP PP 3 4

15 98:23 Intro to Computer Organization Lecture 4 Page Hit Page hit occurs when virtual address referenced belongs to a cached virtual page. Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 5

16 98:23 Intro to Computer Organization Lecture 4 Page Fault Page fault occurs when virtual address referenced belongs to an uncached virtual page. Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 6

17 98:23 Intro to Computer Organization Lecture 4 Handling a Page Fault Page fault causes an exception (interrupts running program). Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 7

18 98:23 Intro to Computer Organization Lecture 4 Handling a Page Fault Page fault handler selects a victim to be evicted (here VP 4). Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 8

19 98:23 Intro to Computer Organization Lecture 4 Handling a Page Fault Page fault handler selects a victim to be evicted (here VP 4). Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 3 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 9

20 98:23 Intro to Computer Organization Lecture 4 Handling a Page Fault Offending instruction is restarted now a page hit. Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 3 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3 2

21 98:23 Intro to Computer Organization Lecture 4 VM Supports Multiprogramming Can have several running programs (processes) at the same time. Each process has its own virtual address space, but number of active virtual pages (working set) per process is typically not large. Therefore, VM system can cache working sets of several processes in physical memory at the same time. VM allows processes to share code and data (e.g., library code) by mapping virtual pages to the same physical page (here PP 6) 2

22 98:23 Intro to Computer Organization Lecture 4 Practical Considerations Virtual memory works because of locality: Programs with better locality will have smaller working sets If ( working set size < main memory size ) Good performance for one process after compulsory misses If ( SUM(working set sizes) > main memory size ) Thrashing: Performance meltdown where pages are swapped (copied) in and out continuously DRAM physical memory as cache for disk is driven by the enormous miss penalty: DRAM is about x slower than SRAM But disk is about,x slower than DRAM Consequences: Large page (block) size: typically 4-8 KB, sometimes 4 MB Fully associative - any VP can be placed in any PP Highly sophisticated, expensive page replacement algorithms Page writes: write-back rather than write-through Set dirty bit on write Write back to disk on page-out if dirty bit is set 22

23 Virtual Address Space V = {,,, N} Physical Address Space P = {,,, M} Address Translation MAP: V P U { } For virtual address a: 98:23 Intro to Computer Organization Lecture 4 VM Address Translation MAP(a) = a if data at virtual address a is at physical address a in P MAP(a) = if data at virtual address a is not in physical memory» Either invalid or stored on disk Address translation is performed by memory management unit (MMU) 23

24 98:23 Intro to Computer Organization Lecture 4 Summary of Address Translation Symbols Basic Parameters N = 2 n : Number of addresses in virtual address space M = 2 m : Number of addresses in physical address space P = 2 p : Page size (bytes) Components of the virtual address (VA) VPO: Virtual page offset (p bits) VPN: Virtual page number (n-p bits) n- p p- Virtual page number (VPN) Virtual page offset (VPO) Components of the physical address (PA) PPO: Physical page offset (p bits) PPN: Physical page number (m-p bits) m- p p- Physical page number (PPN) Physical page offset (PPO) 24

25 98:23 Intro to Computer Organization Lecture 4 Address Translation With a Page Table Page table base register (PTBR) n- Virtual page number (VPN) Virtual address p p- Virtual page offset (VPO) Page table address for process Page table Valid Physical page number (PPN) Valid bit = : page not in memory (page fault) m- p p- Physical page number (PPN) Physical address Physical page offset (PPO) 25

26 98:23 Intro to Computer Organization Lecture 4 Address Translation: Page Hit CPU Chip CPU VA MMU 2 PTEA PTE 3 PA Cache/ Memory 4 Data 5 ) CPU sends virtual address to MMU (memory management unit) 2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to CPU VA: virtual address, PA: physical address, PTE: page table entry, PTEA = PTE address 26

27 98:23 Intro to Computer Organization Lecture 4 Address Translation: Page Fault Exception 4 Page fault handler CPU Chip CPU VA 7 MMU 2 PTEA PTE 3 Cache/ Memory Victim page 5 New page Disk 6 ) CPU sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction 27

28 98:23 Intro to Computer Organization Lecture 4 VM Address Translation Example Basic Parameters N = 2 4 virtual addresses 4-bit virtual addresses M = 2 2 physical addresses 2-bit physical address Page size = 2 6 = 64 bytes Number of virtual pages = 2 4 /2 6 = 2 8 = 256 Number of physical pages = 2 2 /2 6 = 2 6 = 64 28

29 98:23 Intro to Computer Organization Lecture 4 VM Address Translation Example Consider the following snapshot of the page table: Page table has 256 PTEs; will only show first 6 PTEs VPNs and PPNs are in hex VPN PPN Valid VPN PPN Valid A B 4 C 5 6 D 2D 6 E 7 F D 29

30 98:23 Intro to Computer Organization Lecture 4 VM Address Translation Example. Suppose the CPU references virtual address x3d VPN = xf VPO VPN PPN Valid VPN PPN Valid A B 4 C 5 6 D 2D 6 7 E F D page hit Physical address = x PPN = xd PPO = VPO 3

31 98:23 Intro to Computer Organization Lecture 4 VM Address Translation Example 2. Suppose the CPU references virtual address x2cf VPN = xb VPO VPN PPN Valid VPN PPN Valid A B page fault 4 C 5 6 D 2D 6 E 7 F D Assume page fault handler loads virtual page to main memory at PPN x2a. 3

32 98:23 Intro to Computer Organization Lecture 4 VM Address Translation Example 2. Suppose the CPU references virtual address x2cf VPN = xb VPO VPN PPN Valid VPN PPN Valid A B C D 7 9 2A 2D page table updated after loading virtual page to MM 6 E 7 F D Physical address = xa8f PPN = x2a PPO = VPO 32

33 98:23 Intro to Computer Organization Lecture 4 Integrating VM and Cache PTE CPU Chip CPU VA Data 9 MMU 3 PTEA 2 PA PTEA hit PA hit PTEA miss PA miss PTE 5 PTEA PA 6 7 Data L cache 4 8 Memory ) CPU sends virtual address to MMU 2-5) MMU fetches PTE from cache if miss, load from memory 6-8) MMU sends physical address to cache if miss, load from memory 9) Cache sends data word to CPU 33

34 98:23 Intro to Computer Organization Lecture 4 Speeding up Translation with a TLB Page table entries (PTEs) are cached in L like any other memory word PTEs may be evicted by other data references PTE hit still requires a small L delay Solution: Translation Lookaside Buffer (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages Components of a virtual address used to access the TLB n- p+t p+t- p p- TLB tag TLB set index VPO VPN 34

35 98:23 Intro to Computer Organization Lecture 4 TLB Hit CPU Chip TLB A TLB hit eliminates a memory access 2 PTE VPN 3 CPU VA MMU PA 4 Cache/ Memory Data ) CPU sends virtual address to MMU 5 2-3) MMU fetches appropriate PTE from TLB 4) MMU translates virtual address to physical address and sends it to cache/memory 5) Cache/memory sends data word to CPU 35

36 98:23 Intro to Computer Organization Lecture 4 TLB Miss CPU Chip TLB 4 A TLB miss incurs an extra memory access (the PTE) 2 PTE VPN 3 CPU VA MMU PTEA PA Cache/ Memory 5 Data ) CPU sends virtual address to MMU 6 2) MMU fetches appropriate PTE from TLB 3-4) On TLB miss, MMU fetches PTE from page table in memory and stores it in TLB 5) MMU translates virtual address to physical address and sends it to cache/memory 6) Cache/memory sends data word to CPU 36

37 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Virtual and Physical Address Spaces 4-bit virtual addresses 2-bit physical address Page size = 64 bytes VPN (Virtual Page Number) VPO (Virtual Page Offset) PPN (Physical Page Number) PPO (Physical Page Offset) 37

38 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table Page table has 256 PTEs; will only show first 6 PTEs Assume all other VPNs not allocated in main memory VPN PPN Valid VPN PPN Valid A B 4 C 5 6 D 2D 6 E 7 F D 38

39 TLB 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB 6 entries 4-way associative TLBT TLBI VPN VPO Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 3 9 D D 2 4 A D A

40 98:23 Intro to Computer Organization Lecture 4 Cache All Together Now: VM with Cache + TLB 6 lines; 4-byte line size Direct mapped CT CI CO PPN PPO Idx Tag Valid B B B2 B3 Idx Tag Valid B B B2 B A D 2 B A 2D 93 5 DA 3B 3 36 B B D 8F 9 C 2 5 D F D D E B D3 7 6 C2 DF 3 F 4 4

41 Ex. Virtual Address x3d4 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address VPN xf 3 x3 VPO CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 4

42 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table TLB Cache 42

43 Ex. Virtual Address x3d4 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address VPN VPO xf 3 x3 Y NO xd CT CI CO PPN PPO x5 xd CO CI CT Cache Hit? Byte: 43

44 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table TLB Cache 44

45 Ex. Virtual Address x3d4 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address VPN VPO xf 3 x3 Y NO xd CT CI CO PPN PPO x5 xd Y x36 CO CI CT Cache Hit? Byte: 45

46 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Ex 2. Virtual Address xb8f TLBT TLBI VPN VPO x2e 2 xb VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 46

47 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table TLB tag = xb not in set 2 TLB miss TLB Cache 47

48 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Ex 2. Virtual Address xb8f TLBT TLBI VPN VPO x2e 2 xb NO VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 48

49 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table VPN x2e not in MM page fault TLB Cache 49

50 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Ex 2. Virtual Address xb8f TLBT TLBI VPN VPO x2e 2 xb NO YES TBD VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 5

51 Ex 3. Virtual Address x2 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN VPO x x VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 5

52 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table TLB tag = x in set but Valid = TLB miss TLB Cache 52

53 Ex 3. Virtual Address x2 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN VPO x x NO VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI CT Cache Hit? Byte: 53

54 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table TLB Cache 54

55 Ex 3. Virtual Address x2 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN VPO x x NO NO x28 VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI x8 CT x28 Cache Hit? Byte: 55

56 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB Page Table Cache tag = x28 not in set 8 cache miss TLB Cache 56

57 Ex 3. Virtual Address x2 98:23 Intro to Computer Organization Lecture 4 All Together Now: VM with Cache + TLB TLBT TLBI VPN VPO x x NO NO x28 VPN TLBI TLBT TLB Hit? Page Fault? PPN: Physical Address CT CI CO PPN PPO CO CI x8 CT x28 Cache Hit? NO Byte: MEM 57

58 98:23 Intro to Computer Organization Lecture 4 Flat page table can be huge Multi-Level Page Table Consider a 32-bit virtual address space as on modern computers Page size of 4 KB (2 2 ) Page table would have million entries (2 32 / 2 2 ) If each entry is 4 bytes 4 MB of physical memory for page table alone! Multi-level page table Page table is organized as a tree of smaller page tables Obtained by subdividing page number field of virtual address into two or more subfields 58

59 98:23 Intro to Computer Organization Lecture 4 Two-Level Page Table Consider a 32-bit virtual address space, pages of size 4K (= 2 2 ) bytes each: Page number field will consist of 2 bits Page offset field will consist of 2 bits Now divide the 2-bit page number field further into two fields p and p 2 each bits wide: page number page offset p p 2 offset 2 This gives rise to a two-level page table p index to outer page table; holds pointer to an inner table p 2 index to inner table; holds frame number corresponding to page 59

60 98:23 Intro to Computer Organization Lecture 4 Two-Level Page Table Virtual address 2 p p 2 off Outer page table Inner page table Inner page table p Inner page table p p 2 PPN Inner page table 23 PPN off Physical address

61 98:23 Intro to Computer Organization Lecture 4 Two-Level Page Table Virtual address 2 p p 2 off At most two tables retrieved from disk; each can fit in a page Outer page table Inner page table Inner page table p Inner page table p p 2 PPN Inner page table 23 PPN off Physical address

62 98:23 Intro to Computer Organization Lecture 4 Summary Programmer s view of virtual memory Each process has its own private linear address space Cannot be corrupted by other processes System view of virtual memory Uses memory efficiently by caching virtual memory pages Efficient only because of locality Simplifies memory management and programming Simplifies protection by providing a convenient interpositioning point to check permissions 62