IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -2 1 UNIT 2

Transcription

1 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -2 1 UNIT 2 1. Block diagram of MSP430x5xx series micro-controller CPU architecture of MSP430x5xx Memory map/ Address space of MSP430x5xx I/O Ports / GPIO / Digital IO pins (a) LED interfacing (b) Switches Interfacing and Pull up/down resistor concepts Processing of Interrupts Clock system of MSP Low power modes of MSP Watchdog Timer

2 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT MSP430x5xx Microcontroller : The features of MSP430x5xx micro-controller are : Flash-based ultra-low-power MCUs 16-bit RISC architecture 25 MHz Clock, V operation Flexible power management system Power specification overview, as low as: 0.1 μa RAM retention 2.5 μa real-time clock mode 165 μa / MIPS active Wake-up from standby mode in less than 5 µs. Device parameters: Flash options: up to 512 KB RAM options: up to 66 KB ADC options: 10 & 12-bit SAR GPIO options: 29/31/47/48/63/67/74/87 pins Fig : Block diagram of MSP430 F5529/ F5528 / F5519

3 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -2 3 The block diagram of MSP430F5529 consists of the following modules : 1. Unified Clock System (UCS) : The UCS module provides the various clocks for a device. The UCS module supports low system cost and ultra-low power consumption. It provides 3- internal clock signals : MCLK, SMCLK and ACLK Using three internal clock signals, the user can select the best balance of performance and low power consumption. 2. Embedded Emulation Module (EEM) EEM is accessed and controlled through either 4-wire JTAG mode or Spy-Bi- Wire mode. The emulation, JTAG interface and Spy-Bi-Wire interface are used to communicate with a desktop computer when downloading a program and for debugging. 3. Flash memory : 128 KB 4. RAM : 8 KB + 2 KB if USB is disabled 5. Power Management Module (PMM): The PMM manages all functions related to the power supply and its supervision for the device. The PMM uses an integrated low-dropout voltage regulator (LDO) The Supply Voltage Supervisor (SVS) is used to monitor the supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to (or) removed from the VCC terminal. The brownout reset circuit resets the device by triggering a POR (Power on Reset) signal when power is applied (or) removed. 6. Watchdog Timer : A watchdog timer is an electronic timer that is used to detect and recover from computer malfunctions. The Watchdog Timer (WDT) module restarts the system on occurrence of a software problem (or) if a selected time interval expires. During normal operation, the system regularly restarts the watchdog timer to prevent it from elapsing, or "timing out". If the system fails to restart the watchdog due to a hardware fault (or) program error, the timer will elapse and generate a timeout signal. The timeout signal is used to initiate corrective actions like placing the system in a safe state and restoring normal system operation. The WDT can also be used to generate timely interrupts for an application.

4 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT I/O PORTS : P1, P2, P3, P4, P5, P6, P7 & P8 MSP430F5529 has 8-digital I/O ports : P1 to P8. The I/O Ports P1 to P7 have 8- I/O pins and P8 has 3- I/O pins. Each I/O pin is individually configurable for input (or) output direction, and each I/O line can be individually read or written to. All ports have individually configurable pull-up (or) pull-down resistors, as well as, configurable drive strength. Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal. Individual ports can be accessed as byte wide ports or can be combined into word wide ports and accessed via word formats. Port pairs P1/P2, P3/P4, P5/P6, P7/P8, etc. are associated with the names PA, PB, PC, PD, etc., respectively. 8. Full speed USB ( Universal Serial Bus) : Full-speed integrated USB transceiver (PHY)- Physical layerinterface Supports control, interrupt, and bulk transfers Supports USB suspend, resume, and remote wakeup Integrated 1.8 V and 3.3 V low drop-out (LDO) linear regulator Integrated programmable PLL Highly flexible clock frequencies 2 KB of dedicated USB buffer. If USB is disabled, 2 KB buffer space is mapped into RAM and USB pins can be used as GPIO pins Bit Hardware Multiplier (MPY32) The MPY32 is a peripheral and is not part of the CPU. This means its activities do not interfere with the CPU activities. It performs Signed and Unsigned multiplications 8-bit/16-bit/24-bit/32-bit operations 10. Timers Timers are essential to almost any embedded application. The timers are used to generate fixed-period events, periodic wakeup, count edges and replacing delay loops with timer calls allows CPU to sleep, consuming much less power. Timers can support multiple capture/compares, PWM outputs, interval timing and extensive interrupt capabilities. The MSP430F5529 has 4- timer modules 16-bit Timer TA0 : with 5 - CC registers 16-bit Timer TA1 : with 3 - CC registers 16-bit Timer TA2 : with 3 - CC registers 16-bit Timer TB0 : with 7 - CC registers

5 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Real Time Clock ( RTC_A ) Configurable for real-time clock with calendar function or general-purpose counter. Provides seconds, minutes, hours, day of week, day of month, month, and year in real-time clock with calendar function. Interrupt capability 12. Cyclic Redundancy Check (CRC) : The cyclic redundancy check (CRC) module provides a signature for a given data sequence. The signature is generated through a feedback path from data bits 0, 4, 11 & Universal Serial Communication Interface : Two channels : USCI-A & USCI-B Each channel consists of Two ports USCI-A0 & USCI-A1 supports UART, IrDA and SPI USCI-B0 & USCI-B1 supports I2C and SPI 14. ADC12_A The ADC12_A is a high-performance 12-bit analog-to-digital converter (ADC). The module implements a 12-bit SAR core, sample select control and a 16-word conversion-and-control buffer. 16-channel, 14- external & 2- internal 200 KSPS Internal Reference S/H and Auto scan feature 15. Reference Module (REF) The REF module is a general purpose reference system that is used to generate voltage references required for other peripheral modules such as digital-toanalog converters, analog-to digital,converters, or comparators. It generates reference voltages : 1.5 V, 2.0V, 2.5V selectable references 16. Comparator ( Comp_B ) Comp_B is an analog voltage comparator. Comp_B covers general comparator functionality for up to 16 channels. The Comp_B module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.

6 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Direct Memory Access (DMA) Controller Module The direct memory access (DMA) controller module transfers data from one address to another without CPU intervention. Devices that contain a DMA controller may have up to eight DMA channels available. ( The MSP430F5529 has 3-channels) It can also reduce system power consumption by allowing the CPU to remain in a low-power mode, without having to awaken to move data to or from a peripheral. 2. CPU Architecture & Registers of MSP430x5xx :

7 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Memory map/ Address space of MSP430x5xx : Peripherals BSL memory (Flash) Flash Information memory USB RAM RAM Code memory Flash Memory & Interrupt Vector Table 4 KB 2KB (512B * 4 segments) 512 B (128B * 4 segments) 2 KB 8 KB (2KB * 4 sectors) 128 KB (32 KB * 4 banks) 128 KB

8 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT I/O PORTS (GPIO pins) MSP430x5xx devices have up to 12 digital I/O ports : P1 to P11 and PJ. Most ports have eight I/O pins, however some ports may contain less. Each I/O pin is individually configurable for input (or) output direction, and each I/O line can be individually read or written to. All ports have individually configurable pull-up (or) pull-down resistors, as well as, configurable drive strength. Ports P1 and P2 always have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal. Individual ports can be accessed as byte wide ports or can be combined into word wide ports and accessed via word formats. Port pairs P1/P2, P3/P4, P5/P6, P7/P8, etc. are associated with the names PA, PB, PC, PD, etc., respectively. When writing to port PA with word operations, all 16 bits are written to the port. Writing to the lower byte of the PA port using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of the PA port using byte instructions leaves the lower byte unchanged. Each port is assigned several 8-bit registers that control the function of the pins and provides information on their current status. The following is a list of registers always available for ports: PxSEL (Port Selection) : selects either digital I/O (0) or an alternate function (1) PxDIR (Port Direction) : configures the corresponding pin for input mode(0) or output mode(1) PxIN (Port Input) : Reads the voltage levels on input pins, if they are configured as GPIO. This is read-only register, and reflects the current status of port pins. PxOUT (Port Input) : Sends the value to be driven to each pin, if it is configured as GPIO PxREN ( Port Resistor Enable) : Enables pull-up / pull-down resistors on input pins. 1 Enables pull-up / pull-down resistors 0 Disables pull-up / pull-down resistors If the pin is configured in input mode and PxREN is enabled then, the corresponding bit in PxOUT register selects whether the resistors are pull-up (1) or pull-down (0)

9 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -2 9 Some GPIOs in the MSP430 have the capability to generate an interrupt and inform the CPU when a transition has occurred. MSP430 devices typically have interrupt capability on Ports 1 and 2. The registers controlling these options are as follows: PxIE (Interrupt Enable) : Each bit enables (1) or disables (0) the interrupt for that particular pin PxIES ( Interrupt Edge Select) : Selects whether a pin will generate an interrupt on the rising-edge (0) or the falling-edge (1) PxIFG (Interrupt Flag) : Set whenever the interrupt is detectd on a particular pin Note : Procedure to set / clear any bit in the Port Registers PDIR To set Bit.3 of PDIR ( PDIR.3 = 1 ) To clear Bit.3 of PDIR ( PDIR.3 = 0 ) mov.b # b, &PDIR bis.b # , &PDIR PDIR = PDIR 0x08 PDIR = PDIR BIT3 mov.b # b, &PDIR bic.b # , &PDIR PDIR = PDIR & (~0x08) PDIR = PDIR & (~BIT3) Change all bits in PDIR Only PDIR.3 = 1 Set PDIR.3=1 Set PDIR.3=1 Change all bits in PDIR Only PDIR.3 = 0 Clear PDIR.3=0 Clear PDIR.3= Example (1) : Configure P2.3 as output & send Logic HIGH #include <msp430.h> // Specific device void main (void) { WDTCTL = WDTPW WDTHOLD; // Stop watchdog timer P2SEL = P2SEL & (~BIT3); // Select P2.3 as GPIO pin (P2SEL.3 =0) P2DIR = P2DIR BIT3 ; // Set P2.3 as output pin (P2DIR.3=1) P2OUT = P2OUT BIT3 ; // Send Logic HIGH at P2.3(P3OUT.3 =1) }

10 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT (a). LED Interfacing LEDs can be connected in two standard ways, shown in Figure. A series resistor (220 Ω to 1 KΩ) limits the current through LED. In the active high circuit, LED ON if the pin outputs Logic HIGH In the active low circuit, LED ON if the pin outputs Logic LOW A microcontroller is typically better at sinking current than sourcing it. Hence, the second method is employed for many applications. The complete program needs to carry out the following tasks: 1. Configure the microcontroller. 2. Set the relevant pins to be outputs by setting the appropriate bits of P2DIR. 3. Illuminate the LEDs by writing to P2OUT. 4. Keep the microcontroller busy in an infinite, empty loop. Example (2) : Program in C to light LEDs with a constant pattern. Let LED-1 is connected at P2.3 (active High circuit) & LED-2 at P2.4 (active Low circuit) as shown in Fig. #include <msp430.h> // Specific device void main (void) { WDTCTL = WDTPW WDTHOLD; // Stop watchdog timer P2SEL = P2SEL & ~(BIT3+BIT4); // Select P2.3 & P2.4 as GPIO pins P2DIR = P2DIR BIT3+BIT4 ; // Set P2.3 &P2.4 as output pins P2OUT = P2OUT BIT3 ; // Send Logic-1 at P2.3 (LED 1 ON) active High P2OUT = P2OUT & ~BIT4 ; // Send Logic-0 at P2.3 (LED 2 ON) active Low for ( ; ; ) // Loop forever { // doing nothing } }

11 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT (b). Switches Interfacing & Pull up/down Resistors Concepts Pull-up and pull-down resistors are often used when interfacing a switch or some other inputs with a microcontroller. Pull-up and Pull-down resistors are used in electronic logic circuits to ensure that inputs to the micro-controller settle at expected logic levels if external devices are disconnected or high-impedance. These resistors used in logic circuits to ensure a well-defined logical level at a pin under all conditions. This is because, when no external devices are connected to an input pin, it doesn't mean that it is a logical ZERO' Digital logic circuits have three logic states: high, low and floating (or high impedance). The high-impedance state occurs when the pin is not pulled to a high or low logic level, but is left floating instead. A good illustration of this is an unconnected input pin of a microcontroller. It is neither in a HIGH or LOW logic state, and a microcontroller might unpredictably interpret the input value as either a logical HIGH or logical LOW. Pull-up resistors are used to solve the dilemma for the microcontroller by pulling the value to a logical high state, as seen in the Fig.(a). If there weren t for the pull-up resistor, the MCU s input would be floating when the switch is open. Pull-down resistors work in the same manner as pull-up resistors, except that they pull the pin to a logical low value. They are connected between ground and the appropriate pin on a device. An example of a pull-down resistor in a digital circuit can be seen in the Fig.(b). A pushbutton switch is connected between the supply voltage and a microcontroller pin. In such a circuit, when the switch is closed, the micro-controller input is at a logical high value, but when the switch is open, the pull-down resistor pulls the input voltage down to ground (logical zero value), preventing an undefined state at the input.

12 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Reading Input from a Switch The standard way of connecting a simple push button is shown in Figure 4.4. When the switch is open, The voltage at the pin is basically V CC. The pull-up resistor R pull holds the input at logic 1 (voltage V CC) When the switch is closed The pin is connected to the Ground (Logic 0). The input is therefore active low, meaning that it goes low when the button is pressed. (button down input down) A wasted current flows through the pull-up resistors to ground when the button is pressed. This is reduced by making R pull large. Pull-up and pull-down resistors are often used when interfacing a switch or some other input with a microcontroller. Hence, most microcontrollers have internal pull up/down resistors to reduce the no. of external components. Pull-up or pull-down resistors can be activated by setting bits in the PxREN registers, provided that the pin is configured as an input. Application of Pull up/down Resistors: (1) Interfacing of switches / other input devices with microcontrollers (2) A/D converters to provide a controlled current flow into a resistive sensor. (3) I2C protocol bus, where pull-up resistors are used to enable a single pin to act as an input (or) output.

13 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Example (3) : Program to light LED when button B1 is pressed Let LED1 is connected at P2.3 (active Low circuit) and Push button is connected at P2.1 with internal Pull-up resistor enabled #include <msp430.h> // Specific device void main (void) { WDTCTL = WDTPW WDTHOLD; // Stop watchdog timer P2SEL = P2SEL & ~(BIT1+BIT3); P2DIR = P2DIR BIT3 ; // Select P2.1 & P2.3 as GPIO pins // Set P2.3 as output pin (LED1) P2DIR = P2DIR & ~BIT1 ; // Set P2.1 as input pin (Switch) P2REN = P2REN & ~BIT1 ; // Pull-up/down Resistor Enable for P2.1 P2OUT = P2OUT & ~BIT1 ; // Select Pull-up Resistors for P2.1 P2OUT = P2OUT BIT3 ; // Preload LED1 off (active Low ) for ( ; ; ) // Loop forever { if ((P2IN & BIT1) == 0) // Is button down? (active low) { // Yes: Turn LED1 on (active low!) P2OUT = P2OUT & ~BIT3 ; // Send Logic-0 at P2.1 (LED1 ON) } else { // No: Turn LED1 off (active low!) P2OUT = P2OUT BIT3; // Send Logic-1 at P2.1 (LED1 OFF) } } // end for loop }

14 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Processing of Interrupts in MSP430 : Interrupt : Interrupt is an event that causes the microcontroller to stop the normal program execution. Interrupts are usually generated by hardware and often indicate that an event has occurred that needs an urgent response. Reset is usually generated by hardware, either when power is applied (or) when some unfortunate things have happened and normal operation cannot continue. This can happen accidentally if the watchdog timer has not been disabled, which is easy to forget. A reset causes the device to (re)start from a well-defined state. Why Interrupts? Interrupts are commonly used for a range of applications: Urgent tasks that must be executed promptly at higher priority than the main code. Infrequent tasks, such as handling slow input from humans. This saves the overhead of regular polling. Waking the CPU from sleep. This is particularly important in the MSP430, which typically spends much of its time in a low-power mode and can be awakened only by an interrupt. Calls to an operating system. These are often processed through a trap or software interrupt instruction but the MSP430 does not have one. External & Internal interrupts Interrupts are generated by external devices connected to the microcontroller (or) Interrupts can be requested by most peripheral modules in the core of the MCU, such as the clock generator, Timer, ADC, Serial UART.. etc. Maskable & Non-maskable interrupts Most interrupts are maskable, which means that they are effective only if GIE =1 in the status register (SR). They are ignored if GIE is clear. Therefore both the enable bit in the module and GIE must be set for interrupts to be generated. However, the non-maskable interrupts cannot be suppressed by clearing GIE. There are 3- non maskable interrupts: Oscillator fault (OFIFG) Access violation to flash memory (ACCVIFG) An active edge on the external RST/NMI pin Interrupt Service Routine : The code to handle an interrupt is called an interrupt handler or Interrupt Service Routine (ISR). ISR is something like a subroutine called by hardware and Interrupts must be handled in such a way that the code that was interrupted can be resumed without error.

15 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Interrupt Vector : The CPU must be told where to fetch the next instruction following an interrupt or reset. The address of ISR is called as Interrupt vector The MSP430 uses vectored interrupts. Each ISR has its own vector, which is stored at a predefined address in a vector table at the end of the program memory (addresses 0xFFC0 0xFFFF). When the interrupt is enabled, the present PC value is stored at the stack top and loaded with the address of ISR which is available in Interrupt vector table. The vector table is at a fixed location, but the ISRs themselves can be located anywhere in memory. The vectors for the maskable interrupts depend on the peripherals in a particular device and are listed in a table of Interrupt Vector Addresses in the data sheet. Processing of Interrupts: The request for an interrupt is finally passed to the CPU if the GIE bit is set. Hardware then performs the following steps to launch the ISR: 1. The CPU completes the execution of current instruction. 2. The PC, which points to the next instruction, is pushed onto the stack. 3. The SR is pushed onto the stack. 4. The interrupt with the highest priority is selected if multiple interrupts are waiting for service. 5. The interrupt request flag is cleared automatically for vectors that have a single source. 6. The SR is cleared, which has two effects. First, further maskable interrupts are disabled because the GIE bit is cleared; non-maskable interrupts remain active. Second, it terminates any low-power mode. 7. The interrupt vector is loaded into the PC and the CPU starts to execute the interrupt service routine at that address. This sequence takes six clock cycles in the MSP430 before the ISR commences. The stack at this point is shown in above figure. The delay between an interrupt being requested and the start of the ISR is called the latency. If the CPU is already running, it takes more than 6- cycles to start the execution of ISR (cycles required to execute the current instruction + 6 cycles)

16 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT An interrupt service routine must always finish with the special instruction reti (return from interrupt), which has the following actions. This takes a further five cycles in the MSP430. The stack is restored to its state before the interrupt was accepted. 1. The SR pops from the stack. All previous settings of GIE and the mode control bits are now in effect, regardless of the settings used during the interrupt service routine. In particular, this re-enables maskable interrupts and restores the previous low-power mode of operation if there was one. 2. The PC pops from the stack and execution resumes at the point where it was interrupted. Alternatively, the CPU stops and the device reverts to its low-power mode before the interrupt. Example (4) : Program to configure P2.1 as an interrupt pin ( falling edge interrupt ) #include <msp430.h> // Specific device void main (void) { WDTCTL = WDTPW WDTHOLD; // Stop watchdog timer P2SEL = P2SEL BIT1; // Select P2.1 as Interrupt pin P2IE = P2IE BIT1 ; // Enable interrupt P2.1 P2IES = P2IES BIT1; // Falling edge (1 0) P2IFG = P2IFG & ~BIT1; // Clear interrupt flag for P2.1 while(1) { if ((P2IFG & BIT1) == 1) { // do something } } // end while } // Loop forever

17 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Clock System in MSP430 : All microcontrollers contain a clock module to drive the CPU and peripherals. The basic clock module supports low system cost and ultralow power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The basic clock module can be configured to operate without any external components, with one external resistor, with one or two external crystals, or with resonators, under full software control. Three clock signals are available from the basic clock module: (1) MCLK : Master clock is used by CPU and system (2) SMCLK : Subsystem Master clock is distributed to peripherals (3) ACLK : Auxiliary clock is also distributed to peripherals. Most peripherals can choose either SMCLK (MHz range) or ACLK, which is typically much slower and usually 32 KHz. A few peripherals such as A/D converters can use MCLK and some peripherals such as timers, have their own clock inputs. Some peripherals have their own dividers for their clock sources, which gives yet more control. MCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available onchip), or DCOCLK. MCLK is divided by 1, 2, 4, or 8. MCLK is used by the CPU and system. SMCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4, or 8. SMCLK is software selectable for individual peripheral modules. The auxiliary clock ACLK can be derived only from LFXT1 in most devices so ACLK will not be available if there is no crystal. ACLK is software selectable for individual peripheral modules as LFXT1CLK or VLOCLK. ACLK is divided by 1, 2, 4, or 8.

18 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT The basic clock module includes three or four clock sources: (1) Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It is usually used with a low-frequency watch crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz) in most devices. An external clock signal can be used instead of a crystal if it is important to synchronize the MSP430 with other devices in the system. The LFXT1 oscillator supports ultra-low current consumption using a 32 KHz watch crystal in LF mode. (2) High-frequency crystal oscillator, XT2: Some devices have a second crystal oscillator XT2. It is Similar to LFXT1 except that it is restricted to high frequencies. It can be used with standard crystals, resonators, or external clock sources in the 400-kHz to 16-MHz range. (3) Very low-power, low-frequency oscillator, VLO: The VLO is an internal RC oscillator that runs at around 12 KHz and can be used instead of LFXT1 in some newer devices. It saves the cost and space required for a crystal and reduces the current drawn. It is an alternative to LFXT1 when the accuracy of a crystal is not needed. Devices without LFXT1 (for example, the MSP430G22x0) should be configured to use the VLO as ACLK. (4) Digitally controlled oscillator, DCO: The DCO is an integrated digitally controlled oscillator and it is available in all devices. It is basically a highly controllable RC oscillator that starts in less than 1 sec in newer devices. The DCO frequency can be adjusted by software using the DCOx, MODx, and RSELx bits. Both MCLK and SMCLK are supplied by an internal digitally controlled oscillator (DCO), which is controlled by a frequency-locked loop (FLL). Software can disable DCOCLK by setting SCG0 when it is not used to source SMCLK or MCLK in active mode Control of the Clock Module through the Status Register : The clock module is controlled by 4 bits in the STATUS REGISTER as well as its own peripheral registers. All bits are clear in the full-power, active mode. SCG1 (System clock generator 1) : When set, turns off the SMCLK. SCG0 (System clock generator 0) : When set, turns off the DCO DC generator for DCO. if DCO-CLK is not used for MCLK or SMCLK. OSCOFF (Oscillator OFF ) : When set, turns off the VLO and LF XT1 crystal oscillator if LFXT1-CLK is not used for MCLK or SMCLK. CPUOFF : When set, turns off the MCLK, which stops the CPU.

19 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Low-power modes of MSP430 : Why low power? Portable & mobile devices are getting popular, which have limited power sources, e.g., battery Energy conservation for our planet Power generates heat Power optimization becomes a new dimension in system design, besides performance and cost Principles for Low-Power Applications MSP430 provides many features for low-power operations. Put the system in low-power modes/use low-power modules as much as possible Provide clocks of different frequencies frequency scaling Lower supplied voltage voltage scaling Turn off clocks when no work to do clock gating Use interrupts to wake up the CPU, return to sleep when done Peripherals should be switched on only when needed. Use low-power integrated peripheral modules in place of software, for ex.-timer For longer software routines, single-cycle CPU registers should be used. The MSP430 family is designed for ultralow-power applications and uses different operating modes. The operating modes take into account three different needs: Ultralow-power Speed and data throughput Minimization of individual peripheral current consumption Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: Enter interrupt service routine: The PC and SR are stored on the stack CPUOFF, SCG1, & OSCOFF bits are automatically reset enters active mode MCLK must be started so CPU can handle interrupt Options for returning from the interrupt service routine: The original SR is popped from the stack, restoring the previous operating mode. The SR bits stored on the stack can be modified within the ISR to return to a different operating mode when the RETI instruction is executed.

20 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT The low-power modes 0 to 4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Control of Low-Power Modes : The CPUOFF, OSCOFF, SCG0, and SCG1 bits control the mode of operation of the MSP430MCU. All systems are fully operational when all bits are clear. Setting combinations of these bits puts the device into one of its low-power modes. SCG1 (System clock generator 1) : When set, turns off the SMCLK. SCG0 (System clock generator 0) : When set, turns off the DCO DC generator for DCO. if DCO-CLK is not used for MCLK or SMCLK. OSCOFF (Oscillator OFF ) : When set, turns off the VLO and LF XT1 crystal oscillator if LFXT1-CLK is not used for MCLK or SMCLK. CPUOFF : When set, turns off the MCLK, which stops the CPU. Operating Modes For Basic Clock System SCG1 SCG0 OSCOFF CPUOFF Mode CPU and Clocks Status Active CPU is active, all enabled clocks are active LPM LPM LPM LPM3 CPU & MCLK are disabled. SMCLK & ACLK are active CPU & MCLK are disabled. ACLK is active. DCO and DC generator are disabled if it is not used for SMCLK CPU, MCLK, SMCLK are disabled. DC generator remains enabled. ACLK is active. CPU, MCLK, SMCLK, DCO & DC generators are disabled. ACLK is active LPM4 CPU and all clocks disabled

21 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Active mode: CPU, all clocks, and enabled modules are active, I 300µA The MSP430 starts up in this mode, which must be used when the CPU is required to run code. An interrupt automatically switches the device to active mode. The current can be reduced by running the MSP430 at the lowest supply voltage consistent with the frequency of MCLK. If V CC = 1.8V at f DCO = 1MHz, I 200µA LPM-0: CPU and MCLK are disabled, SMCLK and ACLK remain active, I 85 µa This is used when the CPU is not required but some modules require a fast clock from SMCLK and the DCO. LPM-3: CPU, MCLK, SMCLK, and DCO are disabled; only ACLK remains active; I 1 µa. This is the standard low-power mode when the device must wake itself at regular intervals and therefore needs a (slow) clock. It is also required if the MSP430 must maintain a real-time clock. The current can be reduced to about 0.5_A by using the VLO instead of an external crystal in a MSP430F2xx if f ACLK need not be accurate. LPM-4: CPU and all clocks are disabled, I 0.1 µa. The device can be wakened only by an external signal. This is also called RAM retention mode. The MSP430x5xx has LPM5, in which the voltage regulator of the Power Management Module (PMM) is disabled. All RAM and register contents are lost, as well as, I/O configuration. Wake-up is possible via a power sequence or an RST/NMI event. On some devices, wake-up from I/O is also possible. The MSP430 typical current consumption in various modes is shown in Figure.

22 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT The following function puts the device into LPM3. The MSP430 can be awakened only by an interrupt so these must be enabled by setting the GIE bit in SR if it has not been done already. low_power_mode_3 (); // enter LPM3 with interrupts enabled The only clock that runs in LPM3 is ACLK. This means that the DCO must be started to provide MCLK before the ISR can be executed. The following function is used to exit the low power mode low_ power_mode_off_on_exit() // Restore Active Mode on return

23 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Watchdog Timer : 1. A watchdog timer is an electronic timer that is used to detect and recover from computer malfunctions. 2. The Watchdog Timer (WDT) module restarts the system on occurrence of a software problem (or) if a selected time interval expires. 3. During normal operation, the system regularly restarts the watchdog timer to prevent it from elapsing, or "timing out". If the system fails to restart the watchdog due to a hardware fault (or) program error, the timer will elapse and generate a timeout signal. 4. The timeout signal is used to initiate corrective actions like placing the system in a safe state and restoring normal system operation. 5. Microcontrollers often include an integrated, on-chip watchdog. The watchdog and CPU may share a common clock signal, as shown in above figure, or they may have independent clock signals. 6. Time intervals: Watchdog timers may have either fixed or programmable time intervals. Some watchdog timers allow the time interval to be programmed by selecting from among a few selectable, discrete values. In others, the interval can be programmed to arbitrary values. Typically, watchdog time intervals range from ten milliseconds to a minute or more. 7. Corrective actions : A watchdog timer may initiate any of several types of corrective actions, including processor reset, non-maskable interrupt, power cycling, fail-safe state activation, or combinations of these, depending on its architecture. In embedded systems and control systems, watchdog timers are often used to activate fail-safe circuitry, which forces all control outputs to safe states (e.g., turns off motors, heaters, and high-voltages) to prevent injuries and equipment damage while the fault persists. 8. Remember that the watchdog is active by default and must either be disabled or regularly cleared before it rolls over. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

24 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Features of the watchdog timer module include: Four software-selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST/NMI pin function Selectable clock source Can be stopped to conserve power Clock fail-safe feature Watchdog Timer Operation The main purpose of the watchdog timer is to protect the system against failure of the software, such as the program becoming trapped in an unintended, infinite loop. Left to itself, the watchdog counts up and resets the MSP430 when it reaches its limit. The code must therefore keep clearing the counter before the limit is reached to prevent a reset. The watchdog is always active after the MSP430 has been reset. By default the clock is SMCLK, which is in turn derived from the DCO at about 1 MHz. The default period of the watchdog is the maximum value of 32,768 counts, which is therefore around 32 ms. The WDT is clocked from either SMCLK (default) or ACLK, according to the WDTSSEL bit. The reset output can be selected from bits 6, 9, 13, or 15 of the counter. Thus the period is 2 6 = 64, 512, 8192, or 32,768 (default) times the period of the clock. This is controlled by the WDTISx bits in WDTCTL. The intervals are roughly 2, 16, 250, and 1000 ms if the watchdog runs from ACLK at 32 KHz. The operation of the watchdog is controlled by the 16-bit password-protected register WDTCTL. Any read or write access must use word instructions and write accesses must include the write password 0x5A in the upper byte. Any write to WDTCTL with any value other than 0x5A in the upper byte is a security key violation and triggers a Reset regardless of timer mode. Any read of WDTCTL reads 0x69 in the upper byte. The lower byte of WDTCTL contains the bits that control the operation of the watchdog timer, shown in Figure 8.1.

25 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Bits 15-8 WDTPW Watchdog timer Password Always read as 0x69. Must be written as 0x5A, or Reset is generated Bit 7 WDTHOLD Watchdog timer Hold 1 Stops the watchdog timer 0 Watchdog timer is not stopped Bit 6 WDTNMIES Watchdog timer NMI edge select Selects the interrupt edge for the NMI 1 NMI on falling edge 0 NMI on rising edge Bit 5 WDTNMI Watchdog timer NMI select 1 NMI function 0 Reset function Bit 4 WDTTMSEL Watchdog timer Mode select 1 Interval timer mode 0 Watchdog mode Bit 3 WDTCNTCL Watchdog timer Counter clear 1 clears the count value to 0000H 0 No action Bit 2 WDTSSEL Watchdog timer clock source select 1 ACLK 0 SMCLK Bit 1 & Bit 0 WDTIS 1 & WDTIS 0 Watchdog Timer Interval Select 00 Watchdog clock source /32, Watchdog clock source /8, Watchdog clock source / Watchdog clock source /64

26 IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT Example (5) : Program to light LED when button B1 is pressed using interrupt and Low-power mode 4 Let LED is connected at P2.3 (active Low circuit) Let Push button is connected at P2.1 with internal Pull-up resistor enabled P2.1 is to be configured to receive the interrupt from switch #include <msp430.h> // Specific device void main (void) { WDTCTL = WDTPW WDTHOLD; // Stop watchdog timer P2SEL = P2SEL & (~BIT3); P2DIR = P2DIR BIT3 ; // Select P2.3 as GPIO pins // Set P2.3 as output pin (LED1) P2SEL = P2SEL BIT1; // Select P2.1 as Interrupt pin P2IE = P2IE & ~BIT1 ; // Enable Interrupt P2.1 P2IES = P2IES BIT1; // Interrupt Edge Select Falling edge (1) P2OUT = P2OUT BIT3 ; // Preload LED1 off (active Low ) } do { P2IFG = 0; // Clear interrupt flags for P2 } while (P2IFG!=0) for ( ; ; ) // loop forever { low_power_mode_4(); // enter into low power mode 4 } #pragma vector = PORT2_VECTOR interrupt void PORT2_ISR (void) { P2OUT = P2OUT ^ BIT3; // Toggle LED P2IES = P2IES ^ BIT3; // Toggle edge sensitivity do { P2IFG = 0; // Clear any pending interrupts... } while (P2IFG!= 0); //... until none remain }