Interconnects, Memory, GPIO

Transcription

1 Interconnects, Memory, GPIO Dr. Francesco Conti Slide contributions adapted from STMicroelectronics and from Dr. Michele Magno, others

2 Processor vs. MCU

3 Pipeline Harvard architecture Separate Instruction & Data buses enable parallel fetch & store Advanced 3-Stage Pipeline Includes Branch Forwarding & Speculation Additional Write-Back via Bus Matrix

4 Example: STM32 Microcontroller System Core and operating conditions - ARM Cortex -M DMIPS/MHz up to 24 MHz V to 3.6 V range to +105 C Rich connectivity - 8 communication periphs Advanced analog - 12-bit1.2 µs conversion time ADC - Dual channel 12-bit DAC Enhanced control - 16-bit motor control timer - 6x 16-bit PWM timers CORTEX TM -M3 CPU 24 MHz JTAG/SW Debug Nested vect IT Ctrl 1 x Systick Timer DMA 7 Channels 1 x 16-bit PWM Synchronized AC Timer Up to 16 Ext. ITs 37/51/80 I/Os 1 x SPI 1 x USART/LIN Smartcard/IrDa Modem Control ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz) Bridge ARM Peripheral Bus (max 24MHz) Flash I/F Bridge 64kB - 128kB Flash Memory 8kB SRAM 20B Backup Data Clock Control ARM Peripheral Bus (max 24MHz) 6 x 16-bit Timer 2 x Watchdog (independent & window) 2-channel 12-bit DAC 1 x 12-bit ADC up to16 channels Temperature Sensor Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators 32KHz + 4~25MHz Int. RC oscillators 40KHz + 8MHz PLL RTC / AWU 1 x CEC 2 x USART/LIN Smartcard / IrDa Modem Control 1 x SPI 2 x I 2 C

5 Advanced Microcontroller Bus Architecture Advanced Microcontroller Bus Architecture (AMBA) is a standard provided by ARM AHB Advanced High-Performance Bus High performance Pipelined operation Burst transfers Multiple bus masters Split transactions APB Advanced Peripheral Bus Low power Latched address/control Simple interface Suitable for many peripherals

6 Bus Arbitration: AHB Example Arbiter Master #1 #1 Master #2 Address and control mux #2 Master #3 Write data mux Read data mux #3 #4 Decoder

7 Bus Arbitration: AHB Example Arbiter Master #1 #1 Master #2 Address and control mux #2 Master #3 Write data mux Read data mux #3 1. Masters #1,2 try to make an access request in the same cycle; #1 to slave #2, #2 to slave #4 Decoder #4

8 Bus Arbitration: AHB Example Arbiter Master #1 #1 Master #2 Address and control mux #2 Master #3 Write data mux Read data mux #3 2. Only master #2 is granted access by the arbiter and its request is propagated to the slaves Decoder #4

9 Bus Arbitration: AHB Example Arbiter Master #1 #1 Master #2 Address and control mux #2 Master #3 Write data mux Read data mux #3 3. Only slave #4 which is addressed by master #2 issues a response propagated to the correct master #2 by the decoder Decoder #4

10 Example: Cortex M3 Core IF Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA BusMatrix added to Harvard architecture allows parallel access Efficient DMA and Rapid data flow Direct path to SRAM through arbiter, guarantees alternating access Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer Increase Peripherals Speed for better performance Dual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and Low Speed APB (APB1) up to 36MHz Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz toggling I/Os)

11 The Zoo of Memory in MCUs SRAM Volatile memory for runtime execution Fastest access, low amount (usually <100KB, always <1MB) Used in the usual fashion Flash ROM On-chip non-volatile memory used for code or data storage 8-512Kb, about 10k write cycles Bootloader: protected section to upload code in flash Ferroelectric Random Access Memory (FRAM) Forefront of next generation non-volatile memory technology On-chip non-volatile memory faster (50ns) and lower power (250x less) than Flash. External memory Connected via serial (I2C, SPI) or dedicated (FSMC) interface

12 Memory - Address Space On-Chip Flash/ROM and RAM memory Not only memory: everything is mapped into a single, contiguous address space: All memory, including RAM, Flash/ROM, information memory, special function registers (SFRs), and peripheral registers. Flash / ROM RAM Peripherals Memory Address Description Access End: 0FFFFh Interrupt Vector Table Word/Byte Start: 0FFE0h End: 0FFDFh Flash/ROM Word/Byte 0F800h Start *: 01100h End *: 010FFh 0107Fh Information Memory Start: 01000h (Flash devices only) End: 0FFFh Boot Memory Start: 0C00h (Flash devices only) End *: Start: End: Start: End: Start: End: Start: 09FFh 027Fh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h RAM 16-bit Peripheral modules 8-bit Peripheral modules Special Function Registers Word/Byte Word/Byte Word/Byte Word Byte Byte 12

13 General Purpose I/O Each MCU pin can be used as a General Purpose digital input or output. Input: read binary value of specified pin, used for simple communication with external world (e.g. buttonstate) Can be configured to trigger interrupt Output: set binary value of specified pin (e.g. LED, simple signal trigger)

14 GPIO - Inside Inputs/Outputs Each pin is independent Ports (out) and Pins (in) are different!!! Output section Input section

15 GPIO in STM32 The STM32 is well served with general purpose I/O pins, having up to 81 bidirectional I/O pins with interrupt capability. The I/O pins are arranged as five ports each having 16 I/O lines. PA [15:0] PB [15:0] PC [15:0] PD [15:0] PE [15:0] GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E APB2

16 GPIO General Purpose I/O Avoid floating inputs!!! Use a pull-up/down resistor, GND, or internal programmable logic To Input Logic VCC Button 5.6KW Button produces either Vcc or Floating input. Adding a pull-down resistor fixes it. VCC Button 5.6KW Some ports have internal programmable resistors Port Pin

17 Microcontroller External Pins Configuration MCUs are often pin-limited Not enough I/O pins for all I/O peripherals and functions!

18 Microcontroller External Pins Configuration MCUs are often pin-limited Not enough I/O pins for all I/O peripherals and functions! Pins have to be multiplexed (shared) between peripherals and functions

19 Microcontroller External Pins Configuration MCUs are often pin-limited Not enough I/O pins for all I/O peripherals and functions! Pins have to be multiplexed (shared) between peripherals and functions Most pins can be configured for several functions: As input or output pin As an interrupt pin Setup a pull-up / pull-down internal resistor (NO floating pins!)

20 Microcontroller External Pins Configuration MCUs are often pin-limited Not enough I/O pins for all I/O peripherals and functions! Pins have to be multiplexed (shared) between peripherals and functions Most pins can be configured for several functions: As input or output pin As an interrupt pin Setup a pull-up / pull-down internal resistor (NO floating pins!) Assigned as general-purpose I/O (GPIO) or to a specific peripheral Digital peripherals such as UARTs, SPIs, I2Cs Analog peripherals such as ADCs or DACs

21 Microcontroller External Pins Configuration Example to understand how this functionality works in a MCU the specific circuit and register may change wildly between MCUs Memory-Mapped registers Function Select Register PxSEL Interrupt Edge Select Register PxIES Interrupt Enable Register PxIE Interrupt Flag Register PxIFG Direction Register PxDIR PAD 1 Output Register PxOUT Input Register PxIN

22 Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): GPIOC_LED0_ADDR

23 Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): GPIOC_LED0_ADDR

24 Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): STORE GPIOC_LED0_ADDR,0x1 GPIOC_LED0_ADDR

25 Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): STORE GPIOC_LED0_ADDR,0x1 GPIOC_LED0_ADDR

26 Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): STORE GPIOC_LED0_ADDR,0x1 GPIOC_LED0_ADDR