5 MEMORY. Overview. Figure 5-0. Table 5-0. Listing 5-0.

Transcription

1 5 MEMORY Figure 5-0. Table 5-0. Listing 5-0. Overview The ADSP-2191 contains a large internal memory and provides access to external memory through the DSP s external port. This chapter describes the internal memory and how to use it. For information on configuring, connecting, and timing accesses to external memory, see Interfacing to External Memory on page There are 64K words of internal SRAM memory on the ADSP This space is divided into two 32K-word blocks: Block 0 (24-bit) and Block 1 (16-bit). There are 64K words reserved for internal ROM memory on the DSP. The ADSP-2191 uses approximately 1K word of this space for boot routines. Including internal and external memory, the DSP can address 16M words of memory space. External memory connects to the DSP s external port, which extends the DSP s address and data buses off the DSP. The DSP can make 16- or 24-bit accesses to external memory for data or instructions. The DSP s external port automatically packs external data into the appropriate word width during data transfer. Table 5-1 shows the access types and words for DSP external memory accesses. Table 5-1. Internal-to-External Memory Word Transfers Word Type Transfer Type Instruction 24-bit word transfer 1 Data 16-bit word transfer 1 Each packed 24-bit word requires two transfers over 16-bit bus. ADSP-219x/2191 DSP Hardware Reference 5-1

2 Overview Most microprocessors use a single address and data bus for memory access. This type of memory architecture is called Von Neumann architecture. But, DSPs require greater data throughput than Von Neumann architecture provides, so many DSPs use memory architectures that have separate buses for program and data storage. The two buses let the DSP get a data word and an instruction simultaneously. This type of memory architecture is called Harvard architecture. ADSP-219x family DSPs go a step farther by using a modified Harvard architecture. This architecture has program and data buses, but provides a single, unified address space for program and data storage. While the Data Memory (DM) bus only carries data, the Program Memory (PM) bus handles instructions or data, allowing dual-data accesses. DSP core and DMA-capable peripherals share accesses to internal memory. Each block of memory can be accessed by the DSP core and DMA-capable peripherals in every cycle, but a DMA transfer is held off if contending with the DSP core for access. A memory access conflict can occur when the processor core attempts two accesses to the same internal memory block in the same cycle. When this conflict happens, an extra cycle is incurred. The DM bus access completes first and the PM bus access completes in the following (extra) cycle. During a single-cycle, dual-data access, the processor core uses the independent PM and DM buses to simultaneously access data from both memory blocks. Though dual-data accesses provide greater data throughput, there are some limitations on how programs may use them. The limitations on single-cycle, dual-data accesses are: The two pieces of data must come from different memory blocks. If the core tries to access two words from the same memory block (over the same bus) for a single instruction, an extra cycle is needed. For more information on how the buses access these blocks, see Figure ADSP-219x/2191 DSP Hardware Reference

3 Memory The data access execution may not conflict with an instruction fetch operation. If the cache contains the conflicting instruction, the data access completes in a single-cycle and the sequencer uses the cached instruction. If the conflicting instruction is not in the cache, an extra cycle is needed to complete the data access and cache the conflicting instruction. For more information, see Instruction Cache on page 3-9. Efficient memory usage relies on how the program and data are arranged in memory and varies with how the program accesses the data. For the most efficient (single-cycle) accesses, use the above guidelines for arranging data in memory. Internal Address and Data Buses As shown in Figure 5-1, the DSP has two internal buses connected to its internal memory, the Program Memory (PM) bus and Data Memory (DM) bus. The I/O processor which is the global term for the DMA controllers, DMA channel arbitration, and peripheral-to-bus connections also is connected to the internal memory and external port. The PM bus, DM bus, and I/O processor (for DMAs) share two memory ports; one for each block. Memory accesses from the DSP s core (computational units, data address generators, or program sequencer) use the PM or DM buses. The I/O processor also uses the DM bus for non-dma memory accesses (e.g., host port direct reads and writes), but uses a separate connection to the memory s ports for DMA transfers. Using this separate connection and cycle-stealing DMA, the I/O processor can provide data transfers between internal memory and the DSP s communication ports (external port, host port, serial ports, SPI ports, and UART port) without hindering the DSP core s access to memory. While the DSP s internal memory is divided into blocks, the DSP s external memory spaces is divided into banks. External memory banks have ADSP-219x/2191 DSP Hardware Reference 5-3

4 Overview INTERNAL MEMORY (PAGE 0) EXTERNAL MEMORY (PAGES 1-254) BLOCK 1 (0X8000-0XFFFF, 16-BIT WORDS) ADDRESS DATA (STARTING AT 0X ) ADDRESS DATA BLOCK 0 (0X0000-0X7FFF, 24-BIT WORDS) ADDRESS DATA 22 8/16 (SEE NOTE) EXTERNAL PORT PM ADDRESS BUS PM DATA BUS PX BUS EXCHANGE REGISTER DM ADDRESS BUS 8 DM DATA BUS NOTE: EITHER THE MEMORY BUSES OR A DMA CHANNEL MAY ACCESS MEMORY, BUT NOT BOTH SIMULTA- NEOUSLY THE MEMORY BUSES MAY USE ANY TWO PATHS SIMULTANEOUSLY ADDRESSES AND DATA FOLLOW PARALLEL PATHS DMA ADDR DMA DATA I/O ADDR I/O DATA I/O PROCESSOR (DMA CONTROLLERS AND DMA CHANNEL ARBITRATION) ADDR DATA (FOR DMA OR EXT. I/O MEM.) Figure 5-1. ADSP-2191 Memory and Internal Buses Block Diagram 5-4 ADSP-219x/2191 DSP Hardware Reference

5 Memory associated memory select (MSx) pins and may be configured for size, clock ratio, and access waitstates. For more information, see External Memory Space on page The DSP core s PM bus and DM bus and I/O processor can try to access internal memory space or external memory space in the same cycle. The DSP has an arbitration system to handle this conflicting access. Arbitration is fixed at the following priority: (highest priority) DM bus, PM bus, and (lowest priority) I/O processor. Also, I/O processor accesses may not be sequential (beyond each burst access), so the DSP core s buses are never held off for more than four cycles. External Address and Data Buses Figure 5-1 also shows that the PM buses, DM buses, and I/O processor have access to the external bus (pins DATA15 0, ADDR21 0) through the DSP s external port. The external port provides access to system (off-chip) memory and peripherals. This port also lets the DSP access shared memory if connected in a multi-dsp system. Addresses for the PM and DM buses come from the DSP s program sequencer and Data Address Generators (DAGs). The program sequencer and DAGs supply 24-bit addresses for locations throughout the DSP s memory spaces. The DAGs supply addresses for data reads and writes on both the PM and DM address buses, while the program sequencer uses only the PM address bus for sequencing execution. i The external address bus is 22 bits wide on the ADSP-2191(LQFP or PBGA 144-lead packages), so the upper two bits of address do not get generated off-chip. For memory accesses by different functional blocks of the DSP, the upper eight bits of the address the page number come from different page registers. The Data Address Generators DAG1 and DAG2 each are associated with a DAG page (DMPG1, DMPG2) register, the program sequencer has a page register (IJPG) for indirect jumps, and I/O memory ADSP-219x/2191 DSP Hardware Reference 5-5

6 Overview uses the I/O page (IOPG) register. For more information on address generation, see Program Sequencer on page 3-1 or Data Address Generators on page 4-1. Because the DSP s blocks of internal memory are differing widths, placing 16-bit data in block 0 leaves some space unused. For more information on how the DSP works with memory words, see Internal Memory Space on page The PM data bus is 24 bits wide, and the DM data bus is 16 bits wide. Both data buses can handle data words (16-bit), but only the PM data bus carries instruction words (24-bit). At the processor s external port, the DSP multiplexes the three memory buses PM, DM, and I/O to create a single off-chip data bus (DATA15 0) and address bus (ADDR21 0). Internal Data Bus Exchange The internal data buses let programs transfer the contents of one register to another or to any internal memory location in a single cycle. As shown in Figure 5-2, the PM Bus Exchange (PX) register permits data to flow between the PM and DM data buses. The PX register holds the lower eight bits during transfers between the PM and DM buses. The alignment of PX register to the buses appears in Figure 5-2. The PX register is a Register Group 3 (REG3) register and is accessible for register-to-register transfers. i When reading data from program memory and data memory simultaneously, there is a dedicated path from the upper 16 bits of the PMD bus to the Y registers of the computational units. This read-only path does not use the bus exchange circuit. 5-6 ADSP-219x/2191 DSP Hardware Reference

7 Memory 23 0 PM Data Bus (24-bit) (upper 16 bits) (lower 8 bits) PX Register 15 0 DM Data Bus (16-bit) Figure 5-2. PM Bus Exchange (PX) Registers For transferring data from the PMD bus, the PX register is: 1. Loaded automatically whenever data (not an instruction) is read from program memory to any register. For example: AX0 = PM(I4,M4); In this example, the upper 16 bits of a 24-bit program memory word are loaded into AX0 and the lower eight bits are automatically loaded into PX. 2. Read out automatically as the lower eight bits when data is written to program memory. For example: PM(I4,M4) = AX0; In this example, the 16 bits of AX0 are stored into the upper 16 bits of a 24-bit program memory word. The eight bits of PX are automatically stored to the eight lower bits of the memory word. ADSP-219x/2191 DSP Hardware Reference 5-7

8 ADSP-2191 Memory Map For transferring data from the DMD bus, the PX register may be: Loaded with a data move instruction, explicitly specifying the PX register as the destination. The lower eight bits of the data value are used and the upper eight are discarded. PX = AX0; Read with a data move instruction, explicitly specifying the PX register as a source. The upper eight bits of the value read from the register are all zeroes. AX0 = PX; Whenever any register is written out to program memory, the source register supplies the upper 16 bits. The contents of the PX register are automatically added as the lower eight bits. If these lower eight bits of data to be transferred to program memory (through the PMD bus) are important, programs should load the PX register from DMD bus before the program memory write operation. ADSP-2191 Memory Map The ADSP-2191 s memory map appears in Figure 5-3 and has multiple memory spaces: internal memory space, external memory space, system control register memory space, I/O memory space, and boot memory space. 5-8 ADSP-219x/2191 DSP Hardware Reference

9 Memory INTERNAL MEMORY 64K WORD MEMORY PAGES PAGE 255 RESERVED BOOT ROM, 24-BIT ADDRESS 0xFF FFFF 0xFF xFF 0000 LOWER PAGE BOUNDARIES ARE CONFIGURABLE FOR BANKS OF EXTERNAL MEMORY. BOUNDARIES SHOWN ARE BANK SIZES AT RESET. ADDRESS 0xFE FFFF MEMORY SELECTS (MS) FOR PORTIONS OF THE MEMORY MAP APPEAR WITH THE SELECTED MEMORY. EXTERNAL MEMORY (16- BIT) PAGES PAGES PAGES BANK3 (MS3) BANK2 (MS2) BANK1 (MS1) 0xC x BOOT MEMORY 8- OR 16- BIT (BMS) I/O MEMORY 16- BIT 1K WORD PAGES INTERNAL MEMORY PAGES 1 63 PAGE 0 BANK0 (MS0) BLOCK1, 16-BIT BLOCK0, 24-BIT 0x x x x K WORD PAGES x K WORD PAGES 0 7 EXTERNAL (IOMS) INTERNAL ADDRESS 0xFF:0x3FF 0x08:0x000 0x00:0x000 Figure 5-3. ADSP-2191 Memory Map These spaces have the following definitions: Internal memory space. The internal RAM space ranges from address 0x through 0x00 FFFF. The internal (boot kernel) ROM space ranges from address 0xFF 0000 through 0xFF Internal memory space refers to the DSP s on-chip SRAM. External memory space. This space ranges from address 0x through 0xFE FFFF. External memory space refers to off-chip memory that is accessed through data move instructions and is attached to the DSP s external address (ADDR21 0) and data (DATA15 0) buses. During accesses to external memory space, the DSP generates Memory Select (MS3 0) signals for the memory bank that corresponds to the address. ADSP-219x/2191 DSP Hardware Reference 5-9

10 ADSP-2191 Memory Map System control registers. This space is separate from other memory spaces and does not appear in Figure 5-3. This space contains ungrouped registers; not part of a register group. For more information, see System Control Registers on page I/O memory space. This space is separate from other memory spaces and has an address range from address 0x00:0x000 through 0xFF:0x3FF. During accesses to off-chip I/O memory space, the DSP generates an I/O Memory Select (IOMS) signal. For more information, see I/O Memory Space on page Boot memory space. This space is separate from other memory spaces and has an address range from address 0x through 0xFE FFFF. During accesses to boot memory space, the DSP generates a Boot Memory Select (BMS) signal. For more information, see Boot Memory Space on page Internal Memory Space The DSP s internal memory space contains two 32K-word blocks of memory, which occupy Page 0 on the DSP s memory map. The memory map is a unified, continuous address range, but some features of the DSP s architecture lead to these block and page distinctions within the map. These distinctions include: Internal memory block width. Block 0 is 24 bits wide and can contain instructions and data. Block 1 is 16 bits wide and can contain data only. Internal bus width. The PM data bus is 24 bits wide, and the DM data bus is 16 bits wide. While either bus can access either internal memory block for data, only the PM bus can fetch instructions ADSP-219x/2191 DSP Hardware Reference

11 Memory i To Data Address Generators. DAG1 and DAG2 each are associated with a DAG page (DMPG1, DMPG2) register and generate addresses for Block 1 and Block 2. Both DAGs can generate external memory addresses. Page size. Architectural constraints (which are described in the Program Sequencer and Data Address Generators chapters) lead to 64K-word page segmentation of memory a 16-bit address range per page. To move beyond a page range requires changing a value in a page register. These registers hold the upper eight bits of the 24-bit address. There are page registers associated with internal/external/boot memory space and I/O memory space. These registers include: DMPGx, IJPG, and IOPG. execute programs and use data in internal memory, the ADSP-2191 operates similarly to previous ADSP-218x DSPs. For internal memory operations, paging is not required, and the page registers remain at their reset values (Page 0). The DSP s memory architecture permits either bus to access either internal memory block and also permits dual accesses a single cycle operation where each bus accesses a block of memory. To arbitrate simultaneous accesses, the memory interface: Processes a memory read before memory write Processes a DM bus access before a PM bus access Because the internal PM and DM buses are multiplexed at the DSP s external port, external memory accesses differ slightly from internal memory accesses. For more information, see External Memory Space on page Also on-chip, the DSP has an internal boot kernel ROM on memory Page 255. Programs should treat this area as reserved and should not access this area at runtime. ADSP-219x/2191 DSP Hardware Reference 5-11

12 ADSP-2191 Memory Map External Memory Space The DSP s external memory space can address four banks of memory, which contain Page 1 through Page 254 on the DSP s memory map. Programs can configure the number of 64K-word pages per bank, but the addresses for each page are fixed and are part of the unified, continuous address range. For more information on accessing pages through page registers, see Internal Memory Space on page Though external memory is part of the same unified address and page register system as internal memory, the DSP configures and controls access to internal and external memory differently. Items that are unique to external memory accesses include: Memory bank and space selects (MS3 0, BMS, IOMS). The DSP automatically activates an external memory bank or space s select line for each access. For external memory accesses, the DSP activates the bank s select line (Bank 0=MS0 through Bank 3= MS3) based on the memory page of the access. Waitstates. The DSP can apply a selectable number of waitstates for accesses to each external memory bank or space and supports several waitstate modes. Memory bank starting page (bank size). The DSP can select the starting memory page for each external memory bank, allowing the size of each bank to be configured. Bus arbitration. The DSP must be bus master to access external memory. To grant bus mastership to other devices, the DSP has Bus Request (BR) and Bus Grant (BG) pins. If the DSP is stalled waiting to regain bus mastership, the DSP signals this state with the Bus Grant Hung (BGH) pin. External memory access latencies. The DSP s core and peripherals pass data to each other over bus interfaces. Accesses over these interfaces (for example, a core read or write access to external memory) 5-12 ADSP-219x/2191 DSP Hardware Reference

13 Memory i To involve some interface latencies. These latencies vary, depending on the type of access. For a list of external memory access latencies, see Table 7-10 on page execute programs and use data in external memory, the ADSP-2191 operates differently from previous ADSP-218x DSPs paging is required, the interface has more latencies, and (depending on external bus configuration) packing may be required. For more information on these latencies, see Memory Interface Timing on page System Control Registers The DSP has a separate memory space for system control registers. These registers support DSP core operations. The registers in this space include the DAG Base (Bx) registers and the Cache Control (CACTL) register. For more information, see Length and Base (Lx,Bx) Register on page A-24 and Cache Control (CACTL) Register on page A-22. To access system control registers, programs use system control register read/write instructions (Reg()). I/O Memory Space The DSP has an I/O memory space for internal I/O memory-mapped registers and external I/O memory-mapped devices. Similar to but entirely separate from internal and external memory, the addressing of I/O memory is divided into 1K-word pages with Pages 0 7 on-chip and Pages off-chip. Programs select an I/O memory page with the IOPG register. To access I/O memory, programs use the I/O memory read/write instructions (Io()). The on-chip I/O memory contains memory-mapped registers for control, status, and data buffers of DSP peripherals (external port, host port, serial ports, serial peripheral interface ports, and UART port) and peripheral DMA. ADSP-219x/2191 DSP Hardware Reference 5-13

14 ADSP-2191 Memory Map The off-chip I/O memory is for external memory-mapped devices that use the I/O memory interface to communicate with the DSP. If off-chip, the peripherals are attached to the DSP s external address (ADDR21 0) and data (DATA15 0) buses. During accesses to off-chip I/O memory space, the DSP generates an I/O Memory Select (IOMS) signal. i The I/O processor which is the global term for the DMA controllers, DMA channel arbitration, and peripheral-to-bus connections and I/O memory which contains the control, status, and buffer registers for the I/O processor are very different things. The I/O processor does not use the IOPG register for DMA, instead the I/O processor uses DMA page information from a DMA s descriptor. Also, the I/O processor cannot perform DMA to I/O memory; only the DSP core or a host may read or write I/O memory. Boot Memory Space The DSP has a separate external memory space for mapping a boot ROM or FLASH and booting the DSP from this device. This space is separate from other memory spaces and has an address range from address 0x through 0xFE FFFF. Boot memory space refers to off-chip ROM memory that is accessed when the DSP boots from ROM and is attached to the DSP s external address (ADDR21 0) and data (DATA15 0 or DATA7 0) buses. During accesses to boot memory space, the DSP generates a Boot Memory Select (BMS) signal. i Although the most common usage for boot memory space is boot loading at system restart, this memory space also can be accessed at runtime. For more information, see Using Boot Memory Space on page ADSP-219x/2191 DSP Hardware Reference

15 Memory Shadow Write FIFO Because the DSP s internal memory must operate at high speeds, writes to the memory do not go directly into the internal memory. Instead, writes go to a two-deep FIFO called the shadow write FIFO. When an internal memory write cycle occurs, the DSP loads the data in the FIFO from the previous write into memory, and the new data goes into the FIFO. This operation is transparent, because any reads of the last two locations written are intercepted and routed to the FIFO. i Because the ADSP-2191 s shadow write FIFO automatically pushes the write to internal memory as soon as the write does not compete with a read, this FIFO s operation is completely transparent to programs, except in software reset/restart situations. To ensure correct operation after a software reset, software must perform two dummy writes (repeat last write per block) to internal memory before writing the software reset bit. Data Move Instruction Summary Table 5-2 lists the data move instructions. For more information on assembly language syntax, see the ADSP-219x DSP Instruction Set Reference. In Table 5-2, note the meaning of the following symbols: Dreg, Dreg1, Dreg2 indicate any register file location (Register Group) Reg1, Reg2, Reg3, or Reg indicate Register Group 1, 2, 3 or any register Ia and Mb indicate DAG1 I and M registers Ic and Md indicate DAG2 I and M registers ADSP-219x/2191 DSP Hardware Reference 5-15

16 Data Move Instruction Summary Ireg and Mreg indicate I and M registers in either DAG Imm# and Data# indicate immediate values or data of the # of bits Table 5-2. Data/Register Move Instruction Summary Instruction Reg = Reg; DM(<Addr16>), PM(<Addr16>) = Dreg, Ireg, Mreg ; Dreg, Ireg, Mreg = DM(<Addr16>), PM(<Addr16>) ; <Dreg>, <Reg1>, <Reg2> = <Data16>; Reg3 = <Data12>; Io(<Addr10>) = Dreg; Dreg = Io (<Addr10>); Reg(<Addr8>) = Dreg; Dreg = Reg(<Addr8>); 5-16 ADSP-219x/2191 DSP Hardware Reference