T Q S 2 1 L H 8 X 8 1 x x

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1 Specification Quad Small Form-factor Pluggable Plus QSFP+ TO 4xSFP+ AOC Ordering Information T Q S 2 1 L H 8 X 8 1 x x Distance Model Name Voltage Category Device type Interface LOS Temperature TQS-21LH8-X81xx 3.3V With DDMl VCSEL/PIN CML/CML LVTTL 0 C~+70 C 1 Page 1

2 Features Full-Duplex & 10-Gbps per lane with maximum aggregate speed of 40-Gbps. Bit-Error-Rate (BER) better than V single power supply Low power consumption of max. 1.5W at QSFP+ and max. 0.5W at SFP+ side Hot pluggable interface Designed to meet MAS SFF-8436(QSFP+), SFF-8431 and SFF-8472 (SFP+) Programmable EEPROM for serial identification through I 2 C interface RoHS compliant Absolute Maximum Ratings Parameter Symbol Min Max Unit Note Storage temperature TS 0 70 C 1 3.3V Power Supply voltage VCC V Data Input Voltage Single Ended Vin -0.5 Vcc+0.5 V Relative humidity RH 5 85 % 2 Control Input Voltage Vinc V 1. Limited by the fiber cable jacket, not the active ends. 2. Non-condensing. 2 Page 2

3 Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Note Case Operating Temperature Tc 0 70 Power Supply voltage VCC V Data Rate per Channel DR Gbps Bit Error Ratio BER Control Input Voltage High VIN-H 2 Vcc+0.3 V Control Input Voltage Low VIN-L V Two Wire Serial (TWS) Interface Clock Rate 100 khz Differential Data Input / Output Load R 100 Ohms 1. Bit-Error-Rate (BER) is tested with PRBS pattern. 3 Page 3

4 Electrical Characteristics for QSFP+ Module Parameter Min Typ Max Unit Note Transceiver Transceiver Power Consumption 1.5 W Transceiver Power Supply Current 420 ma Transceiver Power-On Initialization Time 2000 ms 1 Transmitter Data Input Differential Peak-to-Peak Voltage Swing 1200 mvpp Differential Input Return Loss Per IEEE 802.3ba, Section 86A db 2 Differential to Common Mode Input Return Loss 10 db 2 J2 Jitter Tolerance 0.17 UI J9 Jitter Tolerance 0.29 UI Receiver Data Output Differential Peak-to-Peak Voltage Swing mvpp 3 Output Transition Time 20% to 80% 28 ps Differential Output Return Loss Per IEEE 802.3ba, Section 86A db 2 Common Mode Output Return Loss Per IEEE 802.3ba, Section 86A db 2 Output Total Jitter 62 ps J2 Jitter Output 0.42 UI J9 Jitter Output 0.65 UI Eye Mask Coordinates: X1, X2; Y1, Y2. Specification Value 0.29, 0.5; 150, 425. UI; mv 4 1. Initialization Time is the time from when the supply voltages reach and remain above the minimum Recommended Operating Conditions to the time when the module enables TWS access. The module at that point is fully functional M to 11.1 GHz according to IEEE 802.3ba specification. 3. AC-Coupled with 100Ω differential output impedance. 4. Hit ratio= per sample with mask definition per below figure. 4 Page 4

5 Electrical Characteristics for SFP+ Module Parameter Min Typ Max Unit Note Transceiver Transceiver Power Consumption 0.5 W Transceiver Power Supply Current 200 ma Transceiver Power-On Initialization Time 300 ms 1 Transmitter Data Input Differential Peak-to-Peak Voltage Swing mvpp Differential Input Return Loss -10 db 2 Receiver Data Output Differential Peak-to-Peak Voltage Swing mvpp 3 Differential Output Return Loss -10 db 2 Output Rise & Fall Time (20-80) 28 ps Total Jitter 0.7 UI Eye Mask Coordinates: X1, X2; Y1, Y2 Specification Value 0.35, 0.5; 150, 425 UI; mv 4 1. Initialization Time is the time from when the supply voltages reach and remain above the minimum Recommended Operating Conditions to the time when the module enables TWS access. The module at that point is fully functional. 2. SDD11/22 differential input and output return loss from 0.05G to 3.9G. 3. AC-Coupled with 100Ω differential output impedance. 4. Hit ratio= per sample with mask definition per below figure. 5 Page 5

6 Optical Cable Specification QSFP+ end to break-out region Parameter Specification Notes Minimum Cable Bending Radius Cable Cross-Section Dimension 30 mm Round Cable with 3-mm in Diameter Cable Cover Type LSZH 1 Cable Length Tolerance L-m + 100/-0 cm TBD SFP+ end to break-out region Parameter Specification Notes Minimum Cable Bending Radius Cable Cross-Section Dimension 30 mm Round Cable with 2-mm in Diameter Cable Cover Type LSZH 1 Standard Cable Length 1-m +0.1m / -0m 1. Cable cover type standard is LSZH. Other types can be available upon request. 6 Page 6

7 QSFP+ Module Pad Assignments and Descriptions. Plug Pin Logic Symbol Description Notes Sequence 1 GND Ground CML-I Tx2n Transmitter Inverted Data Input 3 3 CML-I Tx2p Transmitter Non-Inverted Data Input 3 4 GND Ground CML-I Tx4n Transmitter Inverted Data Input 3 6 CML-I Tx4p Transmitter Non-Inverted Data Input 3 7 GND Ground LVTTL-I ModSelL Module Select 3 9 LVTTL-I ResetL Module Reset 3 10 Vcc Rx +3.3V Power Supply Receiver LVCMOS-I/O SCL 2-wire serial interface clock 3 12 LVCMOS-I/O SDA 2-wire serial interface data 3 13 GND Ground CML-O Rx3p Receiver Non-Inverted Data Output 3 15 CML-O Rx3n Receiver Inverted Data Output 3 16 GND Ground CML-O Rx1p Receiver Non-Inverted Data Output 3 18 CML-O Rx1n Receiver Inverted Data Output 3 7 Page 7

8 Plug Pin Logic Symbol Description Notes Sequence 19 GND Ground GND Ground CML-O Rx2n Receiver Inverted Data Output 3 22 CML-O Rx2p Receiver Non-Inverted Data Output 3 23 GND Ground CML-O Rx4n Receiver Inverted Data Output 3 25 CML-O Rx4p Receiver Non-Inverted Data Output 3 26 GND Ground LVTTL-O ModPrsL Module Present 3 28 LVTTL-O IntL Interrupt 3 29 Vcc Tx +3.3V Power supply transmitter Vcc1 +3.3V Power supply LVTTL-I LPMode Low Power Mode 3 32 GND Ground CML-I Tx3p Transmitter Non-Inverted Data Input 3 34 CML-I Tx3n Transmitter Inverted Data Input 3 35 GND Ground CML-I Tx1p Transmitter Non-Inverted Data Input 3 37 CML-I Tx1n Transmitter Inverted Data Input 3 38 GND Ground GND is the symbol for signal and supply (power) common for the QSFP+ module. All are common within the QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane. 2. Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently. Requirements defined for the host side of the Host Edge Card Connector are listed in Table. Recommended host board power supply filtering is shown in next page. Vcc Rx Vcc1 and Vcc Tx may be internally connected within the QSFP+ module in any combination. The connector pins are each rated for a maximum current of 500 ma. 8 Page 8

9 SFP+ Module Pad Assignments and Descriptions Pin Logic Symbol Description Plug Sequence 1 VeeT Module Transmitter Ground 1 2 Tx_Fault LVTTL-O Not supported. 3 3 Tx_Disable LVTTL-I Not supported. 3 4 SDA LVTTL-I/O 2-wire Serial Interface Data Line 2 5 SCL LVTTL-I/O 2-wire Serial Interface Clock 2 6 Mod_ABS Module Absent 2 7 RS0 LVTTL-I Not supported. 3 8 Rx_LOS LVTTL-O Not supported. 2 9 RS1 LVTTL-I Not supported VeeR Module Receiver Ground 1 11 VeeR Module Receiver Ground 1 12 RD- CML-O Receiver Inverted Data Output 13 RD+ CML-O Receiver Non-Inverted Data Output 14 VeeR Module Receiver Ground 1 15 VccR Module Receiver 3.3 V Supply 4 16 VccT Module Transmitter 3.3 V Supply 4 17 VeeT Module Transmitter Ground 1 18 TD+ CML-I Transmitter Non-Inverted Data Input 19 TD- CML-I Transmitter Inverted Data Input 20 VeeT Module Transmitter Ground 1 Notes 9 Page 9

10 1. Module circuit ground pins are isolated from the module chassis ground. 2. Pullup to VccHost with 4.7k 10k Ω. 3. No connection required. 4. Power supply filtering circuit required. 10 Page 10

11 Mechanical Design Diagram (Unit: mm) 11 Page 11

12 Revision History Date Version Description 08/08/ Update production photo 12 Page 12