Interfacing the internal serial EEPROM
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- Oscar Carson
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1 Interfacing the internal serial EEPROM Stacked into the AT8xEB Microcontrollers 1. Overview The AT8xEB5114 contains an internal serial EEPROM (AT24C02) connected to the microcontroller via two standard ports. This application note aims to help developers take advantage of all the EEPROM characteristics. The AT8xEB5114 is connected to the EEPROM via two standard C51 bidirectional port bits. In order to have the equivalent to a standard TWI (Two Wire Interface) line (open drain with pull-up of few KΩs) with a maximum speed, the bi-directional port bits must be controlled with particular care. The EEPROM and the microcontroller have their own internal brown-out protections, with different thresholds. This means that power supply disturbances can generate a reset on one die whereas the other is still running. The consequence can be a data corruption which can be avoided by implementing special subroutines described in this document. Application Note Rev.
2 2. AT24C02 Internal Connection The internal connection of the EEPROM is shown on Figure 2-1. Figure 2-1. EEPROM and Microcontroller Connections AT8xEBC5114 Vcc A0 A1 A2 WP AT24 C02 Vcc SDA SCL GND P3.6 P3.7 Vss The Vcc and ground pins of the EEPROM are directly connected to the Vcc and the Vss pins of the AT8xEB5114. The SCL and the SDA pins of the EEPROM are internally bonded to the P3.6 and P3.7 ports of the AT8xEB5114. The other pins (Device/page address and WP) are left unconnected. Internal pull-downs in AT24C02 drive A0, A1, A2 and WP to a Low level. 2.1 Standards TWI Line Typically, a standard TWI bus is an open drain transistor connected to the Vcc via a pull-up resistor. The drain is also connected to the Vss pin via the parasitic capacitances. This RC association gives a time constant which gives the maximum speed reachable for the TWI line. This TWI line can be simplified as shown in Figure AT8xEB5114 Application Note
3 AT8xEB5114 Application Note Figure 2-2. Typical TWI Output Stage Vdd Vcc AT24C02 SDA Control GND Rpull-up Cbus load SDA Bus Line The pull-up resistor can be external or integrated on-chip. The Bus load capacitor is the sum of all the parasitic capacitances of all the chips connected to the line. 2.2 EEPROM Ports Characteristics The EEPROM output ports are standard, with a maximum capacitance on SDA pin of 8pF. 2.3 AT8xEB5114 Port Characteristics The AT8xEB5114 ports are standard C51 bidirectional ports. The SCL pin of the EEPROM is an input only, so the SCL pin of the microcontroller can be configured as a push-pull output port in order to obtain the fastest transient as possible. Concerning the SDA pin, it is not possible to configure the microcontroller port as a push-pull output, because SDA pin is sometimes an input and sometimes an output. There is no pull-up on the AT24C02, and there is no additional pull-up on the SDA line. So the SDA pull-up is only made by the AT8xEB5114 SDA port pin. When the AT8xEB5114 port pin is configured as a quasi-bidirectional port, the pull-up resistor is about KΩs when the port pin is low and around 10KΩ when the port pin is high. This means that for a low to high transition, while the level is less than the Vil level, the pull up is 10 times higher than when it has reached this level. It also means that the rising edge is spit into two phases as shown on Figure
4 Figure 2-3. Rising time of a bidirectional externally loaded with a 12pF capacitor Medium pull-up activation (~10KOhms) Vil Weak pull-up (~100KOhms) 2.4 Potential Problem Description in Case of High Speed Transmission On the TWI protocol, the low level can be driven either by the microcontroller or by the EEPROM. Nevertheless, the High level is only driven by the pull-up resistor. In the present case, the pull-up is integrated into the microcontroller. But as explained before, the pull-up value is quite high and the rising-time can be relatively slow. When the microcontroller drives the SDA data line there is absolutely no problem, because the 0 to 1 transition is helped during two clock periods of the microcontroller by a strong pull-up transistor with a resistor value of few tens of Ohms. When the microcontroller receives data from the EEPROM, the rising edge is guaranteed only by the pull-up resistor of the microcontroller. A problem that may occur is that the microcontroller reads a low level instead of a high level because the pull-up has not been able to raise the SDA pin as fast as expected by the EEPROM which relied on the pull-up to ensure the high level. 2.5 Software Solution There is a software solution for the above problem. Each time the microcontroller has to proceed a Low to High transition on a pin, the pin is driven High thanks to the strong transistor of only few tenths of Ohms during two clock periods. Moreover, the microcontroller controls the clock of the protocol. Therefore, just before setting the clock in order to read the data, it can make a High to Low transition (because the port is constantly configured as a High level in bidirectional mode) followed by the Low to high transition which allows the strong transistor for a while. In case the EEPROM would like to transmit a low level, it has no effect, and in case the EEPROM would like to transmit an high level, it considerably helps the rising time. This software solution allows to use the EEPROM at its maximum frequency value. 4 AT8xEB5114 Application Note
5 AT8xEB5114 Application Note 3. EEPROM Brown Out and Microcontroller Power Fail Detect 3.1 AT8xEB5114 Power Fail Detect (PFD) Threshold Levels The AT8xEB5114 is a typical 3.3V microcontroller. It provides Power On Reset and Power Fail Detect threshold levels defined as in Table 3-1. Table 3-1. AT8xEB5114 PFD levels Symbol Parameter Min Typ Max Unit VPFDP Power fail high level threshold V VPFDM Power fail low level threshold (default) V Power fail hysteresis VPFDP - VPFDM mv This means that the microcontroller is under reset with a Vcc voltage value from 0 up to 2.7V. 3.2 AT24C02 Brown-Out Threshold Level The EEPROM typical Power fail detect value is about 1.2V. 3.3 Potential Problem Due to the difference of PFD level between the EEPROM and the Microcontroller, one part can be under reset while the other one is still running. As the PFD level of the EEPROM is lower than the AT8xEB5114, it appears necessary that the microcontroller resets the EEPROM each time it has itself been reset. 3.4 Resetting the EEPROM Usually, the TWI protocol is reset when a start condition is applied on the TWI pins. A start sequence consists of a falling edge on the SDA line while the SCL line is high. To generate a start condition, it is necessary to set the SDA line to 1. This can be done by the weak pull-up of the port while the microcontroller is under reset. But, due to the high pull-up value of the AT8xEB5114 port, it can take a long time before having this condition satisfied, and in case the EEPROM is outputting a low level, it is absolutely impossible to have... even with the strong transistor which would only produce a a spike on the SDA line. In order to reset the EEPROM, the best solution is to proceed as follows: Make the clock toggles as long as there is not a high Level on the SDA pin while the SCL pin is high. As soon as this condition is satisfied (SDA High while SCL is also High), make a START by driving low the SDA pin while the SCL pin is still high. After this first start, which has reset the TWI line you can create a STOP (by making a transition from low a High level on the SDA pin while the SCL is High), then you are certain that your protocol has been properly reset, and that no untimely data can be transmitted to the EEPROM while no other START has been processed. 5
6 AT8xEB5114 Application Note 3.5 C-code 3.6 Examples void TWI_Init_EEP(void) { // Init ports being sure there is no operation SDA_INT = 0; SCL_INT = 0; SDA_INT = 1; SCL_INT = 1; while (SDA_INT == 0){ // Check SDA is high while SCL is also high SCL_INT = 0; SDA_INT = 0; // Try to force SDA to High level... SDA_INT = 1; //..thanks to the fast software pull-up SCL_INT = 1; } // Generate a START to reset the protocol SDA_INT = 0; SCL_INT = 0; // Generate a STOP to be sure no data can be untimely transmitted SCL_INT = 1; SDA_INT = 1; // The EEPROM protocol is now reset and waits for the next instruction } The two following diagrams illustrate what happens when the microcontroller is reset while the EEPROM is still correctly operating. Figure 3-1. illustrates an example where the AT8xEB5114 has requested a read data, and the data contains several 0. Figure 3-1. Microcontroller reset while the EEPROM is sending 0 RST P3.6 = SDA Spikes generated by the strong pull-up activation Standard bidirectional micrcontroller pull-up effect P3.7 = SCL EEPROM READING SEQUENCE RESET START STOP EEPROM READY 6
7 AT8xEB5114 Application Note The small spikes seen on the SDA pin correspond to the software pull-up which tries to rise the SDA pin. The special rising edge on the SCL pin during the AT8xEB5114 is reset is due the standard bidirectional port pull-up resistor. Just after the reset, the microcontroller has to transfer two dummy 0 data bits before being able to reset the EEPROM protocol. Figure 3-2. illustrates an example of AT8xEB5114 reset while the EEPROM does not hold the SDA line to 0. Figure 3-2. Microcontroller reset while the EEPROM is not driving a 0 RST P3.6 = SDA P3.7 = SCL MICROCONTROLLER SENDING DATA RESET START STOP EEPROM READY There is no spike visible because in this case only the microcontroller is transmitting data to the EEPROM. The special rising edge of the SCL pin during the microcontroller is reset is due the standard bidirectional port pull-up resistor. 3.7 Remarks 4. References The protocol mentioned allows to ensure a proper reset of the TWI protocol. Nevertheless, it is not exactly the same as if the EEPROM has been reset by a power lost. In case of loss of power, the internal pointer of the EEPROM is reset. In case of protocol reset, the internal pointer is not reset. If the application firmware starts with a sequential read, take care to reset the pointer thanks to a dummy write. AT8xC5114 Datasheet 24C02 Serial EEPROM Datasheet. 7
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