CMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago

Transcription

1 CMSC Computer Architecture Lecture 12: Virtual Memory Prof. Yajig Li Uiversity of Chicago

2 A System with Physical Memory Oly Examples: most Cray machies early PCs Memory early all embedded systems Physical Addresses 0: 1: CPU CPU s load or store addresses used directly to access memory N-1: 2

3 Difficulties of Direct Physical Addressig Programmer eeds to maage physical memory space Icoveiet & hard, especially with multiple processes Difficult to support code ad data relocatio Processes come ad go; fragmetatio issues How to provide protectio & isolatio? How to support data/code sharig across processes? Also, ISA ca have a address space greater tha the physical memory size E.g., a 64-bit address space with byte addressability What if you do ot have eough physical memory? 3

4 Abstractio: Virtual vs. Physical Memory Programmer sees virtual memory Ca assume the memory is private ad very large Reality: Physical memory size is much smaller tha what the programmer assumes ad ca be shared The system (system software + hardware, cooperatively) maps virtual memory addresses to physical memory The system automatically maages the physical memory space trasparetly to the programmer 4

5 Virtual Memory: Basic Mechaism Idea: Idirectio (i addressig) Address geerated by each istructio i a program is a virtual address i.e., it is ot the physical address used to address mai memory A address traslatio mechaism maps virtual address to a physical address The hardware coverts virtual addresses ito physical addresses via a OS-maaged lookup table (page table) Reuires Hardware + Software support! 5

6 Virtual Pages, Physical Frames Virtual address space divided ito pages Physical address space divided ito frames A virtual page is mapped to A physical frame, if the page is i physical memory A locatio i disk, otherwise If a accessed virtual page is ot i memory, but o disk Geerates page fault Virtual memory system brigs the page ito a physical frame ad adjusts the mappig à called demad pagig Page table: mappig of virtual pages to physical frames 6

7 Page Size What is the graularity of maagemet of physical memory? Specified by the ISA Today: 4KB, 8KB, 4MB, 2GB, Small ad large pages mixed together Large vs. small pages: may tradeoffs Size of the Page Table Number of page faults Trasfer overhead from disk to memory Iteral fragmetatio 7

8 A System with Virtual Memory Memory Virtual Addresses Page Table 0: 1: Physical Addresses 0: 1: CPU P-1: N-1: Disk Physical memory is a cache for pages stored o disk I fact, it is a fully associative cache i moder systems (a virtual page ca be mapped to ay physical frame) 8

9 Beefits of Virtual Memory Automatic maagemet Programmer does ot eed to kow the physical size of memory or maage it à A small physical memory ca appear as a huge oe to the programmer à Life is easier for the programmer Each process has its ow mappig from virtual à physical addresses, which eables Code ad data to be located aywhere i physical memory (efficiet use of physical memory) Isolatio/separatio of code ad data of differet processes i physical processes (protectio ad isolatio) Code ad data sharig betwee multiple processes (sharig) 9

10 Page Tables ad Address Traslatio

11 Virtual to Physical Address Traslatio Parameters P = 2 p = page size (bytes) N = 2 = Virtual-address limit M = 2 m = Physical-address limit 1 p p 1 0 virtual page umber, VPN page offset virtual address address traslatio m 1 p p 1 0 physical frame umber, PFN page offset physical address Page offset bits do t chage as a result of traslatio 11

12 Address Traslatio Usig Page Table Page Table cotais a etry for each virtual page Called Page Table Etry (PTE) What is i a PTE? A valid bit à to idicate validity/presece i physical memory PFN for the correspodig VPN à to support traslatio Cotrol bits to support replacemet Dirty bit idicate if we eed to write back Protectio bits to eable access cotrol ad protectio 12

13 Page Table is Per Process Each process has its ow virtual address space Illusio of full address space for each program Simplifies memory allocatio ad sharig Which table to use is idicated by the page table base register (PTBR) Virtual Address Space for Process 1: Virtual Address Space for Process 2: 0 N-1 0 VP 1 VP 2... VP 1 VP 2... Address Traslatio N-1 M-1 0 PP 2 PP 7 PP 10 Physical Address Space (DRAM) (e.g., read/oly library code) 13

14 Page Table Access Page Table Base Register (PTBR, CR3 i x86) Specifies the address of the page table Must cotai a physical address! PTBR is part of a process s cotext Just like PC, status registers, geeral purpose registers Needs to be loaded whe the process is cotext-switched i 14

15 Address Traslatio Illustrated Separate (set of) page table(s) per process VPN is used to idex ito page table (poits to a page table etry) Page Table Etry (PTE) provides iformatio about page page table base register (per process) virtual address 1 p p 1 0 virtual page umber (VPN) page offset valid physical frame umber (PFN) VPN acts as table idex if valid=0 the page ot i memory (page fault) m 1 p p 1 physical frame umber (PFN) physical address page offset 0 15

16 Page Table Eables Memory Protectio à Virtual memory system serves two fuctios Address traslatio (for illusio of large physical memory) Access cotrol (protectio) Not every process is allowed to access every page E.g., OS code ad data structures should be accessible by system software oly, i.e., reuire supervisor level privilege to access Idea: Store access cotrol iformatio o a page basis i the process s page table Eforce access cotrol at the same time as traslatio 16

17 Access Cotrol Type of access Read, write, execute Privilege level Defied by ISA, e.g., supervisor vs. user PTE cotais protectio bits which specify which accesses ca be made to this page at what privilege level Check bits o each access If violated, geerate exceptio (Access Protectio exceptio) What type of access is reuested? Privilege level of the ruig process Protectio bits i PTE Access Cotrol Logic Access allowed? 17

18 Memory Access Cotrol Bits i Page Tables Page Tables Memory Process i: VP 0: VP 1: Read? Write? Yes Yes No Yes Physical Addr PP 6 PP 4 PP 0 PP 2 VP 2: No No XXXXXXX PP 4 PP 6 Process j: VP 0: VP 1: VP 2: Read? Write? Yes Yes No Yes No No Physical Addr PP 6 PP 9 XXXXXXX PP 8 PP 10 PP 12 18

19 Virtual Memory Maagemet Mechaism

20 Both HW ad SW Support Reuired Page tables are located i memory, maaged by OS Hardware utilizes the iformatio i page table to perform fast address traslatio The hardware compoet is called the MMU (memory maagemet uit) 20

21 System Software (OS) Jobs for VM Keepig track of which physical frames are free Populate page table by allocatig free physical frames to virtual pages (o demad) Implemet page replacemet policy Whe o physical frame is free, what should be swapped out? Chage page tables o cotext switch To use the ruig thread s page table Hadle page faults Implemet other VM tricks Sharig pages betwee processes (e.g., shared libraries) Copy-o-write ad other optimizatios 21

22 Hardware Jobs for VM Address Traslatio (Page Hit) 22

23 HW ad SW: Page Fault Hadlig Note: page-fault hader routie is implemeted by the OS 23

24 I/O Operatio i Page Fault Hadler (1) Processor sigals cotroller Read block of legth P startig at disk address X ad store startig at memory address Y Processor Reg (1) Iitiate Block Read (3) Read Doe (2) Read occurs Direct Memory Access (DMA) by I/O cotroller CPU are free to ru other programs (3) I/O Cotroller sigals completio Iterrupt processor OS resumes suspeded process Cache Memory-I/O bus Memory (2) DMA Trasfer I/O cotroller Disk Disk 24

25 Page Fault ( A Miss i Physical Memory ) Resolved Before fault Memory After fault Memory CPU Virtual Addresses Page Table Physical Addresses CPU Virtual Addresses Page Table Physical Addresses Disk Disk

26 Virtual Memory System Desig Cosideratios

27 Three Major Issues I. How large is the page table ad how do we store ad access it? II. How ca we speed up traslatio & access cotrol check? III. Virtual memory ad cache iteractio 27

28 Page Table Size 64-bit VPN PO 52-bit 12-bit page table 28-bit cocat 40-bit PA 64-bit VA, 40-bit PA, 4KB pages à how large is the page table? 2 52 etries x ~4 bytes» 16PetaBytes Ad that is for just oe process! Page table too large to fit i physical memory!! 28

29 Solutio: Multi-Level Page Tables Example from x86 architecture The process may ot be usig the etire VM space! Oly the first-level page table has to be i physical memory Remaiig levels are i virtual memory (but get cached i physical memory whe accessed) 29

30 Multi-Level Page Protectio X86 Example 30

31 Virtual Memory Issue II How fast do we eed the address traslatio to be? How ca we make it fast? Idea: Use a hardware structure that caches PTEs à Traslatio lookaside buffer (TLB) 31

32 Speedig up Traslatio with a TLB Essetially a small cache of recet address traslatios Avoids goig to the page table o every referece What happes o cotext switch? Idex = lower bits of VPN Tag = uused bits of VPN (+ process ID sometimes) Data = a page-table etry Status = valid, dirty The usual cache desig choices (associativity, replacemet policy, multi-level, etc.) all apply to TLB. 32

33 TLB Examples Typical umbers: PTEs, cycle for hit, cycles for miss, 0.01% 1% miss rate

34 TLB Misses The TLB is small; it caot hold all PTEs Some traslatios will ievitably miss i the TLB TLB miss idicates Page preset, but PTE ot i TLB Page ot preset O TLB miss, access memory to fid the appropriate PTE Called walkig the page directory/table Large performace pealty Who hadles TLB misses? Hardware or software?

35 Hadlig TLB Misses Approach #1. Hardware-Maaged (e.g., x86) The hardware does the page walk The hardware fetches the PTE ad iserts it ito the TLB If the TLB is full, the etry replaces aother etry based o replacemet policy Doe trasparetly to system software Approach #2. Software-Maaged (e.g., MIPS) The hardware raises a exceptio The operatig system does the page walk The operatig system fetches the PTE The operatig system iserts/evicts etries i the TLB

36 Tradeoffs Hardware-Maaged TLB Pro: No exceptio o TLB miss. Istructio simply waits Pro: Idepedet istructios may cotiue Pro: No extra istructios/data brought ito caches Co: Page directory/table orgaizatio is etched ito the system: OS has little flexibility Software-Maaged TLB Pro: The OS ca defie page table/directory orgaizatio Pro: More sophisticated TLB replacemet policies are possible Co: Need to geerate a exceptio à performace overhead due to pipelie flush, exceptio hadler executio, extra istructios brought to caches