ECE331: Hardware Organization and Design

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1 ECE331: Hardware Organization and Design Lecture 31: Computer Input/Output Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

2 Overview for today Input and output are fundamental for computer operation Typically much slower than computation Two types of transfer Polling processor constantly checks for data Interrupts processor is interrupted from activity Need to understand the requirements of data transfer Tied to computer organization (bus, interfaces, etc) I/O bandwidth is important (how fast, how much) Most interfaces today are standardized (USB, monitor, Ethernet) ECE331: Computer I/O 2

Bus Main Memory I/O Controller I/O Controller

3 Anatomy: 5 components of any Computer Processor Control Memory Devices Input Keyboard, Mouse Processor Datapath Output Disk Display, Printer Cache interrupts Memory - I/O Bus Main Memory I/O Controller I/O Controller I/O Controller Disk Disk Graphics Network ECE331: Computer I/O 3

4 Handling IO Users like to connect devices to their computers Keyboard, mouse, printer External devices may require attention from processor at unpredictable times CPU doesn t know when you re about to hit a key IO devices can be very fast or very slow Need to have a flexible way to control all devices ECE331: Computer I/O 4

5 I/O Device Examples and Speeds I/O Speed: bytes transferred per second (from mouse to display: million-to-1) Device Behavior Partner Data Rate (Mbit/sec) Keyboard Input Human Mouse Input Human Laser Printer Output Human Magnetic Disk Storage Machine Modem I or O Machine Network-LAN I or O Machine Graphics Display OutputHuman ECE331: Computer I/O 5

6 Hardware Solution (875 Chipset) Pentium 4 processor Main memory DIMMs DDR 400 (3.2 G B/sec) DDR 400 (3.2 G B/sec) Memory controller hub (north bridge) 82875P System bus (800 MHz, 604 GB/sec) AGP 8X (2.1 G B/sec) CSA (0.266 GB/sec) Graphics output 1 Gbit Ethernet Disk Serial ATA (150 MB/sec) (266 M B/sec) Parallel ATA (100 MB/sec) CD/DVD Disk Serial ATA (150 MB/sec) AC/97 (1 MB/sec) Stereo (surroundsound) USB 2.0 (60 MB/sec) I/O controller hub (south bridge) 82801EB Parallel ATA (100 M B/sec) (20 MB/sec) Tape 10/100 M bit Ethernet... PCI bus (132 M B/sec) ECE331: Computer I/O 6

7 Instruction Set Architecture for I/O Some machines have special input and output instructions Alternative model (used by MIPS): Input: ~ reads a sequence of bytes Output: ~ writes a sequence of bytes Memory also a sequence of bytes, so use loads for input, stores for output Called Memory Mapped Input/Output A portion of the address space dedicated to communication paths to Input or Output devices (no memory there) These addresses are not regular memory, instead, they correspond to registers in I/O devices ECE331: Computer I/O 7 address 0 0xFFFF0000 0xFFFFFFFF cntrl reg. data reg.

8 Memory Mapped IO Make control registers and I/O device data registers appear to be part of the system s main memory Reads and writes to the mapped region of the memory are translated by memory controller hardware into accesses of hardware device Makes it easy to support variable numbers/types of devices just map them onto different regions of memory Accessing I/O device registers and memory can be done by accessing data structures via the device pointers Most device drivers are now written in C/C++. Memory mapped I/O makes this feasible without any changes to the way a CPU is programmed ECE331: Computer I/O 8

9 Processor-I/O Speed Mismatch 1 GHz microprocessor can execute 1000 million load or store instructions per second, or 4 million KB/s data rate I/O devices from 0.01 KB/s to 30,000 KB/s Input: device may not be ready to send data as fast as the processor loads it Also, might be waiting for human to act Output: device may not be ready to accept data as fast as processor stores it What to do? ECE331: Computer I/O 9

10 Processor Checks Status before Acting: Polling Path to device generally has 2 registers: 1 register says it s OK to read/write (I/O ready), often called Control Register 1 register that contains data, often called Data Register Processor reads from Control Register in loop, waiting for device to set Ready bit in Control reg to say its OK (0 1) Processor then loads from (input) or writes to (output) data register Load from device/store into Data Register resets Ready bit (1 0) of Control Register ECE331: Computer I/O 10

11 Cost of Polling? Assume: a 1 GHz processor takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling Mouse: polled 30 times/sec - not to miss user movement Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. No transfer can be missed Mouse Polling Clocks/sec = 30 * 400 = clocks/sec % Processor for polling = 12*10 3 /1*10 9 = % Polling mouse has little impact on processor Times Polling Disk/sec = 8 MB/s /16B = 500K polls/sec Disk Polling Clocks/sec = 500K * 400 = 200,000,000 clocks/sec % Processor for polling: 2*10 8 /1*10 9 = 20% Unacceptable ECE331: Computer I/O 11

12 What is the alternative to polling? Interrupt Wasteful to have processor spend most of its time spinwaiting for I/O to be ready Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready Solution: use exception mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer Polling is like picking up the phone every few seconds to see if you have a call. Interrupt is like letting the phone ring ECE331: Computer I/O 12

13 I/O Interrupt Controller sends interrupt to the processor along with additional information which device nature of interrupt: error, no paper, no ink, Processor halts execution of current program Saves State Processor looks up which handler to start from the interrupt information When interrupt is handled, returns to program state and resumes ECE331: Computer I/O 13

14 Interrupt Driven Data Transfer Memory (1) I/O interrupt (2) save PC add sub and or } user program (3) interrupt service addr (4) (5) } read store... jr interrupt service routine ECE331: Computer I/O 14

15 Benefit of Interrupt-Driven I/O 500 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time If interrupt rate = polling rate Disk Interrupts/sec = 8 MB/s /16B = 500K interrupts/sec Disk Polling Clocks/sec = 500K * 500 = 250,000,000 clocks/sec % Processor used during transfers: 250*10 6 /1*10 9 = 25% If disk active 5% 5% * 25% 1.25% busy ECE331: Computer I/O 15

16 Interrupts Multiple devices Aggregates interrupts Prioritization (network, keyboard,..) Device 1 Processor Advanced Priority Interrupt Controller (APIC) Device 2 Device i Device n ECE331: Computer I/O 16

17 Interrupt vs. Polling Which is better: Interrupts or Polling? Interrupts are better if the processor has something else to do and the time-to-response is not critical Polling is better if the processor has to respond to an event ASAP Polling is also used when data is expected at regular intervals such as in a modem Modem typically connects to a com port The com port can be polled at expected intervals ECE331: Computer I/O 17

18 Direct Memory Access (DMA) How to transfer large amounts of data between a Device and Memory? Waste of CPU cycles if done through CPU Let the device controller transfer data directly to and from memory => DMA The CPU sets up the DMA transfer by supplying the type of operation, memory address and number of bytes to be transferred The DMA controller contacts the bus directly, provides memory address and transfers the data Once the DMA transfer is complete, the controller interrupts the CPU to inform completion Cycle Stealing Bus gives priority to DMA controller thus stealing cycles from the CPU ECE331: Computer I/O 18

19 OS control of I/O operations Low-level control of I/O device is complex because it requires managing a set of concurrent events and because requirements for correct device control are often very detailed I/O systems often use interrupts to communicate information about I/O operations and these can occur at a random time The I/O system is shared by multiple programs using the processor ECE331: Computer I/O 19

ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design Lecture 29: Computer Input/Output Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Announcements ECE Honors Exhibition Wednesday, April