LPC81x, LPC82x, LPC83x Errata Sheet and Datasheet Update for Vdd.1 Errata

Transcription

1 4/12/2018 epcn Print: Customer Information Notification I Customer Information Notification I Issue Date: Effective Date: Dear Product Data, 13-Apr Apr-2018 Here's your personalized quality information concerning products Mouser Electronics purchased from NXP. For detailed information we invite you to view this notification online Management Summary New revisions of errata sheets and datasheets are available for the LPC81x, LPC82x and LPC83x. Change Category Wafer Fab Process Wafer Fab Materials Wafer Fab Location Assembly Process Assembly Materials Assembly Location Product Marking Test Location Design Mechanical Specification Test Process Errata Test Electrical spec./test Packing/Shipping/Labeling Equipment coverage LPC81x, LPC82x, LPC83x Errata Sheet and Datasheet Update for Vdd.1 Errata Information Notification New revisions of errata sheets and datasheets are available for the LPC81x, LPC82x and LPC83x products. The errata sheets have been updated with the Vdd.1 errata. See errata sheets for details. The datasheets have an added reference to the errata sheet in the Power-up ramp conditions Table, note [2]. The new document revisions are as follows: ES_LPC81xM Errata Sheet Rev 3.2, ES_LPC82x Errata Sheet Rev 1.3, ES_LPC83x Errata Sheet Rev 1.1, LPC81xM Product Data Sheet Rev 4.6, LPC82x Product Data Sheet Rev 1.3, LPC83x Product Data Sheet Rev 1.2, Why do we issue this Information Notification To keep customers informed of the latest device errata. Identification of Affected Products Top side marking See errata sheets for affected product revisions. Impact There is no change to product form, fit, function, or reliability. Data Sheet Revision 1/2

2 4/12/2018 epcn Print: Customer Information Notification I A new datasheet will be issued Additional information Additional documents: view online Contact and Support For all inquiries regarding the epcn tool application or access issues, please contact NXP "Global Quality Support Team". For all Quality Notification content inquiries, please contact your local NXP Sales Support team. For specific questions on this notice or the products affected please contact our specialist directly: Name Tim Camenzind Position Senior Quality Engineer address tim.camenzind@nxp.com At NXP Semiconductors we are constantly striving to improve our product and processes to ensure they reach the highest possible Quality Standards. Customer Focus, Passion to Win. NXP Quality Management Team. About NXP Semiconductors NXP Semiconductors N.V. (NASDAQ: NXPI) provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise. These innovations are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. NXP Semiconductors High Tech Campus, 5656 AG Eindhoven, The Netherlands NXP Semiconductors. All rights reserved. 2/2

3 ES_LPC81xM Errata sheet LPC81xM Rev April 2018 Errata sheet Document information Info Keywords Abstract Content LPC810M021FN8; LPC811M001JDH16; LPC812M101JDH16; LPC812M101JD20; LPC812M101JDH20, LPC812M101JTB16, LPC81xM errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

4 ES_LPC81xM Errata sheet LPC81xM Revision history Rev Date Description Added VDD Added details on how to determine revision identifier for TSSOP Added CMP Added revision 4C. Updated SYSOSC.1. Added CMP Initial version Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

5 ES_LPC81xM Errata sheet LPC81xM 1. Product identification 2. Errata overview The LPC81xM devices typically have the following top-side marking: LPC81x xxxxx xxxxxxxx xxywwxr[x] The last two letters in the last line (field xr ) identify the boot code version and device revision. Table 1. Device revision table Revision identifier (xr) Revision description 1A Initial device revision with boot code version A Second device revision with boot code version C Third device revision with boot code version 13.4 Field Y states the year the device was manufactured. Field WW states the week the device was manufactured during that year. Remark: On the TSSOP16 package, the last line includes only the date code xxyww. In order to determine the revision identifier, use the ISP command Read Boot code version (for more details, refer to Chapter 21 of the LPC81x user manual (UM10601)). Table 2. Functional problems table Functional problems Short description Revision identifier Detailed description CMP.1 On the LPC810M021FN8 revision A device, the comparator is not functional. 1A, 2A Section 3.1 DPD.1 FLASHCFG.1 I2C.1 PD.1 SYSOSC.1 VDD.1 In Deep Power-down mode, the current consumption can be higher than anticipated The flash access time must be set to 2 system clocks before performing In-System/In-Application programming calls, and power profile API calls. In I2C slave mode, the SLVPENDING bit does not clear when the slave function is disabled. Reset wake-up sources cannot be used to wake up the device from power-down mode. When using an external crystal oscillator, the V DD supply voltage must be 1.9 V or above for device revision 4C, and 2.3 V or above for device revisions 1A and 2A. The minimum wait time of the power supply ramp must be minimum 2 ms. 1A, 2A Section 3.2 1A, 2A Section 3.3 1A, 2A Section 3.4 1A, 2A Section 3.5 1A, 2A, 4C Section 3.6 1A, 2A, 4C Section 3.7 ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

6 ES_LPC81xM Errata sheet LPC81xM Table 3. AC/DC deviations table AC/DC deviations Short description Detailed description n/a n/a n/a Table 4. Errata notes Note Short description Detailed description n/a n/a n/a ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

7 ES_LPC81xM Errata sheet LPC81xM 3. Functional problems detail 3.1 CMP.1 Introduction: The LPC810M021FN8 part features a comparator which can be used to compare voltage levels on external pins and internal voltages. Problem: On the LPC810M021FN8 revision A only, the comparator is not functional. Work-around: None. This errata is fixed on the LPC810M021FN8 revision C. 3.2 DPD.1 Introduction: The LPC800 supports four low-power modes: sleep, deep-sleep, power-down, and deep power-down modes. The LPC800 datasheet specifies 220 na typical deep power-down current (wake-up timer disabled) at 25 C, and 1 µa typical deep power-down current (wake-up timer enabled) at 25 C. Problem: The deep power-down current can be approximately 30 µa higher than the specified typical values in the datasheet. Work-around: None. ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

8 ES_LPC81xM Errata sheet LPC81xM 3.3 FLASHCFG.1 Introduction: On the LPC800, access to the flash memory can be configured with various access times by writing to the FLASHCFG register. The user can write a value of 0x0 (1 system clock flash access time) or a value of 0x1 (2 system clocks flash access time) in the FLASHCFG register. The default value is set to 0x1. The LPC800's ROM supports flash In-System Programming (ISP)/In-Application Programming (IAP) calls, and power profile API calls. Problem: If the user application is using 1 system clock flash access time (FLASHCFG register set to 0x0), the In-System/In-Application Programming calls and power profile API calls will not always operate correctly with this setting. Work-around: Before performing the In-System/In-Application programming calls, and/or power profile API calls, the user must ensure that the FLASHCFG register is set to 2 system clocks flash access time. The user can use 1 system clock flash access time when these API calls are not performed. ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

9 ES_LPC81xM Errata sheet LPC81xM 3.4 I2C.1 Introduction: The I2C peripheral on the LPC800 supports independent Master, Slave, and Monitor functions. In the I2C slave mode, the slave function internally resets when the slave function is disabled. This is controlled using the SLVEN bit in the I2C Configuration register (CFG). The SLVPENDING bit in the I2C status register (STAT) indicates whether the slave function is waiting to continue communication and needs software service. If the SLVPENDING bit is read as '0', the slave function does not need service, and if read as '1', the slave function needs service and an interrupt can be generated. The SLVPENDING bit in the I2C status register (STAT) automatically clears when a '1' is written to the SLVCONTINUE bit in the Slave Control register (SLVCTL) or when the slave function is disabled via the SLVEN bit in the I2C Configuration register (CFG). Problem: When the slave function is disabled, the SLVPENDING bit in the I2C status register (STAT) does not clear, and as a result, an interrupt will be generated when the I2C slave function is re-enabled. Work-around: After disabling the slave function, the SLVPENDING bit in the I2C status register (STAT) should be cleared by writing a '1' to the SLVCONTINUE bit in the Slave Control register (SLVCTL). ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

10 ES_LPC81xM Errata sheet LPC81xM 3.5 PD.1 Introduction: The LPC800 supports four low-power modes: sleep, deep-sleep, power-down, and deep power-down modes. In power-down mode, the LPC800 can wake up from the following wake-up sources: 1. Interrupts from USARTs, SPI, I2C 2. Pin interrupts 3. Brown-Out Detect (BOD) interrupt and reset 4. Windowed Watchdog Timer (WWDT) interrupt and reset 5. External Reset Pin 6. Self Wake-Up Timer (WKT) Problem: The BOD reset, WWDT reset, and the external reset pin wake-up sources cannot be used to wake up the device from power-down mode. Work-around: Use the other wake-sources (mentioned above) to wake up the device from power-down mode. ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

11 ES_LPC81xM Errata sheet LPC81xM 3.6 SYSOSC.1 Introduction: On the LPC800, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC800 has various clock sources such as the internal oscillator (IRC), system oscillator, CLKIN, and watchdog oscillator. An external crystal oscillator can be connected between the XTALIN and XTALOUT pins to use the system oscillator as a clock source. The system oscillator can also be bypassed by setting the BYPASS bit in the SYSOSCCTRL register, and an external clock source can be fed directly to the XTALIN pin. Problem: An external crystal oscillator connected to the system oscillator does not function when the V DD power supply is below 1.9 V for device revision 4C, and below 2.3 V for device revisions 1A and 2A. Work-around: The V DD supply voltage must be 1.9 V or above for device revision 4C, and 2.3 V or above for device revisions 1A and 2A when connecting an external crystal oscillator to the system oscillator. If the V DD supply voltage is below 1.9 V for device revision 4C, and below 2.3 V for device revisions 1A and 2A, an external clock source can be fed to the XTALIN by bypassing the system oscillator or the other clock sources mentioned above can be used. 3.7 VDD.1 Introduction: On the LPC81x, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC81x datasheet specifies a power-up ramp condition for the user application. Before ramping up, the minimum wait time (t wait ) of the power supply on the V DD pin (200 mv or below) is 12 s. Problem: The device might not always start-up if the minimum wait time (t wait ) is 12 s. The required minimum time (t wait ) specification is 2 ms. Work-around: None. ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

12 ES_LPC81xM Errata sheet LPC81xM 4. AC/DC deviations detail 5. Errata notes n/a 5.1 Note.1 n/a ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

13 ES_LPC81xM Errata sheet LPC81xM 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC81XM All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 12

14 ES_LPC81xM Errata sheet LPC81xM 7. Contents 1 Product identification Errata overview Functional problems detail CMP Introduction: Problem: Work-around: DPD Introduction: Problem: Work-around: FLASHCFG Introduction: Problem: Work-around: I2C Introduction: Problem: Work-around: PD Introduction: Problem: Work-around: SYSOSC Introduction: Problem: Work-around: VDD Introduction: Problem: Work-around: AC/DC deviations detail Errata notes Note Legal information Definitions Disclaimers Trademarks Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 3 April 2018 Document identifier: ES_LPC81XM

15 ES_LPC82x Errata sheet LPC82x Rev April 2018 Errata sheet Document information Info Keywords Abstract Content LPC824M201JHI33; LPC822M101JHI33; LPC824M201JDH20; LPC822M101JDH20; LPC82x errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

16 ES_LPC82x Errata sheet LPC82xM Revision history Rev Date Description Added VDD Added CMP Added text to the work-around of DPD.2 for clarity in Section 3.1: Deep power-down mode operates correctly for the entire temperature range (-40 C to 105 C) if the VDD supply is between 1.8 V and 3.35 V Initial version Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

17 ES_LPC82x Errata sheet LPC82xM 1. Product identification The LPC82x devices typically have the following top-side marking: The LPC82x devices typically have the following top-side marking for HVQFN33 packages: 82xJ xxxx xxxx yywwxr The last two letters in the last line (field xr ) identify the boot code version and device revision. Table 1. Device revision table Revision identifier (xr) 1A Revision description Initial device revision 2. Errata overview Field yy states the year the device was manufactured. Field ww states the week the device was manufactured during that year. Table 2. Functional problems table Functional problems Short description Revision identifier Detailed description DPD.2 Deep power-down mode is not functional outside certain voltage and temperature ranges. 1A Section 3.1 SYSOSC.2 UART.1 CMP.1 VDD.1 When using an external crystal oscillator, the V DD supply voltage must be 1.9 V or above. The UART controller sets the Idle status bits for receive and transmit before the transmission of the stop bit is complete. PIO0_21 cannot be used as GPIO output port when enabling ACMP_I4 function on PIO0_23 pin port pin. The minimum wait time of the power supply ramp must be minimum 2 ms. 1A Section 3.2 1A Section 3.3 1A Section 3.4 1A Section 3.5 Table 3. AC/DC deviations table AC/DC deviations Short description Detailed description n/a n/a n/a Table 4. Errata notes Note Short description Detailed description n/a n/a n/a ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

18 ES_LPC82x Errata sheet LPC82xM 3. Functional problems detail 3.1 DPD.2 Introduction: The LPC82x has a supply voltage (V DD ) from 1.8 V to 3.6 V and can operate from -40 C to 105 C. The LPC82x supports four reduced power modes (sleep, deep-sleep, power-down, and deep power-down mode). Deep power-down mode allows for maximal power savings where the entire system is shut down except for the general purpose registers in the PMU and the self wake-up timer. Only the general purpose registers in the PMU maintain their internal states in deep power-down mode. Problem: At temperatures 25 C, the deep power-down mode is not functional if the V DD supply voltage is > 3.4 V. At temperatures > 25 C, the deep power-down mode is not functional if the V DD supply voltage is > 3.35 V. Work-around: Deep power-down mode operates correctly for the entire temperature range (-40 C to 105 C) if the VDD supply is between 1.8 V and 3.35 V. For temperatures 25 C, ensure that the supply voltage is not > 3.4 V (V DD = 1.8 V to 3.4 V) when using deep power-down mode. For temperatures > 25 C, ensure that the supply voltage is not > 3.35 V (V DD = 1.8 V to 3.35 V) when using deep power-down mode. ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

19 ES_LPC82x Errata sheet LPC82xM 3.2 SYSOSC.1 Introduction: On the LPC82xM, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC82xM has various clock sources such as the internal oscillator (IRC), system oscillator, CLKIN, and watchdog oscillator. An external crystal oscillator can be connected between the XTALIN and XTALOUT pins to use the system oscillator as a clock source. The system oscillator can also be bypassed by setting the BYPASS bit in the SYSOSCCTRL register, and an external clock source can be fed directly to the XTALIN pin. Problem: An external crystal oscillator connected to the system oscillator does not function when the V DD power supply is below 1.9 V. Work-around: The V DD supply voltage must be 1.9 V or above when connecting an external crystal oscillator to the system oscillator. If the V DD supply voltage is below 1.9 V, an external clock source can be fed to the XTALIN by bypassing the system oscillator or the other clock sources mentioned above can be used. 3.3 UART.1 Introduction: In receive mode, the UART controller provides a status bit (the RXIDLE bit in the UART STAT register) to check whether the receiver is currently receiving data. If RXIDLE is set, the receiver indicates it is idle and does not receive data. In transmit mode, the UART controller provides two status bits (TXIDLE and TXDISSTAT bits in the UART STAT register) to indicate whether the transmitter is currently transmitting data. The TXIDLE bit is set by the controller after the last stop bit has been transmitted. The TXDISSTAT bit is set by the controller after the transmitter has sent the last stop bit and has become fully idle following a transmit disable executed by setting the TXDIS bit in the UART CTRL register. The status bits can be used to implement software flow control, but their setting does not affect normal UART operation. ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

20 ES_LPC82x Errata sheet LPC82xM Problem: The RXIDLE bit is incorrectly set for a fraction of the clock cycle between the reception of the last data bit and the reception of the start bit of the next word, that is while the stop bit is received. RXIDLE is cleared at the beginning of the start bit. data word 1 parity bit (optional) stop bit logic 1 start bit logic 0 data word 2 START D0 D1 D2 D3 D4 D5 D6 D7 PB STOP START D0 not correct: RXIDLE set Fig 1. Incorrect setting of RXIDLE during UART receive Both, TXIDLE and TXDISSTAT are set incorrectly between the last data bit and the stop bit while the transfer is still ongoing. start bit logic 0 data word parity bit (optional) stop bit logic 1 START D0 D1 D2 D3 D4 D5 D6 D7 PB STOP not correct: TXIDLE, TXDISSTAT set correct: TXIDLE, TXDISSTAT set Fig 2. Incorrect setting of TXIDLE and TXDISSTAT during UART transmit Work-around: When writing code that checks for the setting of any of the status bits RXIDLE, TXIDLE, TXDISSTAT, check the value of the status bit in the STAT register: If status bit = 1, add a delay of one UART bit time (if STOPLEN = 0, one stop bit) or two bit times (if STOPLEN = 1, two stop bits) and check the value of the status bit again: If status bit = 1, the receiver is idle. If status bit = 0, the receiver is receiving data. If the status bit = 0, the receiver is receiving data. ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

21 ES_LPC82x Errata sheet LPC82xM 3.4 CMP.1 Introduction: On the LPC82x, the analog comparator has four input pins (ACMP_I[4:1]). These are fixed-pin functions and are associated with one bit in the PINENABLE0 register that selects or deselects the comparator input function. Problem: When the ACMP_I4 function is enabled on port pin PIO0_23 pin, port pin PIO0_21 cannot be used as GPIO output port. Also, to use the ACMP_I4 function, the port pin PIO0_23 must not be configured as GPIO output. Work-around: No work-around. 3.5 VDD.1 Introduction: On the LPC82x, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC82x datasheet specifies a power-up ramp condition for the user application. Before ramping up, the minimum wait time (t wait ) of the power supply on the V DD pin (200 mv or below) is 12 s. Problem: The device might not always start-up if the minimum wait time (t wait ) is 12 s. The required minimum time (t wait ) specification is 2 ms. Work-around: None. ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

22 ES_LPC82x Errata sheet LPC82xM 4. AC/DC deviations detail 5. Errata notes n/a n/a ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

23 ES_LPC82x Errata sheet LPC82xM 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC82X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

24 ES_LPC82x Errata sheet LPC82xM 7. Contents 1 Product identification Errata overview Functional problems detail DPD SYSOSC UART CMP VDD AC/DC deviations detail Errata notes Legal information Definitions Disclaimers Trademarks Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 3 April 2018 Document identifier: ES_LPC82X

25 ES_LPC83x Errata sheet LPC83x Rev April 2018 Errata sheet Document information Info Keywords Abstract Content LPC834M101FHI33; LPC832M101FDH20; LPC83x errata This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table.

26 ES_LPC83x Errata sheet LPC83x Revision history Rev Date Description Added VDD Initial version Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

27 ES_LPC83x Errata sheet LPC83x 1. Product identification The LPC83x devices typically have the following top-side marking: The LPC83x devices typically have the following top-side marking for HVQFN33 packages: 83xF xxxx xxxx yywwxr The last two letters in the last line (field xr ) identify the boot code version and device revision. Table 1. Device revision table Revision identifier (xr) 1A Revision description Initial device revision 2. Errata overview Field yy states the year the device was manufactured. Field ww states the week the device was manufactured during that year. Table 2. Functional problems table Functional problems Short description Revision identifier Detailed description DPD.2 Deep power-down mode is not functional outside certain voltage and temperature ranges. 1A Section 3.1 SYSOSC.2 UART.1 VDD.1 When using an external crystal oscillator, the V DD supply voltage must be 1.9 V or above. The UART controller sets the Idle status bits for receive and transmit before the transmission of the stop bit is complete. The minimum wait time of the power supply ramp must be minimum 2 ms. 1A Section 3.2 1A Section 3.3 1A Section 3.4 Table 3. AC/DC deviations table AC/DC deviations Short description Detailed description n/a n/a n/a Table 4. Errata notes Note Short description Detailed description n/a n/a n/a ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

28 ES_LPC83x Errata sheet LPC83x 3. Functional problems detail 3.1 DPD.2 Introduction: The LPC83x has a supply voltage (V DD ) from 1.8 V to 3.6 V and can operate from -40 C to 85 C. The LPC83x supports four reduced power modes (sleep, deep-sleep, power-down, and deep power-down mode). Deep power-down mode allows for maximal power savings where the entire system is shut down except for the general purpose registers in the PMU and the self wake-up timer. Only the general purpose registers in the PMU maintain their internal states in deep power-down mode. Problem: At temperatures 25 C, the deep power-down mode is not functional if the V DD supply voltage is > 3.4 V. At temperatures > 25 C, the deep power-down mode is not functional if the V DD supply voltage is > 3.35 V. Work-around: Deep power-down mode operates correctly for the entire temperature range (-40 C to 85 C) if the VDD supply is between 1.8 V and 3.35 V. For temperatures 25 C, ensure that the supply voltage is not > 3.4 V (V DD = 1.8 V to 3.4 V) when using deep power-down mode. For temperatures > 25 C, ensure that the supply voltage is not > 3.35 V (V DD = 1.8 V to 3.35 V) when using deep power-down mode. ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

29 ES_LPC83x Errata sheet LPC83x 3.2 SYSOSC.1 Introduction: On the LPC83xM, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC83xM has various clock sources such as the internal oscillator (IRC), system oscillator, CLKIN, and watchdog oscillator. An external crystal oscillator can be connected between the XTALIN and XTALOUT pins to use the system oscillator as a clock source. The system oscillator can also be bypassed by setting the BYPASS bit in the SYSOSCCTRL register, and an external clock source can be fed directly to the XTALIN pin. Problem: An external crystal oscillator connected to the system oscillator does not function when the V DD power supply is below 1.9 V. Work-around: The V DD supply voltage must be 1.9 V or above when connecting an external crystal oscillator to the system oscillator. If the V DD supply voltage is below 1.9 V, an external clock source can be fed to the XTALIN by bypassing the system oscillator or the other clock sources mentioned above can be used. 3.3 UART.1 Introduction: In receive mode, the UART controller provides a status bit (the RXIDLE bit in the UART STAT register) to check whether the receiver is currently receiving data. If RXIDLE is set, the receiver indicates it is idle and does not receive data. In transmit mode, the UART controller provides two status bits (TXIDLE and TXDISSTAT bits in the UART STAT register) to indicate whether the transmitter is currently transmitting data. The TXIDLE bit is set by the controller after the last stop bit has been transmitted. The TXDISSTAT bit is set by the controller after the transmitter has sent the last stop bit and has become fully idle following a transmit disable executed by setting the TXDIS bit in the UART CTRL register. The status bits can be used to implement software flow control, but their setting does not affect normal UART operation. ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

30 ES_LPC83x Errata sheet LPC83x Problem: The RXIDLE bit is incorrectly set for a fraction of the clock cycle between the reception of the last data bit and the reception of the start bit of the next word, that is while the stop bit is received. RXIDLE is cleared at the beginning of the start bit. data word 1 parity bit (optional) stop bit logic 1 start bit logic 0 data word 2 START D0 D1 D2 D3 D4 D5 D6 D7 PB STOP START D0 not correct: RXIDLE set Fig 1. Incorrect setting of RXIDLE during UART receive Both, TXIDLE and TXDISSTAT are set incorrectly between the last data bit and the stop bit while the transfer is still ongoing. start bit logic 0 data word parity bit (optional) stop bit logic 1 START D0 D1 D2 D3 D4 D5 D6 D7 PB STOP not correct: TXIDLE, TXDISSTAT set correct: TXIDLE, TXDISSTAT set Fig 2. Incorrect setting of TXIDLE and TXDISSTAT during UART transmit Work-around: When writing code that checks for the setting of any of the status bits RXIDLE, TXIDLE, TXDISSTAT, check the value of the status bit in the STAT register: If status bit = 1, add a delay of one UART bit time (if STOPLEN = 0, one stop bit) or two bit times (if STOPLEN = 1, two stop bits) and check the value of the status bit again: If status bit = 1, the receiver is idle. If status bit = 0, the receiver is receiving data. If the status bit = 0, the receiver is receiving data. ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

31 ES_LPC83x Errata sheet LPC83x 3.4 VDD.1 Introduction: On the LPC83x, the V DD supply voltage range is from 1.8 V to 3.6 V. The LPC83x datasheet specifies a power-up ramp condition for the user application. Before ramping up, the minimum wait time (t wait ) of the power supply on the V DD pin (200 mv or below) is 12 s. Problem: The device might not always start-up if the minimum wait time (t wait ) is 12 s. The required minimum time (t wait ) specification is 2 ms. Work-around: None. ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

32 ES_LPC83x Errata sheet LPC83x 4. AC/DC deviations detail 5. Errata notes n/a n/a ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

33 ES_LPC83x Errata sheet LPC83x 6. Legal information 6.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ES_LPC83X All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Errata sheet Rev April of 10

34 ES_LPC83x Errata sheet LPC83x 7. Contents 1 Product identification Errata overview Functional problems detail DPD SYSOSC UART VDD AC/DC deviations detail Errata notes Legal information Definitions Disclaimers Trademarks Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 3 April 2018 Document identifier: ES_LPC83X

35 LPC81xM 32-bit ARM Cortex -M0+ microcontroller; up to 16 kb flash and 4 kb SRAM Rev April 2018 Product data sheet 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kb of flash memory and 4 kb of SRAM. The peripheral complement of the LPC81xM includes a CRC engine, one I 2 C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits System: ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. Serial Wire Debug (SWD) and JTAG boundary scan modes supported. Micro Trace Buffer (MTB) supported. Memory: Up to 16 kb on-chip flash programming memory with 64 Byte page write and erase. Up to 4 kb SRAM. ROM API support: Boot loader. USART drivers. I2C drivers. Power profiles. Flash In-Application Programming (IAP) and In-System Programming (ISP). Digital peripherals: High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter. High-current source output driver (20 ma) on four pins. High-current sink driver (20 ma) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function.