16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC)

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1 16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC) 16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC) Features High speed t AA = 10 ns/15 ns Embedded error-correcting code (ECC) for single-bit error correction Low active and standby current I CC = 90 ma typical I SB2 = 20 ma typical Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V 1.0-V data retention Automatic power-down when deselected Transistor-transistor logic (TTL) compatible inputs and outputs ERR pin to indicate 1-bit error detection and correction Available in Pb-free 119-ball plastic ball grid array (PBGA) package Functional Description CY7C1062G and are high-performance CMOS fast static RAM devices with embedded ECC. Both have three chip enables, giving easy memory expansion features. The device includes an error indication pin that signals the host processor in the case of a single bit error-detection and correction event. To write to the device, take Chip Enables (CE 1, CE 2, and CE 3 LOW) and Write Enable (WE) input LOW. If Byte Enable A (B A ) is LOW, then data from I/O pins (I/O 0 through I/O 7 ) is written into the location specified on the address pins (A 0 through A 18 ). If Byte Enable B (B B ) is LOW, then data from I/O pins (I/O 8 through I/O 15 ) is written into the location specified on the address pins (A 0 through A 18 ). Likewise, B C and B D correspond with the I/O pins I/O 16 to I/O 23 and I/O 24 to I/O 31, respectively. To read from the device, take Chip Enables (CE 1, CE 2, and CE 3 LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If the first B A is LOW, then data from the memory location specified by the address pins appear on I/O 0 to I/O 7. If B B is LOW, then data from memory appears on I/O 8 to I/O 15. Likewise, B C and B D correspond to the third and fourth bytes. See Truth Table CY7C1062G/ on page 15 for a complete description of read and write modes. The input and output pins (I/O 0 through I/O 31 ) are placed in a high-impedance state when the device is deselected (CE 1, CE 2, or CE 3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (B A-D HIGH), or during a write operation (CE 1, CE 2 and CE 3 LOW and WE LOW). On the device, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High) [1]. CY7C1062G and devices are available in Pb-free 119-ball plastic ball grid array (PBGA) package. For a complete list of related documentation, click here. Note 1. This device does not support automatic write-back on error detection. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *F Revised September 13, 2016

2 Logic Block Diagram CY7C1062G ECC ENCODER DATA IN DRIVERS I/O 0 I/O 7 I/O 8 I/O 15 I/O 16 I/O 23 I/O 24 I/O 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 512K x 32 RAM ARRAY COLUMN DECODER SENSE AMPLIFIERS ECC DECODER WE B D B C B B B A A10 A11 A12 A13 A14 A15 A16 A17 A18 WE CE3 CE2 B D B C B B B A OE CE1 Logic Block Diagram ECC ENCODER DATA IN DRIVERS I/O 0 I/O 7 I/O 8 I/O 15 I/O 16 I/O 23 I/O 24 I/O 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 512K x 32 RAM ARRAY COLUMN DECODER SENSE AMPLIFIERS ECC DECODER WE B D B C B B B A ERR A10 A11 A12 A13 A14 A15 A16 A17 A18 WE CE3 CE2 B D B CB B B A OE CE1 Document Number: Rev. *F Page 2 of 20

3 Contents Pin Configurations... 4 Product Portfolio... 5 Maximum Ratings... 6 Operating Range... 6 DC Electrical Characteristics... 6 Capacitance... 7 Thermal Resistance... 7 AC Test Loads and Waveforms... 7 Data Retention Characteristics... 8 Data Retention Waveform... 8 AC Switching Characteristics... 9 Switching Waveforms Truth Table CY7C1062G/ ERR Output Ordering Information Ordering Code Definitions Package Diagrams Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Cypress Developer Community Technical Support Document Number: Rev. *F Page 3 of 20

4 Pin Configurations A B C D E F G H J K L M N P R T U Figure ball PBGA Pinout (Top View) - CY7C1062G [2] 1 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 NC I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O A 4 A 3 A 2 A 1 A 0 I/O 0 A 18 A 17 CE 1 A 16 A 15 I/O 1 B c CE 2 NC CE 3 B a I/O 2 V DD V SS V SS V SS V DD I/O 3 V SS V DD V SS V DD V SS I/O 4 V DD V SS V SS V SS V DD I/O 5 V SS V DD V SS V DD V SS I/O 6 V DD V SS V SS V SS V DD I/O 7 V SS V DD V SS V DD V SS NC V DD V SS V SS V SS V DD I/O 8 V SS V DD V SS V DD V SS I/O 9 V DD V SS V SS V SS V DD I/O 10 V SS V DD V SS V DD V SS I/O 11 V DD V SS V SS V SS V DD I/O 12 A 14 A 12 A 8 B d NC B b A 13 I/O 13 A 11 WE A 10 A 9 I/O 14 A 7 OE A 6 A 5 I/O 15 Figure ball PBGA Pinout (Top View) - [2] A B C D E F G H J K L M N P R T U 1 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 ERR I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O A 4 A 3 A 2 A 1 A 0 I/O 0 A 18 A 17 CE 1 A 16 A 15 I/O 1 B c CE 2 NC CE 3 B a I/O 2 V DD V SS V SS V SS V DD I/O 3 V SS V DD V SS V DD V SS I/O 4 V DD V SS V SS V SS V DD I/O 5 V SS V DD V SS V DD V SS I/O 6 V DD V SS V SS V SS V DD I/O 7 V SS V DD V SS V DD V SS NC V DD V SS V SS V SS V DD I/O 8 V SS V DD V SS V DD V SS I/O 9 V DD V SS V SS V SS V DD I/O 10 V SS V DD V SS V DD V SS I/O 11 V DD V SS V SS V SS V DD I/O 12 A 14 A 12 A 8 B d NC B b A 13 I/O 13 A 11 WE A 10 A 9 I/O 14 A 7 OE A 6 A 5 I/O 15 Note 2. NC pins are not connected internally to the die. 3. ERR is an Output pin.if not used, this pin should be left floating. Document Number: Rev. *F Page 4 of 20

5 Product Portfolio Product Features and Options (see Pin Configurations on page 4) Range V CC Range (V) Speed (ns) CY7C1062G18 Embedded ECC. No ERR 1.65 V 2.2 V CY7C1062G30 output pin 2.2 V 3.6 V Industrial 18 Embedded ECC. Optional 1.65 V 2.2 V ERR output pin 2.2 V 3.6 V Power Dissipation Operating I CC, (ma) Standby, I SB2 (ma) f = f max Typ [4] Max Typ [4] Max Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = 1.8 V (for V CC range of 1.65 V 2.2 V), V CC =3V and (for V CC range of 2.2 V 3.6 V), T A = 25 C. Document Number: Rev. *F Page 5 of 20

6 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature C to +150 C Ambient temperature with power applied C to +125 C Supply voltage on V CC relative to GND V to V CC V DC voltage applied to outputs in High Z State [5] V to V CC V DC input voltage [5] V to V CC V Current into outputs (LOW) ma Static Discharge Voltage (MIL-STD-883, Method 3015)... > 2001 V Latch-up current... > 140 ma Operating Range Grade Ambient Temperature V CC Industrial 40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range of 40 C to 85 C Parameter Description Test Conditions V OH V OL Output HIGH Voltage Output LOW Voltage 10 ns / 15 ns Min Typ [6] Max 1.65 V to 2.2 V V CC = Min, I OH = 0.1 ma V to 2.7 V V CC = Min, I OH = 1.0 ma V to 3.0 V V CC = Min, I OH = 4.0 ma V to 3.6 V V CC = Min, I OH = 4.0 ma V to 2.2 V V CC = Min, I OL = 0.1 ma V to 2.7 V V CC = Min, I OL = 2 ma V to 3.6 V V CC = Min, I OL = 8 ma V to 2.2 V 1.4 V CC V IH Input HIGH Voltage 2.2 V to 2.7 V 2.0 V CC V to 3.6 V 2.0 V CC V to 2.2 V V IL Input LOW Voltage [5] 2.2 V to 2.7 V V to 3.6 V I IX Input Leakage Current GND < V IN < V CC I OZ Output Leakage Current GND < V OUT < V CC, Output disabled I CC I SB1 I SB2 Operating Supply Current Automatic CE Power-down Current TTL Inputs Automatic CE Power-down Current CMOS Inputs V CC = Max, I OUT = 0 ma, CMOS levels f = 100 MHz f = 66.7 MHz Max V CC, CE > V IH [7], V IN > V IH or V IN < V IL, f = f MAX 40.0 Max V CC, CE > V CC 0.2 V [7], V IN > V CC 0.2 V or V IN < 0.2 V, f = Unit V A ma 5. V IL(min) = 2.0 V and V IH(max) = V CC + 2 V for pulse durations of less than 20 ns. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = 1.8 V (for V CC range of 1.65 V 2.2 V), V CC =3V (for V CC range of 2.2 V 3.6 V), and T A = 25 C. 7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. Document Number: Rev. *F Page 6 of 20

7 Capacitance Parameter [8] Description Test Conditions 119-ball PBGA Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, V CC = V CC(typ) 10 pf C OUT I/O Capacitance Thermal Resistance Parameter [8] Description Test Conditions 119-ball PBGA Unit JA JC Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Still air, soldered on a inch, four layer printed circuit board C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [9] Output Z 0 = 50 (a) * Capacitive load consists of all components of the test environment 50 V TH 30 pf* V HIGH 90% 10% GND Rise Time: > 1 V/ns All Input Pulses (c) High-Z Characteristics: R1 V CC Output 5 pf* * Including JIG and Scope (b) 90% 10% Fall Time: > 1 V/ns R2 Parameters 1.8 V 3.0 V Unit R R V TH V HIGH V 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full-device AC operation assumes a 100-µs ramp time from 0 to V CC (min) and 100-µs wait time after V CC stabilizes to its operational value. Document Number: Rev. *F Page 7 of 20

8 Data Retention Characteristics Over the Operating Range of 40 C to 85 C Parameter Description Conditions Min Max Unit V DR V CC for Data Retention 1.0 V I CCDR t CDR [11] t R [11, 12] Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time V CC = V DR, CE > V CC 0.2 V [10], V IN > V CC 0.2 V or V IN < 0.2 V 30.0 ma 0.0 V CC > 2.2 V 10.0 V CC < 2.2 V 15.0 ns Data Retention Waveform Figure 4. Data Retention Waveform [10] V CC V CC(min) DATA RETENTION MODE V DR = 1.0 V V CC(min) t CDR t R CE 10. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear V CC ramp from V DR to V CC(min.) > 100 s or stable at V CC(min.) > 100 s. Document Number: Rev. *F Page 8 of 20

9 AC Switching Characteristics Over the Operating Range of 40 C to 85 C Parameter [13] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle t POWER V CC (stable) to the first access [14, 15] s t RC Read cycle time t AA Address to data / ERR valid t OHA Data / ERR hold from address change t ACE CE LOW to data / ERR valid [16] t DOE OE LOW to data / ERR valid t LZOE OE LOW to low Z [17, 18] t HZOE OE HIGH to high Z [17, 18] t LZCE CE LOW to low Z [16, 17, 18] ns t HZCE CE HIGH to high Z [16, 17, 18] t PU CE LOW to power-up [15, 16] t PD CE HIGH to power-down [15, 16] t DBE Byte enable to data valid t LZBE Byte enable to low Z t HZBE Byte disable to high Z Write Cycle [19, 20] t WC Write cycle time t SCE CE LOW to write end [16] t AW Address setup to write end t HA Address hold from write end t SA Address setup to write start t PWE WE pulse width ns t SD Data setup to write end t HD Data hold from write end t LZWE WE HIGH to low Z [17, 18] t HZWE WE LOW to high Z [17, 18] t BW Byte Enable to write end Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V CC > 3 V) and V CC /2 (for V CC < 3 V), and input pulse levels of 0 to 3 V (for V CC > 3 V) and 0 to V CC (for V CC < 3V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 7, unless specified otherwise. 14. t POWER gives minimum amount of time that the power supply is at stable Vcc until first memory access is performed. 15. These parameters are guaranteed by design and are not tested. 16. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 17. t HZOE, t HZCE, t HZWE, t HZBE, t LZOE, t LZCE, t LZWE, and t LZBE are specified with a load capacitance of 5 pf as in (b) of Figure 3 on page 7. Transition is measured 200 mv from steady state voltage. 18. Tested initially and after any design or process changes that may affect these parameters. 19. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 20. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE Low) should be sum of t HZWE and t SD. Document Number: Rev. *F Page 9 of 20

10 Switching Waveforms Figure 5. Read Cycle No. 1 of CY7C1062G (Address Transition Controlled) [21, 22] t RC ADDRESS t AA t OHA DATA I/O PREVIOUS DATA OUT VALID DATA OUT VALID Figure 6. Read Cycle No. 1 of (Address Transition Controlled) [21, 22] t RC ADDRESS t AA t OHA DATA I/O PREVIOUS DATA OUT VALID DATA OUT VALID t AA t OHA ERR PREVIOUS ERR VALID ERR VALID 21. The device is continuously selected, OE, CE, B A, B B, B C, B D = V IL. 22. WE is HIGH for read cycle. Document Number: Rev. *F Page 10 of 20

11 Switching Waveforms (continued) Figure 7. Read Cycle No. 2 (OE Controlled) [23, 24, 25] ADDRESS t RC CE t PD t ACE t HZCE OE t DOE t HZOE t LZOE B A-D t DBE t LZBE t HZBE DATA I/O HIGH IMPEDANCE DATA OUT VALID HIGH IMPEDANCE t LZCE V CC SUPPLY CURRENT t PU I SB 23. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 24. WE is HIGH for read cycle. 25. Address valid before or similar to CE transition LOW. Document Number: Rev. *F Page 11 of 20

12 Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (CE Controlled) [26, 27, 28] t WC ADDRESS t SA t SCE CE t AW t PWE t HA WE t BW B A-D OE t HZOE t SD t HD DATA I/O Note 29 DATA IN VALID 26. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 27. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 28. Data I/O is high impedance if CE or OE or B A, B B, B C, B D = V IH. 29. During this period I/O are in output state. Do not apply input signals. Document Number: Rev. *F Page 12 of 20

13 Switching Waveforms (continued) Figure 9. Write Cycle No. 2 (WE Controlled, OE Low) [30, 31, 32, 33] t WC ADDRESS CE t SCE B A-D t BW WE t SA t AW t PWE t HA thzwe t SD t HD t LZWE DATA I/O Note 34 DATA IN VALID 30. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 31. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 32. Data I/O is high impedance if OE or B A, B B, B C, B D = V IH. 33. The minimum write cycle pulse width should be equal to sum of t HZWE and t SD. 34. During this period I/O are in output state. Do not apply input signals. Document Number: Rev. *F Page 13 of 20

14 Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (B A, B B, B C, B D Controlled) [35, 36, 37] t WC ADDRESS CE t SCE t AW t SA t BW t HA B A-D WE t PWE t HZWE t SD t HD t LZWE DATA I/O Note 38 DATA IN VALID 35. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1, CE 2, and CE 3 LOW. When HIGH, CE indicates the CE 1, CE 2, or CE 3 HIGH. 36. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 37. Data I/O is high impedance if OE or B A, B B, B C, B D = V IH. 38. During this period I/O are in output state. Do not apply input signals. Document Number: Rev. *F Page 14 of 20

15 Truth Table CY7C1062G/ CE 1 CE 2 CE 3 OE WE B A B B B c B D I/O 0 I/O 7 I/O 8 I/O 15 I/O 16 I/O 23 I/O 24 I/O 31 Mode Power H X [39] X [39] X [39] X [39] X [39] X [39] X [39] X [39] High Z High Z High Z High Z power-down (I SB ) X [39] H X [39] X [39] X [39] X [39] X [39] X [39] X [39] High Z High Z High Z High Z power-down (I SB ) X [39] X [39] H X [39] X [39] X [39] X [39] X [39] X [39] High Z High Z High Z High Z power-down (I SB ) L L L L H L L L L Data out Data out Data out Data out Read all bits (I CC ) L L L L H L H H H Data out High Z High Z High Z L L L L H H L H H High Z Data out High Z High Z L L L L H H H L H High Z High Z Data out High Z Read byte A bits only Read byte B bits only Read byte C bits only L L L L H H H H L High Z High Z High Z Data out Read Byte D bits only (I CC ) L L L X [39] L L L L L Data in Data in Data in Data in Write all bits (I CC ) L L L X [39] L L H H H Data in High Z High Z High Z L L L X [39] L H L H H High Z Data in High Z High Z L L L X [39] L H H L H High Z High Z Data in High Z L L L X [39] L H H H L High Z High Z High Z Data in L L L H H X [39] X [39] X [39] X [39] High Z High Z High Z High Z L L L X [39] X [39] H H H H High Z High Z High Z High Z Write byte A bits only Write byte B bits only Write byte C bits only Write byte D bits only Selected, outputs disabled Selected, outputs disabled (I CC ) (I CC ) (I CC ) (I CC ) (I CC ) (I CC ) (I CC ) (I CC ) (I CC ) ERR Output Output [40] Mode 0 Read Operation, no single-bit error in the stored data. 1 Read Operation, single bit error detected and corrected. High Z Device deselected or Outputs disabled or Write Operation. 39. The input voltage levels on these pins should be either at V IH or V IL. 40. ERR is an Output pin. If not used, this pin should be left floating. Document Number: Rev. *F Page 15 of 20

16 Ordering Information Speed (ns) Voltage Range Ordering Code Package Diagram Package Type (Pb-free) ERR Ball V 3.6 V CY7C1062G30-10BGXI ball PBGA No CY7C1062G30-10BGXIT 119-ball PBGA, Tape & Reel No 30-10BGXI 119-ball PBGA Yes 30-10BGXIT 119-ball PBGA, Tape & Reel Yes Operating Range Industrial Ordering Code Definitions CY 7 C G E BG X I X X: T = Tape & Reel; Blank = Bulk Temperature Range: I = Industrial Pb-free Package Type: BG = 119-ball PBGA Speed: 10 ns Voltage Range: 30 = 2.2 V 3.6 V ERR output Single bit error indication Process Technology: 65 nm Data width: 2 = 32-bits Density: 06 = 16-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: Rev. *F Page 16 of 20

17 Package Diagrams Figure pin PBGA ( mm) BG119 Package Outline, *D Document Number: Rev. *F Page 17 of 20

18 Acronyms Document Conventions Acronym Description Units of Measure CE CMOS I/O OE PBGA SRAM TTL WE Chip Enable Complementary Metal Oxide Semiconductor Input/Output Output Enable Plastic Ball Grid Array Static Random Access Memory Transistor-Transistor Logic Write Enable Symbol C degree Celsius MHz megahertz A microampere s microsecond ma milliampere mm millimeter ns nanosecond ohm % percent pf picofarad V volt W watt Unit of Measure Document Number: Rev. *F Page 18 of 20

19 Document History Page Document Title: CY7C1062G/, 16-Mbit (512 K words 32 bits) Static RAM with Error-Correcting Code (ECC) Document Number: Rev. ECN No. Orig. of Change Submission Date Description of Change *E NILE 07/31/2015 Changed status from Preliminary to Final. *F NILE 09/13/2016 Updated DC Electrical Characteristics: Enhanced V OH for voltage range 3.0 V to 3.6 V from 2.2 V to 2.4 V. Updated Footnote 5. Updated part numbers in Ordering Information. Added Tape & Reel ordering codes. Updated copyright notice and Sales, Solutions, and Legal Information. Document Number: Rev. *F Page 19 of 20

20 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless PSoC Solutions PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Cypress Developer Community Forums Projects Video Blogs Training Components Technical Support cypress.com/support Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: Rev. *F Revised September 13, 2016 Page 20 of 20

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