Considerations When Using the 66 MHz as an Accelerated Graphics Port - Peripheral Component Interconnect Bridge

Transcription

1 Considerations When Using the 66 MHz as an Accelerated Graphics Port - Peripheral Component Interconnect Bridge White Paper April 1999 Order Number:

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel s website at Copyright Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. Application Note

3 Contents 1.0 Introduction DC Parameters AC Parameters Additional Considerations Revision History...4 Figures Tables 1 Typical in AGP-PCI Bridge Application MHz PCI vs. AGP Timing AGP vs. PCI - DC Parameter Comparison AGP vs. PCI - AC Parameter Comparison...2 Application Note iii

4 1.0 Introduction Note: This document compares the PCI Local Bus Specification, Revision 2.1 and the AGP Interface Specification, Revision 2.0 as they apply to the PCI-to-PCI Bridge. It highlights relevent differences between these specifications, and indicates potential design issues where careful design considerations are warranted. There is considerable interest in using the 66 MHz PCI-PCI Bridge as an Accelerated Graphics Port (AGP) - Peripheral Component Interconnect (PCI) Bridge. The 66 MHz PCI-PCI Bridge was not specifically designed for this application, and is not fully compliant with the AGP Interface Specification, Revision 2.0. However, understanding the differences between the AGP Interface Specification, Revision 2.0 and PCI Local Bus Specification, Revision 2.1, and using careful signal-integrity analysis, should allow for the successful implementation of the in AGP-PCI designs. Figure 1 shows the typical use of the in an AGP environment. Initialization of an AGP device is done using the configuration mechanism defined by the PCI Local Bus Specification, Revision 2.1. During initialization, the AGP core logic uses the PCI Capabilities List to determine the AGP capabilities of a connected agent. The does not have an Extended Capabilities Pointer and will be detected as a standard PCI device. The AGP is a 3.3 V signaling environment and when connecting a to the AGP interface, the PVIO pin must be connected to 3.3 V. If 66 MHz capable PCI devices are placed downstream of the (secondary side), then the SVIO pin must also be connected to 3.3 V. Figure 1. Typical in AGP-PCI Bridge Application Processor PCI 66MHz or 33MHz (66MHz) A.G.P. Chipset System Memory A Note: While some customers may choose to use the Intel PCI-to-PCI bridge as an AGP-PCI bridge, Intel has not validated nor can it guarantee its use in this type of application. As a result, the information described in this application note is for reference only and any customer that uses Intel bridges in the manner described does so at their own risk. This specifically means all warranties will be void and the AGP-PCI bridge may not be returned if it fails to perform properly. 1 Application Note

5 2.0 DC Parameters The DC parameters listed in Table 1 differ between the PCI (3.3 V signaling) and AGP specifications: Table 1. AGP vs. PCI - DC Parameter Comparison Parameter AGP PCI V OH (Iout=-500µA) V OL (Iout=1500µA) 2.83 V min 2.7 V min V max 0.36 V max V IH V min 1.5 V min V IL V max 1.08 V max C IN 8pF max 10pF max The V IH and V IL specifications do not present a problem because the PCI specified values provide some margin over those required by AGP. The higher input capacitance of a PCI device could present some difficulties. Because AGP is a point-to-point connection and not a bus environment like PCI, it requires much less buffer strength. Driving a higher capacitive load with smaller buffers and vice versa could result in signal-integrity problems. For this reason, we strongly recommend extensive signal-integrity analysis by reviewing the VI curves of the and AGP device. An IBIS model of the 66 MHz is readily available in order to conduct this investigation. The minimum PCI V OH value is slightly lower than the AGP specification and the V OL maximum is slightly higher. However, these values provide sufficient margin to meet the V IH and V IL requirements of both AGP and 66 MHz PCI. 3.0 AC Parameters The AC parameters listed in Table 2 differ between the PCI and AGP specifications: Table 2. AGP vs. PCI - AC Parameter Comparison Parameter AGP PCI Minimum Maximum Minimum Maximum Clock to Control Signal Delay 1 ns 5.5 ns 2 ns 6 ns Clock to Data Delay (Tval) 1 ns 6 ns 2 ns 6 ns Data Setup Time (Tsu) 5.5 ns 3 ns Control Signal Setup Time (P-P) 6 ns 5 ns Edge Rate 1.5 V/ns 4 V/ns 1 V/ns 4 V/ns Prop Delay (Tprop) 2.5 ns 5 ns Ton (Float to Active) 1 ns 6 ns 2 ns Application Note 2

6 The differences listed in Table 2 are not a concern when designing with the in an AGP application. In the cases of Clock to Data Delay, Control Signal Setup Time, and Float to Active, the specified PCI values provide additional margin or are within the AGP limits. Meeting the tighter minimum edge rate of the AGP specification is possible given the design of the The maximum PCI value for the Clock to Control Signal Delay is 0.5 ns greater in the PCI specification. However, the will have sufficient margin to satisfy this AGP requirement. Figure 2 shows the timing breakdown of the 15 ns cycle times for 66 MHz PCI and AGP. The primary difference is in the setup time and propagation delay. AGP allows less propagation delay (shorter board trace) and a larger setup time while PCI allows more propagation delay and less setup time. The system time is the combination of setup time and propagation delay, which in both cases adds up to 8.0 ns. The board designer who implements the must control the board trace lengths in order to comply with the AGP 2.5 ns propagation delay requirement. The maximum clock skew for both 66 MHz PCI and AGP is 1.0 ns. Careful attention should be paid to the routing of secondary clocks on the board in order to minimize the skew. Use the same etch length and impedance for the s_clk input as for the s_clk_o signals. Unused secondary clocks should be disabled or terminated. Figure MHz PCI vs. AGP Timing 66MHz PCI Cycle Tval = 6n Tcyc = 15n Tprop = 5n Tsu = 3n Tskew = 1ns A.G.P. Cycle Tcyc = 15n Tval = 6n Tprop = 2.5n Tsu = 5.5n Tskew = 1ns A Additional Considerations AGP does not have support for the PCI LOCK#, INTC#, INTD#, PERR# and SERR# signals. For the system to operate properly, the p_lock_l and s_lock_l signals must be pulled high through an external pull-up resistor. LOCK# should not be used either directly or indirectly. Executing an exclusive access to a downstream target, or performing a locked read operation when posted write data is in the buffers, could potentially cause a deadlock condition. To avoid this potential problem, drivers must be specially written to avoid accessing PCI resources with lock cycles (XCHG instruction), or ensure that the locked accesses do not cross dword boundaries. 3 Application Note

7 AGP has support for only two interrupt signals INTA# and INTB#. A BIOS will assume an association between a device location behind a PCI-PCI bridge and which INTx# line it uses to request an interrupt. By halving the amount of interrupts, the number of possible device locations behind the bridge will also be halved. Proper binding between the IDSEL and INTx# lines behind a bridge must be maintained. No support for both PERR# and SERR# could have several negative implications. System and expansion board designers should be aware of the potential problems and implement the appropriate workarounds. Using the AGP port as another PCI bus segment connected to the host bus creates additional data transfer paths. These paths are documented in the AGP Interface Specification, Revision 2.0, Section Implementers should refer to this section of the AGP Interface Specification, Revision 2.0 to determine what PCI commands are supported by the core logic. Some commands are required, others are optional, and some like Interrupt Acknowledge and Special Cycles will not be supported on the AGP port. Table 6-1 in the AGP Interface Specification, Revision 2.0 lists the commands that core logic is required to support and those that are optional. 5.0 Revision History Revision Revision History Date Rev 1.0 Initial release of Considerations When using the 66MHz as an Accelerated Graphics Port - Peripheral Component Interface Bridge 4/99 Application Note 4