Basic System Memory Architecture View (Functional)

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Marilyn Anis Gregory
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1 Memory Organization

2 Basic System Memory Architecture View (Functional) Notation: [FFFE]=27h FFFE: 27

3 Basic Characteristics (1/3) Memory cell registers are one byte wide Memory Word is the contents of the cell, usually in hex notation. Data wider than one byte uses two or more memory cells. Reading or writing memory words is done through the Data Bus

4 Basic Characteristics (2/3) Each memorycell is identified by an address The address is independent from contents! The CPU can read/write the memory cell only if the Address Bus has the address of the cell The address of the cell is a physical address Notation: To indicate the contents of a memory cell we write [addr] = contents (for ex: [0200h] = 8Ah) Unless indicated otherwise, hex notation is used ( [0200]=8A ) Memory segment: A set of memory cells with contiguous addresses.

5 Basic Characteristics (3/3) The Control Bus carries signals that are used to indicate what type of transactions are done with memory, if transaction is done with memory and so on

6 Memory Types (1/3) Classification Classified according to Storage permanence: how long data is maintained Write ability: data can be written at normal running voltage and speed conditions Storage permanence classes: Volatile memory: looses its contents when power is removed Non volatile memory: does not loose its contents when power is removed

7 Memory Types (2/3): Volatility Non volatile Examples: ROM structures: ROM, OPROM, EPROM, EEPROM Ferro Electric RAM (FRAM, FeRAM) Flash Memory Vltil Volatile Examples Static RAM (SRAM) Dynamic RAM (DRAM) Popular non volatile in MCU: Flash, FRAM

8 Memory Types (3/3): Write ability Non writable Examples: ROM structures: ROM, OPROM, EPROM, EEPROM Flash Writable Examples Static RAM (SRAM) Dynamic RAM (DRAM) FRAM FRAM memory has both non volatility and write ability

9 Comments on memory RAM (Random Access Memory) is usually used as a generic term to refer to writable and volatile memory The term ROM (Read Only Memory) is used as a generic term to refer to non writable and nonvolatile memory independently of the truthness Modern non writable memory is in fact writable, but at dff different voltages generated internally, and at slower speeds

10 More memory concepts: Physical and Data address. (1) Unless otherwise noted, memorywords will be onebyte size. Physical Address: Address of a memory cell Data size dictates how many memory words are required: 1 to 8 bits: 1 memory word 9 to 16 bits: 2 memory words Data is stored in contiguous memory cells. DATA Address: The lowest physical address of the cells occupied by data.

11 More memory concepts: Physical and Data address. (2) DATA Address: The lowest physical address of the cells occupied by data. Example 1: For data address 0F208 for 456F, physical addresses are 0F208 and 0F209. Example 2: For data address 0F208 for 456FA2B1, physical addresses are 0F208, 0F209, 0F20A, and 0F20B Notation: ti In diagrams and figures, as well as notation, ti cells may be shown in byte, word, double word sizes. Examples: 0F208: 2A or [F208] = 2A 0F208: 2AB9 or [F208] = 2AB9 0F208: 2F1A40CD or [F208] = 2F1A40CD

12 Little endian vs. big endian (1) Little endian: The data address points to the least significant byte of data (i.e., LSB in lowest physical address) Big endian: The data address points to the most significant byte of data (i.e., MSB in lowest physical address) [4300]=342B Little endian: [4300]= 2B, [4301]= 34 Big endian: [4300]= 34, [4301]= 2B

13 IAR Memory Window (1) To open Memory Window Memory Window

14 IAR Memory Window (2) To examine specific Address Zone Memory menu Use memory menu to select views byte (1x) word d(2 (2x) double word (4x) Little Endian or Big Endian Address of first byte in row (In HEX) Sixteen bytes per row ASCII value when present

15 IAR Memory Window (2) (word and double word views) Word view (Little endian) Double word view (Little endian)

16 Program and Data memory Data memory is used for storing variables and data expected to change during program execution. Program memory is used to store system programs and data that will not change during program execution and should not be lost when power is removed

68HC11, Intel 80x86/Pentium Harvard Architecture: Program and data storage

17 Von Neumann and Harvard architectures Von Neumann (Princeton) architecture: Programand and data Memories share the system buses Example: MSP430, 68HC11, Intel 80x86/Pentium Harvard Architecture: Program and data storage have different memory spaces, different buses. Example: PIC MCU, Intel 8051, Atmel

18 Memory Map Memory Map: model representation of the usage given to the addressable space Example: A global Map

19 Example of a partial map: Memory Map (2)

20 CPU and Memory Hardware connection MEMORY INTERFACE

21 Basic considerations Hardware wise, the memory is distributed in banks. Usually, these banks constitute a set of byte registers (virtually or actually) The outputs of these registers are connected via internal buses to the Data Bus. The selection of a particularregister register isdone through terminals connected to the address bus. Interfacing consists in connecting the banks to the Interfacing consists in connecting the banks to the Data, Address and Control buses so that transactions can be made by the CPU

22 Basic Functional description of a bank A(n-1) A(n-2) A0 Internal Address Decoder Y(2 n-2 ) ---- Y0 word 2^(n 1) word 2^(n 2) Word 0 Read/ wr rite Routin ng Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CS Write Read

23 Example: ATMEL AT28C256 32KB (256 Kbits) EEPROM t /I /d df Pin Name A0 A14 Function Addresses CE OE WE Chip Enable Output Enable Write Enable I/O0 I/O7 Data Inputs/Outputs NC DC No Connect Don t Connect

24 Extract from Data sheet (1) Block Diagram

25 Extract from Data sheet (2) Operating Modes

26 Interface Principles for 8 bit Data bus systems Theeight eight IOoutputs of each bank areconnected to the Data Bus in the ordered sequence IO0 with D0, IO1 to D1, etc. For each bank the Address bus bits, are divided in two disjoint subsets: One subset directed toward the selection of internal registers One subset bsetin charge of activating ating the bank using an address decoder for the bank

27 Basics of memory interfacing ADDRESS BUS N>M BITS Memory Chip M bits from Address Bus A0 IO 0 A1 IO IO 7 DATA BUS N-M bits from Address Bus Signals from Control Bus Address Decoder.. A(M-1) CE

28 Basic Analysis Procedure Determine the combination of address bus bits that activates the bank. This set is fixed for all addresses in the space covered by the bank. Vary the set of Address Bus Bits that determine the bank s internal address from from to 11 1 to establish the set of addresses If this set is a least significant group, then the bank covers a segment Do this for each bank. The set of banks may or may Do this for each bank. The set of banks may or may not define a segment.

29 Analysis Examples on Blackboard.

30 Basic design Procedure (Data bus 8 bits) (1/2) Specify an appropriate segment or set of addresses to be covered by the bank Select the set of Address Bus Bits that will determine the bank s internal address as they change from to 11 1 Usually, this set is the least significant group, If there are many banks involved, select the group of bits that will discriminate among banks The rest of the bits are used to activate the whole set of banks.

31 Basic design Procedure (Data bus 8 bits) (1/2) An alternative and easy procedure is tu use programmable PLA or ROM s as address decoders for banks

32 Design examples on blackboard

33 Interface Principles for 16 bit Data bus systems Two banks are needed to connect to the 16 bits of bus. They work by pairs One bank is connected to least significant byte, the other to the most significant ifi tbt byte A) IO0 with D0, IO1 to D1, IO7 to D7. B) IO0 with D8, IO1 to D9. IO7 to D15 Which one goes to the LSB will determine little or big endianess. One bank of the pair works with even addresses (AD. Bus A0=0) and the other withodd addresses (A0=1) The control bus has a signal the indicates if we work with a bank only (byte operation) or with the pair (word operation)

34 Memory Interfacing (Data bus width 16 bits) Note: This is a little endian scheme ADDR. B US: AK A1 High Bank (Odd address) A0 * * A(K-1) CE IO 0 * * IO 7 Dat ta bus: D15 D8 ADDR. B US: AK A1 Low Bank (Even address) A0 * * A(K-1) CE IO 0 * * IO 7 Da ata bus: D7 D0 (A0=1) (A0 = 0) ADDR. Bus A0 ADDR. Bus A(N-1) A(K+1) ADDRESS DECODER Control Bus Signals

35 Basic Principles for 16 bit Data bus (explained with 2KB banks) Internal Addresses established with AD. Bus bits A11 A10 A2 A1 123FF 123FD ******* ******* FF 7FE **** **** Odd address 123FE 123FC ******* ******* Addresses seen by system 7FF 7FE **** **** Even address Address Decoder Operation: 1. If byte data and A0 = 0, activate even address bank only. 2. If byte data and A0 = 1, activate odd address bank only. 3. If word data, activate both banks Note: Connection to data bus determines endianness

Inputs to the system: A0, Y and W/B (1 if word, 0 if byte) Outputs: OddEn, EvenEn both active low Y W/B A0 OddEnn EvenEn 0 0 0 1 0

36 An example : discriminating among banks in one pair Use the previous criteria, adding an active low signal Y to select the system: Y is low, the banks are used and selected according to criteria. If Y = 1, the Modules cannot be enabled. Inputs to the system: A0, Y and W/B (1 if word, 0 if byte) Outputs: OddEn, EvenEn both active low Y W/B A0 OddEnn EvenEn X X 1 1 OddEn ' = Y ' + A0 W / B' EvenEn = Y '+ A0 W / B Note: Y is controlled by other address bus bits and/or control bus bits

39 And for several pairs. Y0 and Y1 may be, for example, outputs of an active low decoder..

40 EXAMPLES ON BLACKBOARD

41 IO Subsystem IV Ports and peripherals

42 IO Subsystem (1) All devices connected to the system buses, other than memory and CPU Input and output ports (I/O): interface CPU with external world directly Input port Output port Input/Output port Peripherals: May be only internal to system or may have also external connection

43 IO Subsystem (2) Input transaction: Information toward CPU Output transaction: Information from CPU Important (not exhaustive) peripherals: Timers: Uses such as measuring time intervals between two events, generate interrupts at specified and many others. Wthd Watchdog Timer (WDT): Sft Safety device and/or timer ADC and DAC: to deal with analog inputs/outputs.

44 IO Structure Data Registers: Input and Output Control Registers: Used for I/O and peripheral configuration Status registers: Show information about information transfer or configuration status Control registers may contain status bits.

45 IO Mapped vs. Memory Mapped IO Mapped IO - Different sets of addresses - Different instructions for transfers Memory Mapped IO - Same system of addresses - Same instructions for transfers

46 IO Mapped vs Memory Mapped (2) IO mapped I/O has different sets of addresses for memory and for I/O subsystem CPU distinguishes address with type of instruction Example: 8086 uses MOV for transfers to/from memory, OUT to transfer to Output port, and IN from port. Routing of address bus is done by control bus according to instruction. Memory mapped I/O does not distinguish between types User must know memory map (or names ).

47 IO Ports: Remarks Input port Buffered: Readable only at a given moment Latched: Readable on demand Must not be left floating Interruptible or non interruptible Output port Always Latched

48 Important Remark for Input Do not leave an input floating: If necessary use pull up or pulldown resistors Pulldown Resistor Pullup Resistor

49 Example: MSP430 General Purpose I/O ports

50 General Purpose I/O (8 bits) Named P0 to P10 a ed 0 to 0 Number of ports and available bits depends on model P1 and P2 have interrupt capability Bit independently programmable Edge selectable interrupt capability Some series have individually programmable pulldown/pull up resistors Depending on model, pins can be configured for special I/O

51 B7 B4 B3 B2 B1 B0

52 Simplified Hardware configuration: 1. Non interruptible port Data Registers C t Control Registers

53 Basic I/O Registers (1/3) Function Selection Register (PxSEL): Selects the connection for the pin, either to the port or to other peripheral(s) 0: Connected to port (default) 1: Connected to other module(s) To connect pin 12to 1.2 port (if necessary, since it is connected by default), clear bit 2 of (P1SEL) [bic.b #BIT2, &P1SEL] To connect pin 1.2 to module, set bit 2 of (P1SEL) [bis.b #BIT2, &P1SEL] Direction Register (PxDIR): Selects in or out direction function for pin 1: Output direction 0: Input tdirection (default) Example: mov.b #0xF0, &P1DIR configures pins 4 to7 as outputs and 0 to 3 as inputs

54 Basic I/O Registers (2/3) Output Register (PxOUT): to write signal to output To output the word 0x2A to port 2: (P2OUT) #2Ah [mov.b #0x2A,&P2OUT] Input Register (PxIN): Read only register Example: mov.b &P1IN, R6 transfers input to R6 Avoid writing to this register (power consumption and does nothing)

55 Multiple peripherals pins: (3/3) SeveralFunctionSelect Select Registers (PxSEL y PxSEL2 for 2xx family): For example, in 2xx family PxSEL PxSEL2: 00: I/O pin 01: Primary peripheral module 10: Reserved (device specific) 11: Secondaryperipheral module Consult data sheets and user guides for specific information.

56 More Examples: To put pins 0, 1 and 6 of Port 3 in output mode and all the others as input: (P3DIR) # b [ mov.b #0x43,&P3DIR] To put pins 0, 1 and 6 of Port t3 in output tmode leaving the others unchanged: (P3DIR) # 0x43 OR (P3DIR) [ bis.b b #0x43,&P3DIR ] To check status (high or low) or the input at pin 3 of input port 2: Test bit 3 of port 2 [bit.b #BIT3,&P2IN]

57 Interruptible I/O ports (P1 and P2) Each pin has individual interrupt capability which can be enabled or disabled independently of other pins. Has the same registers as non interruptible I/O ports, plus threeadditional registers (all read and write registers) Interrupt capability is lost when pin is selected for peripheral

58 Simplified Hardware Configuration: Interruptible port Control Registers Status Register

59 Interruptible Port Registers Interrupt Enable Register (PxIE): enables interrupt capability 1 enabled, 0 disabled (0 default) bis.b #BIT0, &P1IE enables interrupt capability of pin P1.0 Interrupt requests from I/O ports are maskable Interrupt tcapability is lost if pin is used for other module. Interupt Edge Select Register (PxIES): 1: high to low, 0 low to high (0 default) Interrupt Flags (PxIFG) Automatically set when interrupt is generated Writable, so interrupt may be generated by software ATTENTION: I/O IFG Reset only by software (Ex. bic.b b #BIT0,P1IF) 0: no interrupt pending, 1: interrupt pending

60 I/O Ports with Pull up Pull down Resistor (Example from MSP430g2211 data sheet. Consult specific information for other models. Diagram is not complete) PSEL PDIR Pout PREn Condition 0 0 x 0 IN, no R In, R pull down IN, pull up R Out 0 1 x 1 Illegal Use with module

61 Remarks In your launchpad: Check if R pull up is connected at P1.3 if using push button (see next slide) If not, connect with software: bic.b b #BIT3,&P1DIR ; verify input status bis.b #BIT3,&P1REN ; connect resistor and bis.b #BIT3,&P1OUT ; set it as pull up Make an habit to set unused port pins as outputs.

62 USB Connector Pull-up Resistors: R34 for user key* and R27 for reset key Left Port Header J1 Jumper Set J3 Right Port Header J2 MSP430 Optional Power Port * Note: R34 not in later versions. It must be configured internally User Key Jumper Set J5 Reset Key

6. General purpose Input/Output

Chapter 6 6. General purpose Input/Output This chapter starts with a description of one of the simplest integrated peripherals of the MSP430 the General Purpose 8-bit Input Output (GPIO). The Input/Output