Custom Sensor-Based Embedded Computing Systems. Frank Vahid

Transcription

1 Custom Sensor-Based Embedded Computing Systems Frank Vahid Professor Dept. of Computer Science and Engineering University of California, Riverside Assoc. Director, Center for Embedded Computer Systems, UC Irvine eblocks project 2002-present, support provided by the National Science Foundation and Intel Ph.D. student: Susan Lysecky (2006, w Asst. Prof. at U. Arizona); several MS and undergrad students also

2 The Problem What do these problems all have in common? A small store owner with many employees are they in the storeroom, breakroom, or out back? A working adult with an ageing parent at home did she get out of bed today, is she moving around? A homeowner who sometimes forgets to close the garage at night Marines wishing to outfit a building to detect whether someone is inside or when someone was inside Frank Vahid, UC Riverside 2/32

3 The Problem What do these problems all have in common? Put motion and sound sensors throughout, small LEDs (lights) near cash register Put motion sensors around the house, monitor from the web or cell phone or even be tified if motion by certain time in the morning Install contact sensor and light sensor, and indicator next to the bed Place motion, heat, and sound sensors in rooms, halls, doorways Frank Vahid, UC Riverside 3/32

4 Why Can t We Just Do This? Widely usable Lego -like sensors don t exist today Costly, hard to use, plugged into wall... light sensor transmit AND contact switch receive LED But new techlogy makes Lego-like sensor blocks possible... Frank Vahid, UC Riverside 4/32

5 Shrinking Processor Size/Cost Enables New Solution Courtesy of Joe Kahn Make sensors smarter By adding processor+battery Today, tiny and cheap Becomes a "block" easily connected to other blocks Frank Vahid, UC Riverside 5/32

6 Shrinking Processor Size/Cost Enables New Solution eblocks Existing component view New "eblock" view Button / Light Sensor / Magnetic Contact Switch / / LED / Beeper / Electric Relay Frank Vahid, UC Riverside 6/32

7 eblocks Just connect blocks, and they work Button / / Beeper No programming kwledge, electronics kwledge Light Sensor / / LED Frank Vahid, UC Riverside 7/32

8 eblocks Add intermediate blocks that compute and maintain state Spatial programming more intuitive to n-cs people than temporal programming Button Light Sensor Button Toggle Beeper When A is AND OR B is Light Sensor Button Tripper LED Combine then the output is Prolong Frank Vahid, UC Riverside 8/32 LED

9 What's Hard (1) Finding right set of building blocks Too many Overwhelming (too much choice) 2-Input Logic Toggle Tripper Splitter Splitter Too few Overwhelming (too much configuration) Input Logic Prolong (short) Splitter When A is 2 AND OR B is then the output is Input Logic Prolong (long) 5: Splitter 6:... When A is AND OR Combine B is then the output is 2 Yes detector 2 No detector SuperBlock Frank Vahid, UC Riverside 9/32

10 What's Hard (2) Making the blocks understandable People NOT likely to read directions Those that do are unlikely to understand Performed extensive user testing (over 500 students, kids, and adults) over two years Example: Combine block A B Output Logic Block Logic Sentence Frank Vahid, UC Riverside 10/32 configurable DIP switch Combine When the input is Most success A B : A is, B is A is, B is A is, B is A is, B is Phrased truth table A B A is, B is A is, B is A is, B is A is, B is Combine the output should be The output should be when: out Phrased truth table embedded in sentence When the input is A B A B A B A B A B The output should be out Combine Colored truth table embedded in sentence When A is AND OR B is then the output is Combine

11 What's Hard (3) Batteries must last years, yet performance should appear continuous Blocks are off 99.9% of the time Developed theory to map eblock events to continuous time Developed custom CAD tool to automatically find the best block parameter settings out of the billions of possibilities (a) (b) (c) (d) f t f f < < error < < f t f f error time interpreted as Frank Vahid, UC Riverside 11/32

12 eblocks Example "Garage Open at Night" detector <10 minutes to build Light Sensor Detect night-time use Light Sensor block When A is AND OR B is then the output is Combine LED Need to indicate garage open at night use LED block Plug pieces together and the system is done! Magnetic Contact Switch Detect garage door open use Contact Switch block Use Combine block to combine light sensor and contact switch into one Frank Vahid, UC Riverside 12/32

13 Graphical Simulator User specifies and tests block design Java-based simulator User chooses between pallets Blocks added by dragging User is able to configure various blocks by clicking on switches Connections created by drawing lines between blocks Button When A is AND OR Light Sensor B is then the output is Combine Beeper Available eblocks Sensors Output Compute/Communications When Button Beeper A is AND B is OR then the output is Motion Combine Green/Red Sensor Light rst in Light Sensor Once Yes, Stays Yes Toggle Yes/No seconds Prolonger Hide this panel Advanced Mode Welcome to the eblocks Simulator! In this area, you ll find helpful hints on creating your own designs. Click and drag an eblock off of the Available eblocks panel to add it to your design. To connect two blocks, click and drag from an output port (colored circle) to an input port (gray circle). A connection can be destroyed by clicking on a connected port. To move a block around the workspace, click and drag its orange area. Blocks can be moved into the trash can to delete them. Green circles indicate that the port is sending a, red circles indicate that the port is sending a, yellow Circles indicate that the port is sending an error signal, and gray circles dete an input port. Frank Vahid, UC Riverside 13/32

14 Graphical Simulator User specifies and tests block design Java-based simulator User chooses between pallets Blocks added by dragging User is able to configure various blocks by clicking on switches Connections created by drawing lines between blocks User can create, experiment, test and configure design Button When A is AND OR Light Sensor B is then the output is Combine Beeper Welcome to the eblocks Simulator! In this area, you ll find helpful hints on creating your own designs. Available eblocks Sensors Output Compute/Communications When Button Beeper A is then the output is Motion Combine Green/Red Sensor Light rst in Light Sensor Once Yes, Stays Yes Toggle Yes/No seconds Prolonger Hide this panel Click and drag an eblock off of the Available eblocks panel to add it to your design. To connect two blocks, click and drag from an output port (colored circle) to an input port (gray circle). A connection can be destroyed by clicking on a connected port. To move a block around the workspace, click and drag its orange area. Blocks can be moved into the trash can to delete them. Green circles indicate that the port is sending a, red circles indicate that the port is sending a, yellow Circles indicate that the port is sending an error signal, and gray circles dete an input port. AND B is OR Advanced Mode Frank Vahid, UC Riverside 14/32

15 eblocks and Embedded Microprocessors Can greatly simplify coding Button / 1/0 Micro- Light Sensor processor Button Tripper / 1/0 Frank Vahid, UC Riverside 15/32

16 And w for something completely different... Warp processing 2001-present, supported by SRC, Intel, IBM, Freescale, Xilinx Ph.D. students Roman Lysecky Ph.D., June 2005, w Asst. Prof. at Univ. of Arizona Greg Stitt Ph.D. June 2007, w Asst. Prof. at Univ. of Florida, Gainseville Ann Gordon-Ross Ph.D. June 2007, w Asst. Prof. at Univ. of Florida, Gainseville Frank Vahid, UC Riverside 16/32

17 Circuits on FPGAs Can Sometimes Give Big Speedups C Code for FIR Filter for (i=0; i i < 128; i++) y y[i] += += c[i] c[i] * x[i] * x[i] Circuit for FIR Filter * * * * * * * * * * * * Processor Processor Processor FPGA 1000 s of instructions ~ 7 cycles Speedup > 100x Several thousand cycles Pipelined -- >500x Circuit parallelism/pipelining can yield big speedups Frank Vahid, UC Riverside 17/32

18 Dynamic Translation Motivated by commercial dynamic binary translation of early 2000s e.g., Transmeta Crusoe code morphing VLIW VLIW Binary Performance x86 Binary Binary Translation x86 VLIW FPGA Binary Binary Translation x86 VLIW FPGA Warp processing (Lysecky/Stitt/Vahid ): dynamically translate binary to circuits on FPGAs Frank Vahid, UC Riverside 18/32

19 Warp Processing Background 1 Initially, software binary loaded into instruction memory Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 FPGA On-chip CAD Frank Vahid, UC Riverside 19/32

20 Warp Processing Background 2 Microprocessor executes instructions in software binary Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 Time Energy FPGA On-chip CAD Frank Vahid, UC Riverside 20/32

21 Warp Processing Background 3 Profiler monitors instructions and detects critical regions in binary Profiler beqbeqbeqbeqbeqbeqbeqbeqbeqbeq addaddaddaddaddaddaddaddaddadd I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 Time Energy FPGA On-chip CAD Critical Loop Detected Frank Vahid, UC Riverside 21/32

22 Warp Processing Background 4 On-chip CAD reads in critical region Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 Time Energy FPGA On-chip CAD Frank Vahid, UC Riverside 22/32

23 Warp Processing Background 5 On-chip CAD decompiles critical region into control data flow graph (CDFG) FPGA Profiler I Mem D$ Dynamic On-chip CAD Part. Module (DPM) Decompilation surprisingly effective at recovering high-level program structures Stitt et al ICCAD 02, DAC 03, CODES/ISSS 05, ICCAD 05, FPGA 05, TODAES 06, TODAES 07 Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 reg3 := 0 reg4 := 0 Frank Vahid, UC Riverside 23/32 Time loop: reg4 := reg4 + mem[ reg2 + (reg3 << 1)] reg3 := reg3 + 1 if (reg3 < 10) goto loop ret reg4 Energy Recover loops, arrays, subroutines, etc. needed to synthesize good circuits

24 Warp Processing Background 6 On-chip CAD synthesizes decompiled CDFG to a custom (parallel) circuit Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 Time Energy FPGA Dynamic On-chip CAD Part. Module (DPM) reg3 := 0 reg4 := loop: reg4 := reg4 + mem[ reg2 + (reg3 << 1)] reg3 := reg3 + 1 if (reg3 < 10) goto loop ret reg4 Frank Vahid, UC Riverside 24/

25 Warp Processing Background 7 On-chip CAD maps circuit onto FPGA Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl reg1, reg3, 1 Add reg5, reg2, reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 Time Energy FPGA Dynamic On-chip CAD Part. Module (DPM) Lean place&route/fpga 10x faster CAD (Lysecky et al DAC 03, ISSS/CODES 03, DATE 04, DAC 04, DATE 05, FCCM 05, TODAES 06) Multi-core chips use 1 powerful core for CAD reg3 := 0 reg4 + := 0 + SM SM loop: reg4 := reg4 + mem[ reg2 CLB + (reg3 << 1)] reg3 := reg3 + 1 if SM (reg3 < 10) SM goto loop ret reg4 Frank Vahid, UC Riverside 25/32 SM SM CLB

26 Warp Processing Background 8 On-chip CAD replaces instructions in binary to use hardware, causing performance and energy to warp by an order of magnitude or more Profiler I Mem D$ Software Binary Mov reg3, 0 Mov reg4, 0 loop: Shl // instructions reg1, reg3, that 1 Add interact reg5, with reg2, FPGA reg1 Ld reg6, 0(reg5) Add reg4, reg4, reg6 Add reg3, reg3, 1 Beq reg3, 10, -5 Ret reg4 >10x speedups for some apps Time Time Energy Energy Software-only Warped FPGA Dynamic On-chip CAD Part. Module (DPM) SM reg3 := 0 reg4 + := 0 + SM SM loop: reg4 := reg4 + mem[ reg2 CLB + (reg3 << 1)] reg3 := reg3 + 1 if SM (reg3 < 10) SM goto loop SM CLB ret reg4 Frank Vahid, UC Riverside 26/

27 Challenge: Decompilation Requires aggressive decompilation to recover loops, arrays,..., from binaries Results: Competitive with synthesis from C Speedup FIR Filter Beamformer Viterbi Brev Url BITMNP01 IDCTRN01 High-level Binary-level PNTRCH01 Average Synthesis from C Code Synthesis after Decompiling Binary Example Cycles ClkFrq Time Area Cycles ClkFrq Time Area %Time Overhead %Area Overhead bit_correlator % 0% fir % 3% udiv % 0% prewitt % 58% mf % 0% moravec % -1% Avg: -1% 10% Frank Vahid, UC Riverside 27/32

28 Challenge: JIT Compile to FPGA Developed ultra-lean CAD heuristics for synthesis, placement, routing, and techlogy mapping; simultaneously developed CAD-oriented FPGA e.g., Our router (ROCR) 10x faster and 20x less memory, at cost of 30% longer critical path. Similar results for synth & placement (EDAA Outstanding Dissertation Award 2006) Xilinx ISE Riverside JIT FPGA tools 0.2 s 3.6MB 9.1 s 60 MB Riverside JIT FPGA tools on a 75MHz ARM7 1.4s 3.6MB Frank Vahid, UC Riverside 28/32

29 Experiments Benchmarks: Image processing, DSP, scientific computing Highly parallel examples to illustrate thread warping potential We created multithreaded versions Base architecture 4 ARM cores Focus on recurring applications (embedded) TW: FPGA running at whatever frequency determined by synthesis Multi-core 4 ARM MHz Thread Warping 4 ARM MHz + FPGA (synth freq) Compared to FPGA On-chip CAD Frank Vahid, UC Riverside 29/32

30 Speedup from Thread Warping Fir Prewitt Linear Moravec Wavelet Maxfilter 3DTrans N-body Avg. Geo. Mean 38 4-uP TW 8-uP 16-uP 32-uP 64-uP Average 130x speedup But, FPGA uses additional area 11x faster than 64-core system Simulation pessimistic, actual results likely better So we also compare to systems with 8 to 64 ARM11 ups FPGA size = ~36 ARM11s Frank Vahid, UC Riverside 30/32

31 Dynamic Enables Expandable Logic Concept RAM RAM Expandable RAM Logic System Warp tools detect detects amount RAM of FPGA, during invisibly start, adapt improves application performance to use less/more invisiblyhardware. DMA Cache Cache Profiler FPGA FPGA Warp Tools FPGA FPGA Expandable RAM up Expandable Logic Performance Frank Vahid, UC Riverside 31/32 Speedup Softw are 1 FPGA 2 FPGAs 3 FPGAs 4 FPGAs N-Body 3DTrans Prew itt Wavelet

32 Virtual Immersion eblocks: Enables customized sensor-based system design by n-experts May lead to...? Wood and nails of the sensor world Currently working with hearingimpaired, aging Warp processing (featured in this month s IEEE Computer) Enables large speedups on certain applications (e.g., image processing), user can expand hardware without changing software Frank Vahid, UC Riverside 32/32