Amarjeet Singh. January 30, 2012
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1 Amarjeet Singh January 30, 2012
2 Website updated - Lecture slides, audio from last class Assignment-2 How many of you have already finished it? Final deadline today Assignment-3 Due Friday You can use Dragon to program either xmega or EVK1100 over JTAG interface Should be fairly easy to do Demo for both the assignments next week You should program your board with the code of Assignment-2 using JTAG 2
3 Student presentations Will share the spreadsheet with everyone Go over both the papers in your topic Select one of the two papers that you will present by this weekend and put the name of paper in the spreadsheet Presentations will start after mid semester Post the schedule after you all have selected the papers Those who are not presenting need to submit 1 page summary on the same paper the same day in the class Each group need to submit one summary only You should also be starting on your Group project after mid semester More details on the group project by next week 3
4 What limits the sampling rate of ADC? How is propagation delay given for ADC block in xmega? What are things to consider when selecting a sensor to interface with your microcontroller? What is the function of voltage regulators? What are some common types of voltage regulators? Where and why are decoupling capacitors used? Where are why are pull up/down resistors used? Explain briefly the I2C protocol Why is it not suitable for peer to peer communication? 4
5 Four main signals: Master Out Slave In (MOSI) Master In Slave Out (MISO) Serial Clock (SCK) Chip Select (CS) Since there is a separate CS for each device on board, SPI does not scale up well in comparison with I2C MOSI: Generated by master, received by slave Also labeled as Serial Input (SI) or Serial Data In (SDI) MISO: Generated by slave, under control by the master Also labeled as Serial Output (SO) or Serial Data Out (SDO) Chip Select (Slave Select) generated using spare I/O of master 5
6 Master configures SCK with frequency less than or equal to maximum frequency supported by slave device (1-70 MHz) Master pulls the CS low Full duplex data transfer: Both master and slave contain shift registers: Master starts the transfer by writing to its SPI shift register As master transfers the byte to the slave on MOSI, slave transfers the contents of its shift register back to the master on MISO After 5 bits are transferred what is the state of TX Buffer? Both the write and the read performed simultaneously For write only operation, read byte is ignored For read only operation, a dummy byte is written to initiate slave transmission 6
7 Four modes of operation depending on clock polarity and clock phase Low clock polarity (CPOL = 0): SCK is low when idle and toggles high during transfer High clock polarity (CPOL = 1): Reverse of low clock polarity Clock phase zero (CPHA = 0): MOSI and MISO are valid on rising/falling edge of SCK for low/high clock polarity respectively Clock phase zero and low clock polarity How does the timing diagram change for CPOL = 1? 7
8 Clock phase one (CPHA = 1): MOSI and MISO are valid on falling/rising edge of SCK for low/high clock polarity respectively Clock phase one and low clock polarity SPI Mode 0: CPOL = 0, CPHA = 0; SPI Mode 1: CPOL = 0, CPHA = 1; SPI Mode 2: CPOL = 1, CPHA = 0; SPI Mode 3: CPOL = 1, CPHA = 1 Most common modes: SPI Mode 0 and 3 (data sampled on positive clock edge) 8
9 9
10 Atmel AT25DF641: 64 Mbit Serial Flash Memory Supports SPI mode 0 and 3 Works at 75 MHz Low power dissipation: 5 ma (typical) active read current 100,000 Program/Erase cycles 10
11 Atmel AT25DF641: 64 Mbit Serial Flash Memory Supports SPI mode 0 and 3 Works at 75 MHz Low power dissipation: 5 ma (typical) active read current 100,000 Program/Erase cycles Which SPI mode does this waveform represent? 11
12 4 lines required: MOSI, MISO, SCK, CS Allows simultaneous read and write making it more efficient Higher data rate: Up to 4 Mbps or more Multiple devices can be connected simultaneously but with only a single master Device selection based on Chip Select: Implies an extra pin for each device on the master chip More efficient in point to point connection: Why? No acknowledgement mechanism to confirm data receipt 12
13 SPI more suited for applications that are thought as data streams (as opposed to reading/writing address locations in slave devices) Gains efficiency in applications that take advantage of its duplex capability e.g. codec (that requires sending samples in and out) Due to lack of built-in device addressing, SPI requires more hardware resources when more than one slave device is attached But SPI more efficient and simpler in point-to-point links Cost and complexity of I2C does not scale with number of devices With its collision detection and acknowledgement scheme, I2C is a true multi-master bus 13
14 4 internal Chip Selects supported What external device can be used to control 16 slave devices 14
15 Absolute maximum ratings (AVR32) Found in the Section Electrical Characteristics in the datasheet Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device and hence should be avoided 15
16 16
17 V DDCORE represents core operating voltage Max value of V IL denotes highest value where the pin is guaranteed to be read as 0 Min value of V IH denotes lowest value where the pin is guaranteed to be read as 1 When a pin is output high, it will be the source of current Some devices may have an upper limit on total aggregate current as well on a group of pins e.g. Sum of all I OH for ports C0- C5, D0-D4, ADC7, RESET should not exceed 150 ma (ATmega) When a pin is output low, it will sink current Negative value since the current is going in Similar to I OH, some devices have upper limit on aggregate I OL as well e.g. sum of I OL on ports C0-C5, ADC6, ADC7 should not exceed 100 ma (ATmega) Value of pull up resistors based upon the current ratings 17
18 Internal voltage regulator Can supply voltage to other devices on board With limited current capabilities Decoupling requirements also typically specified ADC voltage input range also specified 18
19 Threshold for logic high and logic low vary across devices For an input device to recognize the signal as high or low, the output device must provide the signal appropriately Interfacing AT25DF641 Flash with ATMEGA328P Absolute Maximum Ratings Operating Range 19
20 Interfacing AT25DF641 Flash with ATMEGA328P Common DC Characteristics 20
21 Power consumption in different modes of operation V DDIO = 3.3 V V DDCORE = 1.8 V IOs configured in input, pull-up mode 21
22 22
23 UART: Universal Asynchronous Receiver Transmitter Translates data between parallel and serial form Universal designation indicates that the data format and transmission speeds are configurable Actual electric signaling level and methods are typically handled by a driver circuit external to UART USART: UART that can also communicate synchronously I/O interface converting parallel data from microprocessor for serial communication and serial data on line to parallel for microcontroller What typical hardware logic will be useful for serial/parallel conversion? 23
24 No common clock but still need a way to detect bit boundaries: e.g. How do we differentiate between 00 and 000 A clock transmitted along with data stream Useful where we need to send one character at a time and the interval of time between each byte may vary Typical transmission format is 1 start bit in the beginning, 0/1 parity bit after the data and 1 or 2 stop bits in the end of each character Receiver synchronizes its clock upon receiving the start bit and samples the data (7 or 8 bits) If stop bits are received in correct sequence, receiver assumes successful reception else an error is declared If a UART is receiving 1 character (8 bits) per second transmitted with 1 parity and 2 stop bits, what is the bit rate on serial output? 24
25 Multiple standards for voltage signaling RS-232 RS-485 Some signaling schemes do not use electrical wires Infrared Signal (IrDA) Bluetooth (in Serial Port Profile SPP) Error detection using parity bits A match of parity bit implies the transmission was correct What are different types of parity? What is the maximum number of bit errors that we can detect with 1-bit parity? CRC algorithm for more complex bit error correction and detection 25
26 Recommended Standard 232 Works for cable lengths up to 25 meters and data rates up to 38.4 kbps First introduced in 1962 RS-232 compatible serial port was a standard feature for serial communication with many external devices attached with computers in 1990s Replaced with USB these days Originally designed for connecting Data Terminal Equipment (DTE) to Data Communication Equipment (DCE) DTE has a pin based connector DCE has a hole based connector Either uses a 25-pin or 9-pin connector 9-pin connector more common 26
27 Standard signals Tx (3), Rx (2), RTS (7), CTS (8), DTR (4), DCE Ready (6), Data Carrier Detect (1), Ring Indicator (9), Signal Ground (5) Many of these signals are intended for modem control To form a simple signal between computer and a terminal, only Tx, Rx and SG are required Do you use any device that has RS-232 connection? 27
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