Terasic DE0 Field Programmable Gate Array (FPGA) Development Board
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1 Lecture FPGA-01 DE0 FPGA Development Board and Quartus II 9.1 FPGA Design Software Terasic DE0 Field Programmable Gate Array (FPGA) Development Board 1
2 May 16, Layout and Components of DE0 May 16, Block Diagram of the DE0 Board Cyclone III 3C16 FPGA:15,408 Les, 4 PLLs, 346 I/O pins Normally high, generate active-low pulse when pressed NOR flash SPI and SD 1-bit modes Logic 0/1 when in the Down/Up position 16 x 2 Character LCD EEPROM Altera EPM240 CPLD 2
3 May 16, DE0 Installation Step 1: Install the Altera Design Software on the host computer. Download the software: - Quartus II: the primary FPGA development tool - Nios II: soft-core embedded processor - ModelSim-Altera: Simulation tool May 16, DE0 Installation (Cont.) Step 2: Install the USB Blaster Plug in the power cable. Use the USB cable to connect the USB connector on the DE0 board to a USB port on a computer Recognize the new hardware connected Specify the path for the USB Blaster driver Select appropriate driver. (C:\altera\91\quartus\drivers\usb-blaster) - 4. Install USB Blast driver. (C:\altera\91\quartus\drivers\usb-blaster\x32) 3
4 May 16, Power-Up the DE0 Board The DE0 board comes with a preloaded configuration bit stream to demonstrate some feature of the board. All user LEDs are flashing. All 7-segment displays are cycling through 0 to F. The VGA monitor displays the image as shown in the right-hand side: May 16, DE0 Control Panel The DE0 board comes with a Control Panel facility. (Start the executable DE0_ControlPanel.exe) Allow users to access various components on the board from a host computer. Connect the host computer with the DE0 board through a USB connection. Verify the functionality of components on the board. 4
5 May 16, DE0 Control Panel (Cont.) The control codes that perform the control functions Is implemented in the FPGA board, and Communicates with the Control Panel window on the host computer. Host Host computer: Control Panel window USB Blaster USB cable DE0 May 16, Configuring the Cyclone III FPGA The DE0 board contains a serial EEPROM chip (i.e., the EPCS4 device) that stores configuration data for the Cyclone III FPGA. The configuration data is automatically loaded from the EEPROM chip into the FPGA once the power is applied to the board. With Quartus II, it is possible to reprogram the FPGA and to change the non-volatile data in the EEPROM chip. - JTAG (Joint Test Action Group) programming: Download the configuration to FPGA directly, but the configuration is lost when the power is off. - AS (Active Serial) programming: Download the configuration into the EEPROM chip, and the configuration is retained when the power is off. When the power is on, data is loaded from the EEPROM. 5
6 May 16, Configuring the FPGA in JTAG Mode Download the.sof (SRAM Object File) file by the programmer of Quartus II May 16, Configuring the FPGA in JTAG Mode (Cont.) The steps to program SRAM Object File (.sof) into the FPGA device on the DE0 board are as follows: Step 1: Power on DE0 board with SW11 to RUN mode and connect it to the host. Step 2: Open Quartus II, and choose Tools Programmer Step 3: Click Hardware Setup and then Select USB Blaster Step 4: Click Add File to select the.sof file in JTAG mode, and then click Start to program it. 6
7 May 16, Configuring the EPCS in AS Mode Download the.pof (Programmer Object File) file by the programmer of Quartus II May 16, Configuring the EPCS4 in AS Mode (Cont.) The steps to program Programmer Object File (.pof) into the EPCS4 device on the DE0 board are as follows: Step 1: Power on DE0 board with SW11 to PROG mode and connect it to the host. Step 2: Open Quartus II, and choose Tools Programmer Step 3: Click Hardware Setup and then Select USB Blaster Step 4: Click Add File to select the.pof file in Active Serial Programming mode, and then click Start to program it. (Remember to select Add Device EPCS4 ) Setting for generating.pof file: Assignments Settings Device Device and Pin Options Configuration Active Serial, EPCS4, and check Use configuration device & Generate compressed bitstreams. 7
8 May 16, Pushbutton and Slide Switches Pin number Pin number 3 Pushbutton switches: Not pressed Logic High Pressed Logic Low 10 Slide switches (Sliders): Up Logic High Down Logic Low May 16, LEDs Pin number 10 LEDs Opuput high LED on Output low LED off 8
9 May 16, Segment Displays Pin number (active-low) Quartus II 9.1 FPGA Design Software 9
10 May 16, Simplified Design Flow of Quartus II Design entry ( block editor or text editor) Block editor: Block Diagram/Schematic File (.bdf) Text editor: Verilog HDL (.v) or VHDL (.vhd) Specify the designed circuit Download to FPGA Create projects and assign target devices (New Project Wizard) Compilation and Fitting Determine the placement and choose routing wires in the chip Simulation (Vector Wave File (.vwf) ) Compilation and Fitting Pin Assignments Timing simulation: Verify functional correctness and timing issues. Functional simulation: Verify functional correctness without considering timing issues. May 16, Schematic Design with Quartus II Example: When the BUTTON0 is pressed, LEDG0 shows the ANDed result of SW0 and SW1 and LEDG1 shows the ORed result of SW0 and SW1. Step 1: Start a new project Select File New Project Wizard - Working directory: Class01 - Project name: Class01 - Top-level design entry: Class01 Family & Device Settings - Device family: Cyclone III - Available device: EP3C16F484C6 EDA Tool Settings - Leave it alone at the moment 10
11 May 16, Schematic Design with Quartus II (Cont.) Step 2: Design entry using the graphic editor Select File New Block Diagram/Schematic File (.bdf) Save as Class01.bdf (check Add file to current project ) Select primitives of Symbol Tool to add - Three input pins A, B, and C, two output pins X and Y - One AND gate, one OR gate, two tri-state buffers, and one NOT gate. Select Orthogonal Node Tool to connect the nodes. Select Start Compilation to compile the circuit May 16, Schematic Design with Quartus II (Cont.) Step 3: Simulation with Vector Waveform File (.vwf) Select File New Vector Waveform File (.vwf) Save as Class01.vwf (check Add file to current project ) Select Edit Insert Insert Node or Bus Node Finder (Filter: Pins: all) to add input/output pins into the simulation. Select Edit End Time and select Edit Grid Size to configure the simulation period to 500ns and count period. - A: count value, binary, start value 0, count every 50ns, multiplied by 1. - B: count value, binary, start value 0, count every 50ns, start time 0ns, multiplied by 2. - C: forcing high or forcing low. Select Start Simulation to simulate the circuit. Functional simulation - Select Assignments Settings Simulator Settings to set Simulation mode as Functional. - Select Processing Generate Functional Simulation Netlist - Select Start Simulation to simulate the circuit. 11
12 May 16, Schematic Design with Quartus II (Cont.) Step 3: Simulation with Vector Waveform File (.vwf) Select Assignments Device to configure the board settings. - Set Family as Cyclone III and Device as EP3C16F484C6 - Select Device and Pin Options Select and set Unused Pins as As input tri-stated and Select Configuration to set configuration scheme as Active Serial and configuration device as EPCS4 Select Assignments Pins to activate the Pin Planner. Select Start Compilation to compile the circuit with circuit assignment. Select Tools Programmer to download the.soft file to the FPGA board for testing. May 16, Pin Assignment Backup and Export Backup and export pin assignments You can backup the ProjectName.pin file under your project directory. You can export the pin assignment by exporting it as an.csv file Under Pin Planner, Select File Export - 2. Use EXCEL or any text editor to open this file
13 May 16, Lab 01 Part 1 - Simulation Use the block editor (Block Diagram/Schematic File:.bdf) to design a NAND gate with one output pin F and two input pin A and B. Then use Vector Waveform File (.vwf) to simulate the results. - A: count value, binary, start value 0, simulation period=4us, start time: 0, advanced by 1 every 100ns - B: count value, binary, start value 0, simulation period=4us, start time: 0, advanced by 1 every 200ns Map A to SW0, B to SW1, and F to LED0 of DE0, and program it. May 16, Part 2 - Transferring the following Design to the Target FPGA Use two slides (SW1-SW0) as the binary input value. - The corresponding LED (LEDG0-3) is on when it is selected by the binary input. Other LEDs are off. E.g., 10 (SW1-SW0) lights LEDG2. 13
14 May 16, Pushbutton and Slide Switches Pin number Pin number 3 Pushbutton switches: Not pressed Logic High Pressed Logic Low 10 Slide switches (Sliders): Up Logic High Down Logic May 16, LEDs Pin number 10 LEDs Opuput high LED on Output low LED off 14
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