SKW22 Serial-Wi-Fi Module Datasheet

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1 SKW22 Serial-Wi-Fi Module Datasheet Name: b/g Serial WiFi Module Model NO.: SKW22 Revision: 2.0 Revision History: Revision Description Approved Date 1.0 George External PA George Skylab M&C Technology Co., Ltd. Address: Room.801, Bldg.211, Terra Industrial Park, Futian District, Shenzhen Phone: (Sales Support) Phone: (Technical Support) Fax: Website:

2 1 Overview 1.1 Document Overview This document describes the SKW22 Low Power module hardware specification. The SKW22 based modules provide cost effective, low power, and flexible platform to add Wi-Fi connectivity. for embedded devices for a variety of applicatio, such as wireless seors and thermostats. It com- bines ARM7-based processors with an RF traceiver, MAC, security, & PHY functio, FLASH and SRAM, onboard and off module certified antenna optio, and various RF front end optio for end customer range needs in order to provide a WiFi and regulatory certified IEEE radio with concur- rent application processing services for variety of applicatio, while leverage existing wire- less network infrastructures. 1.2 Product Overview Compliant with IEEE and regulatory domai: DSSS modulation for data rate of 1 Mb/s and 2 Mb/s; CCK modulation rates of 5.5 and 11 Mb/s. Compatible with IEEE b. Supports short preamble and short slot times. WiFi Certified Solution o Supports i security WPA - Enterprise, Personal WPA2 - Enterprise, Personal Vendor EAP Type(s) EAP-TTLS/MSCHAPv2, PEAPv0/EAP-MSCHAPv2, PEAPv1/EAP- GTC, EAP-FAST, EAP-TLS High-throughput hardware AES and RC4 encryption/decryption engines. RoHS and CE compliant FCC/IC Certified Fully compliant with EU & meets the R&TTE Directive for Radio Spectrum Japan Radio Type Approval (i.e. TELEC) pre-scan compliant Dual ARM7 Processor Platform: 1 st ARM7 processor (WLAN CPU) for WLAN software 2 nd ARM7 (APP CPU) for networking software Based on Advanced Microprocessor Bus Architecture (AMBA) system: o AMBA High-Speed Bus (AHB). o AMBA Peripheral Bus (APB). On-chip WLAN boot code located in dedicated boot ROM. Interfaces: One general-purpose slave SPI interfaces for external sen- sors, memory, or external CPU interface; one interface may be configured as a high-speed Slave-only. UART interfaces.

Up to 16 configure able general purpose I/Os. Single 3.3V supply option o I/O supply voltage 1.8 ~ 3.3V option One PWM output Two 10-bit ADC channels, aggregate sample rate 32 ks/s.

3 Up to 16 configure able general purpose I/Os. Single 3.3V supply option o I/O supply voltage 1.8 ~ 3.3V option One PWM output Two 10-bit ADC channels, aggregate sample rate 32 ks/s. Two alarm inputs to asynchronously awaken the chip. Support of up to two control outputs for power supply and seors. Embedded RTC (Real Time Clock) can run directly from battery. Power supply monitoring capability. Low-power mode operation. Sleep, Deep Sleep, and Standby 27(L) x 19.8(W) x 2.8(H) mm small dimeion SKW22

4 2 Pin-out and Signal Description 2.1 SKW22 Device Pin-out Diagram (Module top view) Figure 3-1: SKW22 Device Pin-out Diagram (Module top view) SKW22 Module Pi Description Voltage Internal Bias after Signal Pi Name Description Domain hardware reset State 1 GND 0V Not Applicable Analog port Ground

5 2 ALARM1 VBAT Pull-down (See Note 1) Digital Input Embedded Real Time Clock Wake Up Input 1 3 ALARM2 VBAT Pull-down (See Note Embedded Real Time Clock Wake Up Digital Input 1) Input 2 4 GND 0V Not Applicable Analog port Ground 5 ADC2 VDD18 Not Applicable Analog General Analog to Digital Converter 2 6 ADC1 VDD1 Not Applicable Analog General Analog to Digital Converter 1 7 VBAT VBAT Not Applicable Analog port Embedded Real Time Clock Power Supply 8 GND 0V Not Applicable Analog port Ground 9 GPO21_11MHZ VDDIO Pull-down Digital Input Internal Clock Circuitry Test Point / General Purpose 10 GPO20_22MHZ VDDIO Pull-down Digital Input Internal Clock Circuitry Test Point / General Purpose DC_DC_CNTL VBAT Not Applicable Digital VIN_3V3 Regulator Control GND 0V Not Applicable Analog port Ground 13 VOUT_1V8 VIN_3V Not Applicable Analog port Internal 1.8V Vout 14 VDDIO VDDIO Not Applicable Analog port All I/O voltage domain (can be tied to VIN_3V3 or tied to HOST I/O supply) 15 VIN_3V3 VIN_3V3 Not Applicable Analog port Single Supply Port 16 SSPI_DIN VDDIO Pull-down (See Note 1) Digital Input SPI Slave Receive Data Input from the HOST 17 SSPI_CLK VDDIO Pull-up (See Note 1) Digital Inpu SPI Slave Clock Input from the HOST 18 SSPI_DOUT VDDIO Pull-up (See Note 1) Digital Input SPI Slave Tramit Data to the HOST 19 SSPI_CS VDDIO Pull-up (See Note 1) Digital Inpu SPI Slave Chip Select Input from the HOST UART1_CTS / GPIO26 UART1_RTS / GPIO27/Program mode VDDIO VDDIO Pull-down Pull-down(See Note 2) 22 UART0_TX/GPIO1 VDDIO Pull-down 23 UART0_RTS/GPIO25 VDDIO Pull-down 24 UART0_RX/GPIO0 VDDIO Pull-down 25 UART0_CTS/GPIO24 VDDIO Pull-down 26 GPO31_LED2 VDDIO Pull-down Digital Digital Digital Digital Digital Digital Digital Universal Asynchronous Receiver Tramitter 1 Clear to Send Input (See Note 6) / General Purpose Input Universal Asynchronous Receiver Tramitter 1 Re- quest to Send (See Note 6) / General Pur- pose Input /Programming mode Universal Asynchronous Receiver Tramitter 0 Tramitter / General Purpose Input Universal Asynchronous Receiver Tramitter 0 Request to Send (See Note 6) / General Purpose Input Universal Asynchronous Receiver Tramitter 0 Receive Input / General Purpose Input Universal Asynchronous Receiver Tramitter 0 Clear to Send Input (See Note 6) / General Purpose Input Light Emitting Diode Driver / General Purpose Input

6 27 GPIO30_LED1 VDDIO Pull-down 28 PWM/WPS VDDIO Pull-down 29 GPIO28 VDDIO Pull-down Digital Digital Input / Digital Input / Light Emitting Diode Driver / General Purpose Input General Purpose Input General Purpose Input 30 EXT_RESETn(See Note 5) VDDIO Pull-up Digital Open Drain Input / 31 GND 0V Not Applicable Analog port Ground 32 RF 0V Not Applicable RF port Module Hardware Reset Input and Power Supply Reset Antenna 33 GND 0V Not Applicable Analog port Ground Notes: Table 2-1: Pi Description 1. These pi have onboard hardware configured pull-ups/dow and cannot be changed by software. 2. If UART1_RTS is high during boot, then the WLAN will wait for Flash download via UART0. For develop- ment purposes, route this pin to a test point on the board so it can be pulled up to VIN_3V3. 3. EXT_RESETn is a active low signal. It is an output during power up, the EXT_RESETn signal does not clear the RTC RAM or the SRAM. 4. CTS and RTS signals indicate it is clear to send or ready to send when they are LOW. If signals are high, indicates device is not ready.

7 2.2 Power Supply In this section, diagrams are shown for various application power supply connection. This connection applies for desig (typically battery operated) using SKW22 module and want to utilize standby (lowest current coumption) state of the module. In this connection it is important to note the following: 1) VDDIO power should be OFF during this state. Recommendation is to use DC_DC_CNTL to also control the unit supplying the voltage to VDDIO 2) Input voltage to VBAT must always be ON to keep the RTC powered so that the 32KHz crystal is running

9 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Conditio beyond those cited in Table 4-1 may cause permanent damage to the SKW22, and must be avoided. Parameter Symbol Minimum Typical Maximum Unit Storage TST ºC temperature RTC Power Supply Vbat V I/O Supply voltage VDDIO V Single Supply Port VIN_3V V 3.2 Operating Conditio Table 3-1: Absolute Maximum Ratings Parameter Symbol Minimum Typical Maximum Unit Extended temp. range TA ºC RTC Power Supply Vbat V I/O Supply voltage VDDIO V Single Supply Port VIN_3V V 3.3 Internal 1.8V regulator Table 3-2: Operating Conditio VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC fosc=3.0mhz Parameter Symbol Minimum Typical Maximum Unit Voltage VOUT_1V8 1.8 V Maximum IVOUT_1V ma Current Oscillation Frequency fosc MHz Table 3-3: Internal 1.8V Regulator

10 3.4 I/O DC Specificatio Digital Input Specificatio Parameter Symbol Minimum Typical Maximum Unit Input Low Voltage VIL * V VDDIO Input High Voltage VIH 0.8* VDDIO VDDIO V Table 3-4: Digital Input Parameters RTC Input Specificatio (with Schmitt Trigger) Parameter Symbol Mininum Typical Maximum Unit Note I/O Supply Voltage VDDRTC 1.2 Vbat V Input Low Voltage VIL *VDDRTC V Input High Voltage VIH 0.8*VDDRTC VDDRTC V Schmitt trig. Low to High threshold point Schmitt trig. High to Low threshold point Input Leakage Current VT+ 0.57*VDDRTC 0.68*VDDRTC V VT- 0.27*VDDRTC 0.35*VDDRTC V IL 260 pa Table 3-5: RTC Input Parameters RTC Specificatio Parameter Symbol Mininum Typical Maximum Unit Note I/O Supply VDDRTC 1.2 Vbat V Voltage Low Voltage VOL V High VOH 0.8*VDDRTC VDDRTC V Voltage rise time ttlh pf load fall time tthl pf load

11 Input Leakage Current IL 730 pa 3.5 Power Coumption Table 3-6: RTC Parameters Test Conditio: VDD33=VDDIO=Vbat=3.3V Temp=25ºC System state Standby Deep Sleep (SKW22) Receive (SKW22; -81 dbm RX 11Mb/Sec. Tramit (SKW22; +18 dbm at antenna 11Mb/Sec.) Current (Typ.) 7uA 200uA 140 ma 250 ma 3.6 Radio Parameters Table 3-7: Power Coumption in Different States Test Conditio: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC; 100-byte packet Parameter Minimum Typical Maximum Unit Notes RF Frequency MHz range Radio bit rate 1 11 Mbps Ch 14 max is 2 Mbps TX/RX specification for SKW22 power (average) 8 dbm Modulated signal at antenna port; 11Mb/Sec. Spectrum Mask dbr Modulated signal at antenna port F0 +/- 11 MHz Offset >= 22 MHz Receive Seitivity at antenna port dbm 11 Mbps CCK, 8% PER Mbps CCK, 8% PER Mbps QPSK, 8% PER Mbps BPSK, 8% PER

12 Spectrum Mask dbr Modulated signal at antenna port F0 +/- 11 MHz Offset >= 22 MHz Receive Seitivity at antenna port dbm 11 Mbps CCK, 8% PER Mbps CCK, 8% PER Mbps QPSK, 8% PER Mbps BPSK, 8% PER 3.7 ADC Parameters Table 3-8: Radio Parameters Test Conditio: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC Parameter Minimum Typical Maximum Unit Notes ADC Resolution Bits ADC Sample Freq ksps ADC input Clock Freq ADC Full Scale Voltage khz - VOUT_1V8 VOUT_1V8 V Reference =VOUT_1V Reference = bandgap Measuring Vbat Conversion Time 32 Clocks Based on internally gen- erated 1MHz or KHz Clocks ADC Integral -2-2 LSB Non-Linearity (INL) ADC Differential non-linearity (DNL) -1-1 LSB AVDD Power µa Supply current(operational) ADC Offset Error mv ADC Gain Error mv

13 Settling Time - 1 µs Input resistance MOhm Input Capacitance pf Bandgap Voltage (Vref) (T = 25ºC) V Table 3-9: ADC Parameters 3.8 SPI Interface Timing Test Conditio: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC Motorola SPI, clock polarity SPO = 0, clock phase SPH = 0 Figure 3-1: timing diagram, Master mode, SPO=SPH=0. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of Select line and first rising 1 edge of SPI clock Delay in Master asserting TX line after falling edge of Select line Time before rising edge of SPI clock by which received data must be ready Time for which received data must be stable after rising edge of SPI clock Time for which the Select line will be held after the sampling edge 1 for the final bit to be traferred 2 core SPI + 3 ec MSPI clock period mixed 30 ec 10 ec MSPI clock period

14 DATASHEET SKW22 Table 3-10: timing parameters, Master mode, SPO=SPH=0. Figure 3-2: timing diagram, Slave mode, SPO=SPH=0. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of Select line and first rising edge of SPI clock. Delay in Slave asserting TX line after falling edge of SPI clock, or the first bit after falling edge of the Select line. Time before rising edge of SPI clock by which received data must be ready Time for which received data must be stable after rising edge of SPI clock Time for which the Select line will be held after the sampling edge for the final bit to be traferred 4 core SPI core SPI clock periods core SPI core SPI + 14 mixed mixed mixed mixed

15 Table 3-11: timing parameters, Slave mode, SPO=SPH= Motorola SPI, clock polarity SPO = 0, clock phase SPH = 1 Figure 3-3: timing diagram, Master, SPO=0, SPH=1. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of select line and first rising edge of SPI clock. Delay in Master asserting TX line after rising edge of SPI clock. Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred MSPI clock period MSPI clock period

16 DATASHEET SKW22 Table 3-12: timing parameters, Master mode; SPO=0, SPH=1. Figure 3-4: timing diagram, Slave, SPO=0, SPH=1. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of select line and first rising edge of SPI clock. Delay in Slave asserting TX line after rising edge of SPI clock. Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred core SPI core SPI core SPI + 14 mixed mixed mixed

17 Table 3-13: timing parameters, Slave mode, SPO=0, SPH= Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0 Figure 3-5: timing diagram, Master mode, SPO=1, SPH=0. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of select line and first falling 1 edge of SPI clock. Delay in Master asserting TX line after falling edge of Select line. Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred. 2 core SPI MSPI clock period mixed MSPI clock period

18 DATASHEET SKW22 Table 3-14: timing parameters, Master mode, SPO=1, SPH=0. Figure 3-6: timing diagram, Slave mode, SPO=1, SPH=0. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of Select line and first falling edge of SPI clock. Delay in Slave asserting TX line after rising edge of SPI clock, or the first bit after falling edge of the Select line. Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred. 4 core SPI core SPI core SPI core SPI + 14 Mixed Mixed Mixed MSPI clock period

19 Table 3-15: timing parameters, Slave mode, SPO=1, SPH= Motorola SPI, clock polarity SPO = 1, clock phase SPH = 1 Figure 3-7: timing diagram, Master mode, SPO=SPH=1. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of select line and first falling edge of SPI clock. Delay in Master asserting TX line after falling edge of SPI clock. Time before rising edge of SPI clock by which received data must be ready. Time for which received data must be stable after rising edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred MSPI clock period MSPI clock period

20 DATASHEET SKW22 Table 3-16: timing parameters, Master mode, SPO=SPH=1. Figure 3-8: timing diagram, Slave mode, SPO=SPH=1. Parameter Description Minimum Maximum Unit tssetup ttxddelay trxdsetup trxdhold tsshold Minimum time between falling edge of select line and first falling edge of SPI clock. Delay in Slave asserting TX line after falling edge of SPI clock. Time before rising edge of SPI clock by which received data must be ready. Time for which received data must be stable after rising edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be traferred. Table 3-17: timing parameters, Master mode, SPO=SPH= core SPI core SPI core SPI + 14 Mixed Mixed Mixed

21 4 Package and Layout Guidelines 4.1 SKW22 Recommended PCB Footprint and Dimeio Figure 4-1: PCB Footprint and Dimeio 4.2 Surface Mount Assembly

Recommended reflow parameters. 2~4 ᄚ 60 to 120 seconds 180 to 200 ᄚ C 230 to 240 ᄚC 20 to 40 seconds Note: 1.

22 The reflow profile 1 is shown in Figure 5-8. Recommended reflow parameters are summarized in Table 5-1. Figure 4-2: Reflow temperature profile. PreHeat Temperature Ramp up rate for (A) 2 Pre-heat time (B) 3 Pre-heat ending temperature (C) 4 Heating 5 Peak Temperature range (D) Melting time that is the time over 220 ᄚC (E) Table 4-1: Recommended reflow parameters. 2~4 ᄚ 60 to 120 seconds 180 to 200 ᄚ C 230 to 240 ᄚC 20 to 40 seconds Note: 1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the conditio of the parts and boards, and the specificatio of the reflow furnace. 2. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the solder paste. 3. If the preheat is iufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time. 4. If the temperature is too low, non-melting tends to be caused in the area with large heat ca- pacity after reflow. 5. Be careful about sudden rise in temperature as it may worsen the slump of solder paste. 6. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining strength at times.

GS1500M b/g/n LOW-POWER WI-FI MODULE

GS1500M b/g/n LOW-POWER WI-FI MODULE GS1500M 802.11 b/g/n LOW-POWER WI-FI MODULE DATA SHEET Reference: Version: GS1500M-DS SP-1.4 Date: November 2014 Information in this document is provided in connection with GainSpan products. No license,