Techniques for Optimizing Performance and Energy Consumption: Results of a Case Study on an ARM9 Platform

Transcription

1 Techniques for Optimizing Performance and Energy Consumption: Results of a Case Study on an ARM9 Platform BL Standard IC s, PL Microcontrollers October 2007

2 Outline LPC3180 Description What makes this low power Measurements using EEMBC energy bench 2

3 LPC3180 ARM9-based microcontroller built on 90nm ARM926EJ-S CPU core Separate 32Kbyte instruction and data caches Vector Floating Point (VFP9) coprocessor Operating range 13MHz to 20MHz at 0.9 V 20 MHz to 208 MHz at 1.1 V. 3

4 LPC3180 Block diagram 4

5 What makes the LPC3180 Low power Intrinsic features 90nm low power process Minimized switching losses 0.5*C load *V 2 *Fclk Low voltage operation volts Architectural Clock gating Minimized bridge latency Memories are not clocked until accessed VDD PMOS NMOS Cross conduction current Charge/discharge current C Load 5

6 Vector Floating Point Unit Fully compliant with ANSI/IEEE STD Coprocessor provides full support for single-precision and double precision add, subtract, multiply, divide, and multiply accumulate operations. No assembly needed Floating-point libraries and compile options ARM Real View Developer Suite (RVDS) ARM Developer Suite (ADS) Real View Developer Kit for NXP IAR Embedded Workbench for ARM GCC

7 Benefits of VFP Turned on/off via software through a control register With the clocks disabled, no dynamic power consumed Many clock cycles saved Increases performance by a factor of about 5 with an approximately 14% increase in power consumption VFP9 is fully clock gated. Many microcontrollers don t have a HW floating-point User is forced to emulate the instructions using special software libraries that require significantly more processor cycles and power consumption

8 External Memory Interface Features Memory subsystem and software design choices can have significant impact on power consumption Memory types Code partitioning Use of system features that save power LPC3180 external memory interface support DDR and SDR SDRAM Single-level and multi-level NAND flash devices (although flash not be used for the case study being presented here)

9 Typical Power Consumption of Memory Memory Type Size (Mb) Bit Width Frequency (MHz) Voltage (V) Current (ma) SDRAM Power (mw) Mobile SDRAM DDR * Mobile SDRAM * Demonstrating relative comparison Actual system performance varies based on how memories are used Doesn t include power dissipated in processor s pads due to capacitive loading from board layout and memories

10 Benefits of Internal Memory Most microcontrollers have internal SRAM and flash memory Consumes much lower power than external LPC3180 has 64K SRAM that runs at half the processor frequency 72 µw/mhz, which is 7.5 ma at 104 MHz of constant access Interfaces to internal memories have automatic clock gating and are only clocked when an access occurs Run code in internal SRAM when possible Partition code so frequently active processes are located in the internal memory bank and seldom used routines are placed in external memory

11 Phytec Core Module Housing LPC3180 Board instrumented to measure current and voltage for each supply input Phytec core modules have jumpers to the processor where series resistors can be inserted to measure the current

12 Power Take Offs for V and I Measurements Boards designed to connect 0.1 inch header pins and include a mini USB cable connection For connecting to NI DAQ USB-6251 Mini USB cables Two conductors for current sense Two conductors for voltage sense

13 The Standard Benchmark suites targeting several application areas Automotive: Powertrain, industrial, general purpose Consumer: Digital imaging (printers, digital cameras) Digital entertainment: Multimedia Java: Mobile phones Networking: Routing and testing network packets Office Automation: Text and image processing for printers Telecom: Modem and xdsl related algorithms

14 EEMBC Energy Methodology Consortium work over Applies to all EEMBC benchmarks Ties performance with energy consumption Specified for silicon devices which can be certified under current procedures Specific device information is disclosed according to EEMBC rules Non-intrusive methodology

15 Available Data Two figures of merit Maximum power consumption Typical power consumption Maximum power consumption used in system design Typical power is more relevant to battery life, operating costs, heat dispersion, etc. Typical power doing what, however?

16 Challenges of Hardware-Based Power Measurements What system components to measure? CPU core Caches Integrated peripheral controllers Which benchmarks to use? Does it matter? How to measure? Equipment Time consuming Sensitive to environment

17 The Importance of Benchmark Variety Processors are complex enough that the power can change based on benchmark Processors have multiple resources affected by different benchmarks and even different datasets Even the coding of the instructions and register selection may affect power The following slides present sample academic information that was used while creating the methodology

18 EEMBC Methodology Highlights Calculate average energy per iteration Benchmark and workload specific Use affordable hardware (NI DAQ) Multiple unaliased sampling frequencies Adaptive statistical process Specifies ambient temperature to avoid need of complex hardware. Alternatives considered: Measure case temperature Measure junction temperature

19 EnergyBench Test Conditions Connect to the various power planes Core IO Consistent 5% variance between runs Resistor contributes 1% DAQ board contributes 1% Maintain ambient room temperature (70 degrees F) Vendor must disclose cooling method (e.g. heat-sink dimensions, or fan model) Warm up target device for 30 minutes

20 Power Measurement Procedure Sample over the same workload multiple times to achieve statistical confidence Sample at multiple unaliased frequencies for consistent procedure using affordable hardware Calculate average power (using RMS) and energy (per benchmark iteration) Repeat process with more benchmark iterations if Std. Deviation is too big (5%)

21 EEMBC Methodology System Warm up increase samples Run Benchmark and sample V,I 2 unaliased frequencies change frequencies Calculate Avg. Energy/It yes Std Dev Too Big? Or Energy from 2 freq differs too much? no Done

22 Requires Special EEMBC Implementation Test Harness modified Partnership with National Instruments Use LabVIEW and inexpensive DAQ board Allows simultaneous measurement of performance and power Energy calculated per benchmark Use NI tools and hardware NI DAQ can be easily controlled Precompiled LabVIEW software presents consistent GUI and avoids user error

23 NI LabVIEW Used for Display and Analysis

24 NI LabVIEW Used for Display and Analysis

25 Computing the Energy Consumption Computing energy per iteration: Samples / Iteration = Sampling Freq. / (iterations/sec) Power RMS = RMS (power samples for each iteration) Energy for each iteration = POWER RMS * (seconds/iteration) For final result report average of all energy values calculated

26 Computing the Energy Consumption Published result is average energy consumption for one iteration of the workload Use confidence intervals to validate power measurements Sampling will not catch all spikes, but maximum and minimum readings will also be reported

27 Results (Power) basefp01 pow er power no fp, no ic no fp, ic on fp on, no ic fp on, ic on setup 13MHz,0.9V 13MHz,1.2V 52MHz 104MHz 208MHz

28 Results (Performance) basefp01 iter/s iter/s no fp, no ic no fp, ic on fp on, no ic fp on, ic on setup 13MHz,0.9V 13MHz,1.2V 52MHz 104MHz 208MHz

29 Results (Energy) basefp01 energy estimated energy per iteration no fp, no ic no fp, ic on fp on, no ic fp on, ic on 13MHz,0.9V 13MHz,1.2V 52MHz 104MHz 208MHz setup

30 LPC3000 ARM926EJ Road Map Production In develop. Wireless Kiosk display ref design Full motion video graphics support Soft Modem ref design LPC3240 LPC3250 LPC3xxx Functionality VoIP ref design LPC3190 LPC3220 LPC3230 LPC3180 LPC3180/01 Adeneo WinCE 6.0 BSP Wind River Linux BSP

31 LPC3000 Product Portfolio ARM926EJ-S Core 90nm low-power process, operation down to 0.9 V Ultra Low Power Mode Vector Floating Point Co-Processor Integrated Java Byte-Code Co-Processor 0.9 V Ultra Low-Power Mode DMA, 32KB D-Cache, 32KB I-Cache, SPI, I 2 C (2), UART (7), IrDA, 10-b ADC Optional, contact marketing 289 TFBGA 15 x 15 x0.7 with 0.8mm ball pitch 320 LFBGA 13 x 13 x 0.9 with 0.5mm ball pitch 289 TFBGA 12 x 12 x 0.7 with 0.65mm ball pitch

32 LPC3180/01 vs LPC3180 Same Advanced Low Power 90nm CMOS process LPC3180 is the predecessor manufactured at Crolles2 LPC3180/01 is manufactured at TSMC Same Pinout and Package LPC3180/01 improvement I 2 C is now master, multi-master, and slave (instead of master only) JTAG pull-up and pull-down fully meets IEEE specification Improved voltage ranges Peripheral I/O domains: More flexible voltage domains that can reduce the number of different supply voltages These are all extended to include 1.8V, 2.8V, or 3.0V External bus domain: Now extended to include 2.8V and above Improved power-up state 2 pins on each SPI now defaults to inputs (instead of outputs)

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