Digital Thermometer and Thermostat

Transcription

1 Rev 1; 3/08 Digital Thermometer and Thermostat General Description The low-voltage (1.7V to 3.7V) digital thermometer and thermostat provides 9-, 10-, 11-, or 12-bit digital temperature readings over a -55 C to +125 C range with ±0.5 C accuracy over a -0 C to +70 C range. A 9-bit resolution mode is software compatible with the LM75. Communication with the is achieved through a simple 2-wire serial interface. Three address pins allow up to eight devices to operate on the same 2-wire bus, which greatly simplifies distributed temperature-sensing applications. The thermostat has a dedicated open-drain output (O.S.) and programmable fault tolerance, which allows the user to define the number of consecutive error conditions that must occur before O.S. is activated. There are two thermostatic operating modes that control thermostat operation based on user-defined trip points (T OS and T HYST ) that are stored in EEPROM registers. Networking Equipment Cellular Base Stations Office Equipment Medical Equipment Any Thermally Sensitive System TOP VIEW SDA 1 8 VDD 2 7 A0 O.S. 3 6 GND 4 5 SDA SO Applications A1 A2 1 8 VDD 2 7 A0 O.S. 3 6 Pin Configurations A1 Features Operating Range from 1.7V to 3.7V Temperature Measurements Require No External Components Measures Temperatures from -55 C to +125 C (-67 F to +257 F) ±0.5 C Accuracy Over a 0 C to +70 C Range Thermometer Resolution is User-Configurable from 9 (Default) to 12 Bits (0.5 C to C Resolution) 9-Bit Conversion Time is 25ms (max) Thermostatic Settings are User-Definable and Nonvolatile (NV) Stand-Alone Thermostat Capability Data Read/Write Occurs Through a 2-Wire Serial Interface (SDA and Pins) Data Lines Filtered Internally for Noise Immunity (50ns Deglitch) Optional Bus Timeout Feature Prevents Lockup Problems on 2-Wire Interface Multidrop Capability Simplifies Distributed Temperature-Sensing Applications Pin/Software Compatible with the LM75 Available in 8-Pin SO and µmax Packages Ordering Information PART TEMP RANGE PIN-PAGE S+ -55 C to +125 C 8 SO (150 mils) S+T&R -55 C to +125 C 8 SO (150 mils), 2500-Piece T&R U+ -55 C to +125 C 8 μmax 8 μmax, U+T&R -55 C to +125 C 3000-Piece T&R +Denotes a lead(pb)-free/rohs-compliant package. T&R = Tape and reel. GND 4 5 μmax A2 Commands are capitalized for clarity. µmax is a registered trademark of Maxim Integrated Products, Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD Relative to Ground V to +4.0V Voltage Range on Any Other Pin Relative to Ground V to +6.0V Operating Temperature Range C to +125 C Storage Temperature Range C to +125 C Soldering Temperature...Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (1.7V V DD 3.7V, T A = -55 C to +125 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Supply Voltage V DD V Input Voltage Range (SDA,, O.S., A0, A1, A2) Thermometer Error (Note 2, 3) T ERR (Note 1) V 0 C to +70 C ± C to +125 C ± 2.0 Input Logic-High V IH (Note 1) 0.7 V DD V Input Logic-Low V IL (Note 1) 0.3 V DD V SDA Output Logic-Low Voltage V OL1 6mA sink current (Note 1) V O.S. Saturation Voltage V OL2 4mA sink current (Notes 1, 2) 0.8 V Input Current Each I/O pin 0.4V < V I/O < 0.9 x V DD μa I/O Capacitance C I/O 10 pf Standby Current I DD1 (Notes 4, 5, 6) 2 μa Active Current (Notes 4, 5, 6) I DD Active temp conversions 750 Communication only 100 E 2 Copy only 500 C μa AC ELECTRICAL CHARACTERISTICS (1.7V V DD 3.7V, T A = -55 C to +125 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution 9 12 Bits Temperature Conversion Time t CONVT 9-bit conversions bit conversions bit conversions bit conversions 200 Frequency f 400 khz EEPROM Copy Time t WR -40 C to +85 C 10 ms -40 C T A +85 C (Note 7) 10k 20k EEPROM Copy Endurance N EEWR T A = +25 C (Note 7) 40k 80k ms Cycles 2

3 AC ELECTRICAL CHARACTERISTICS (continued) (1.7V V DD 3.7V, T A = -55 C to +125 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Data Retention t EEDR -40 C to +125 C (Note 8) 10 Years Bus Free Time Between a STOP and START Condition START and Repeated START Hold Time from Falling t BUF (Note 9) 1.3 μs t HD:STA (Notes 9, 10) Low Period of t LOW (Note 9) 1.3 μs High Period of t HIGH (Note 9) 0.6 μs Repeated START Condition Setup Time to Rising Data-Out Hold Time from Falling t SU:STA (Note 9) 600 ns t HD:DAT (Notes 9, 11) μs Data-In Setup Time to Rising t SU:DAT (Note 9) 100 ns Rise Time of SDA and (Receive) Fall Time of SDA and (Receive) Spike Suppression Filter Time (Deglitch Filter) t R (Notes 9, 12) t F (Notes 9, 12) Note 1: All voltages are referenced to ground. Note 2: Internal heating caused by O.S. loading causes the to read approximately 0.5 C higher if O.S. is sinking the max-rated current. Note 3: Specified in 12-bit conversion mode. Quantization error must be considered when converting in lower resolutions. Note 4: I DD specified with O.S. pin open. Note 5: I DD specified with V DD at 3.0V and SDA, = 3.0V, T A = -55 C to +85 C. Note 6: I DD specified with A0, A1, A2 = 0V or V DD. Note 7: V DD must be > 2.0V. Note 8: E 2 Copy occurs at +25 C. Note 9: See the timing diagram (Figure 1). All timing is referenced to 0.9 x V DD and 0.1 x V DD. Note 10: After this period, the first clock pulse is generated. Note 11: The provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of s falling edge. Note 12: For example, if C B = 300pF, then t R(MIN) = t F(MIN) = 50ns. Note 13: This timeout applies only when the is holding SDA low. Other devices can hold SDA low indefinitely and the does not reset C B 300 ns ns C B 300 ns t SS 0 50 ns STOP Setup Time to Rising t SU:STO (Note 9) 600 ns Capacitive Load for Each Bus Line C B 400 pf Input Capacitance C I 5 pf Serial Interface Reset Time t TIMEOUT SDA time low (Note 13) ms 3

4 PIN NAME FUNCTION 1 SDA Data Input/Output. For 2-wire serial communication port. Open drain. 2 Clock Input. For 2-wire serial communication port. 3 O.S. Thermostat Output. Open drain. 4 GND Ground 5 A2 Address Input 6 A1 Address Input 7 A0 Address Input 8 VDD Supply Voltage. +1.7V to +3.7V supply pin. Pin Description SDA t F t LOW t F t SP t R t BUF t SU:DAT t R t HD:STA t HD:STA t SU:STA t SU:STO t HD:DAT SR P S Figure 1. Timing Diagram PRECISION REFERENCE OVERSAMPLING MODULATOR DIGITAL DECIMATOR VDD SDA CONFIGURATION REGISTER A0 A1 A2 ADDRESS AND I/O CONTROL TEMPERATURE REGISTER T OS AND T HYST REGISTERS THERMOSTAT COMPARATOR O.S. R F GND Figure 2. Block Diagram 4

5 Operation Measuring Temperature The measures temperature using a bandgap temperature-sensing architecture. An on-board deltasigma analog-to-digital converter (ADC) converts the measured temperature to a digital value that is calibrated in degrees Celsius; for Fahrenheit applications a lookup table or conversion routine must be used. The is factory-calibrated and requires no external components to measure temperature. The can be configured to power up either automatically converting temperature or in a low-power standby state. The preferred power-up mode can be set using the SD bit in the configuration register as explained in the Configuration Register section. The resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits, corresponding to temperature increments of 0.5 C, 0.25 C, C, and C, respectively. The factory default resolution at power-up is 9 bits (R1 = 0, R0 = 0), however this can be programmed to 10, 11, or 12 bits using the R0 and R1 bits in the configuration register as explained in the Configuration Register section. Note that the conversion time doubles for each additional bit of resolution. After each temperature measurement and analog-todigital (A/D) conversion, the stores the temperature as a 16-bit two s complement number in the 2-byte temperature register (see Figure 3). The sign bit (S) indicates if the temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. The most recently converted digital measurement can be read from the temperature register at any time. Since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress. Bits 3 through 0 of the temperature register are hardwired to 0. When the is configured for 12-bit resolution, the 12 MSBs (bits 15 through 4) of the temperature register contain temperature data. For 11-bit resolution, the 11 MSBs (bits 15 through 5) of the temperature register contain data, and bit 4 reads out as 0. Likewise, for 10-bit resolution, the 10 MSBs (bits 15 through 6) contain data, and for 9-bit the 9 MSBs (bits 15 through 7) contain data and all unused LSBs contains 0s. Table 1 gives examples of 12-bit resolution digital output data and the corresponding temperatures. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 MS Byte S Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS Byte Figure 3. Temperature, T OS, and T HYST Register Format Table Bit Resolution Temperature/Data Relationship TEMPERATURE ( C) DIGITAL OUTPUT (BINARY) DIGITAL OUTPUT (HEX) D A FF F5E E6F C900 5

6 Shutdown Mode For power-sensitive applications, the offers a low-power shutdown mode. The SD bit in the configuration register controls shutdown mode. When SD is programmed to 1, the conversion in progress is completed and the result stored in the temperature register, after which the goes into a low-power standby state. The O.S. output is cleared if the thermostat is operating in interrupt mode and O.S remains unchanged in comparator mode. The 2-wire interface remains operational in shutdown mode, and writing a 0 to the SD bit returns the to normal operation. Upon power-up in shutdown mode, the executes one temperature measurement. The result is stored in the temperature register, after which the enters the shutdown state. Operation Thermostat The thermostat can be programmed to power up in either comparator mode or interrupt mode, which activate and deactivate the open-drain thermostat output (O.S.) based on user-programmable trip points (T OS and T HYST ). The T HYST and T OS registers contain Celsius temperature values in two s complement format and consist of EEPROM that is shadowed by SRAM. Once written to the shadow SRAM, values can be stored in EEPROM by issuance of a Copy Data command from the master (see the Command Set section for more details). The device can operate using the shadow SRAM only or using the EEPROM. If the EEPROM is used, the values are NV and can be programmed prior to installation of the for standalone operation. The factory power-up settings for the are with the thermostat in comparator mode, active-low O.S. polarity, overtemperature trip-point (T OS ) register set to 80 C, the hysteresis trip-point (T HYST ) register set to +75 C, and the number of consecutive conversion to trigger O.S. set to 1. If these power-up settings are compatible with the application, the can be used as a stand-alone thermostat (i.e., no 2-wire communication required) with no programming required prior to installation. If interrupt mode operation, active-high O.S. polarity, different T OS and T HYST values, or a different number of conversions to trigger O.S. are desired, they must be programmed into the EEPROM either after initial power-up or prior to IC installation. The programmed values then become the new power-up defaults. In both operating modes, the user can program the thermostat-fault tolerance, which sets how many consecutive temperature readings (1, 2, 4, or 6) must fall outside the thermostat limits before the thermostat output is triggered. The fault tolerance is set by the F1 and F0 bits in the configuration register. The default factory power-up setting for fault tolerance is 1 (F1 = 0, F0 = 0). The data format of the T OS and T HYST registers is identical to that of the temperature register (see Figure 3), i.e., a 2-byte two s complement representation of the trip-point temperature in degrees Celsius with bits 3 through 0 hardwired to 0. After every temperature conversion, the measurement is compared to the values stored in the T OS and T HYST registers. The O.S. output is updated based on the result of the comparison and the operating mode of the IC. The number of T OS and T HYST bits used during the thermostat comparison is equal to the conversion resolution set by the R1 and R0 bits in the configuration register. For example, if the resolution is 9 bits, only the 9 MSBs of T OS and T HYST are used by the thermostat comparator. The active state of the O.S. output can be programmed by the POL bit in the configuration register. The powerup factory default is active low (POL = 0). If the user does not wish to use the thermostat capabilities of the, the O.S. output should be left unconnected. Note that if the thermostat is not used, the T OS and T HYST registers can be used for general storage of system data. Comparator Mode When the thermostat is in comparator mode, O.S. can be programmed to operate with any amount of hysteresis. The O.S. output becomes active when the measured temperature exceeds the T OS value a consecutive number of times as defined by the F1 and F0 fault tolerance (FT) bits in the configuration register. O.S. then stays active until the first time the temperature falls below the value stored in T HYST. Putting the device into shutdown mode does not clear O.S. in comparator mode. Thermostat comparator mode operation with FT = 2 is illustrated in Figure 4. 6

7 IN THIS EXAMPLE, THE IS CONFIGURED TO HAVE A FAULT TOLERANCE OF 2. TEMPERATURE T OS T HYST INACTIVE O.S. OUTPUT COMPARATOR MODE ACTIVE INACTIVE O.S. OUTPUT INTERRUPT MODE ACTIVE ASSUMES A READ HAS OCCURED CONVERSIONS Figure 4. O.S. Output Operation Example Interrupt Mode In interrupt mode, the O.S. output first becomes active when the measured temperature exceeds the T OS value a consecutive number of times equal to the FT value in the configuration register. Once activated, O.S. can only be cleared by either putting the into shutdown mode or by reading from any register (temperature, configuration, T OS, or T HYST ) on the device. Once O.S. has been deactivated, it is only reactivated when the measured temperature falls below the T HYST value a consecutive number of times equal to the FT value. Again, O.S can only be cleared by putting the device into shutdown mode or reading any register. Thus, this interrupt/clear process is cyclical between T OS and T HYST events (i.e, T OS, clear, T HYST, clear, T OS, clear, T HYST, clear, etc.). Thermostat interrupt mode operation with FT = 2 is illustrated in Figure 4. 7

8 Configuration Register The configuration register allows the user to program various options such as conversion resolution, thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. The configuration register is arranged as shown in Figure 5 and detailed descriptions of each bit are provided in Table 2. The user has read/write access to all bits in the configuration register except the MSB (NVB bit), which is a read-only bit. All bits in the register but the NVB bit are NV EEPROM backed by shadow SRAM, and thus power-up in their programmed state. Once written to the shadow SRAM, values can be stored in EEPROM by issuance of a Copy Data command from the master (see the Command Set section for more details). If the values are not copied to the EEPROM, the device powers up with the factory default settings or the last values that were copied to the EEPROM. The NVB bit is SRAM and powers up in the state shown in Table 2. MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB NVB R1 R0 F1 F0 POL TM SD Figure 5. Configuration Register Table 2. Configuration Register Bit Descriptions BIT NAME NVB NV Memory Status R1 Conversion Resolution Bit 1 R0 Conversion Resolution Bit 0 F1 Thermostat Fault Tolerance Bit 1 F0 Thermostat Fault Tolerance Bit 0 POL Thermostat Output (O.S.) Polarity TM Thermostat Operating Mode SD Shutdown FUNCTIONAL DESCRIPTION Power-up state = 0, read only NVB = 1 Write to an NV memory cell is in progress. NVB = 0 NV memory is not busy. Factory power-up state = 0 Sets conversion resolution (see Table 3). Factory power-up state = 0 Sets conversion resolution (see Table 3). Factory power-up state = 0 Sets the thermostat fault tolerance (see Table 4). Factory power-up state = 0 Sets the thermostat fault tolerance (see Table 4). Factory power-up state = 0 POL = 0 O.S. is active low. POL = 1 O.S. is active high. Factory power-up state = 0 TM = 0 Comparator mode. TM = 1 Interrupt mode. See the Operation Thermostat section for a detailed description of these modes. Factory power-up state = 0 SD = 0 Active conversion and thermostat operation. SD = 1 Shutdown mode. See the Shutdown Mode section for a detailed description of this mode. 8

9 Table 3. Resolution Configuration R1 R0 THERMOMETER RESOLUTION (BITS) MAX CONVERSION TIME (ms) Table 4. Fault Tolerance Configuration F1 F0 CONSECUTIVE OUT-OF-LIMITS CONVERSIONS TO TRIGGER O.S Register Pointer The four registers each have a unique 2-bit pointer designation, which is defined in Table 5. When reading from or writing to the, the user must point the to the register that is to be accessed. When reading from the, once the pointer is set, it remains pointed at the same register until it is changed. For example, if the user desires to perform consecutive reads from the temperature register, then the pointer only has to be set to the temperature register one time, after which all reads are automatically from the temperature register until the pointer value is changed. When writing to the, the pointer value must be refreshed each time a write is performed, even if the same register is being written to twice in a row. At power-up, the pointer defaults to the temperature register location. The temperature register can be read immediately without resetting the pointer. Changes to the pointer setting are accomplished as described in the 2-Wire Serial Data Bus section. Table 5. Pointer Definition REGISTER P1 P0 Temperature 0 0 Configuration 0 1 T HYST 1 0 T OS Wire Serial Data Bus The communicates over a standard bidirectional 2-wire serial data bus that consists of a serial clock () signal and serial data (SDA) signal. The interfaces to the bus through the input pin and open-drain SDA I/O pin. All communication is MSB first. The following terminology is used to describe 2-wire communication: Master Device: Microprocessor/microcontroller that controls the slave devices on the bus. The master device generates the signal and START and STOP conditions. Slave: All devices on the bus other than the master. The always functions as a slave. Bus Idle or Not Busy: Both SDA and remain high. SDA is held high by a pullup resistor when the bus is idle, and must either be forced high by the master (if the output is push-pull) or pulled high by a pullup resistor (if the output is open drain). Transmitter: A device (master or slave) that is sending data on the bus. Receiver: A device (master or slave) that is receiving data from the bus. START Condition: Signal generated by the master to indicate the beginning of a data transfer on the bus. The master generates a START condition by pulling SDA from high to low while is high (see Figure 6). A repeated START is sometimes used at the end of a data transfer (instead of a STOP) to indicate that the master performs another operation. STOP Condition: Signal generated by the master to indicate the end of a data transfer on the bus. The master generates a STOP condition by transitioning SDA from low to high while is high (see Figure 6). After the STOP is issued, the master releases the bus to its idle state. Acknowledge (): When a device (either master or slave) is acting as a receiver, it must generate an acknowledge () on the SDA line after receiving every byte of data. The receiving device performs an by pulling the SDA line low for an entire period (see Figure 6). During the clock cycle, the transmitting device must release SDA. A variation on the signal is the not acknowledge (N). When the master device is acting as a receiver, it uses a N instead of an after the last data byte to indicate that it is finished receiving data. The master indicates a N by leaving the SDA line high during the clock cycle. 9

10 Slave Address: Every slave device on the bus has a unique 7-bit address that allows the master to access that device. The s 7-bit bus address is A 2 A 1 A 0, where A 2, A 1, and A 0 are user-selectable through the corresponding input pins. The three address pins allow up to eight s to be multidropped on the same bus. Address Byte: The control byte is transmitted by the master and consists of the 7-bit slave address plus a read/write (R/W) bit (see Figure 7). If the master is going to read data from the slave device then R/W = 1, and if the master is going to write data to the slave device then R/W = 0. Pointer Byte: The pointer byte is used by the master to tell the which register is going to be accessed during communication. The six MSBs of the pointer byte (see Figure 8) are always 0 and the two LSBs correspond to the desired register as shown in Figure 8. SDA START CONDITION (OR N) FROM RECEIVER STOP CONDITION Figure 6. Start, Stop, and Signals Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit A 2 A 1 A 0 R/W Figure 7. Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit P1 P0 Figure 8. Pointer Byte 10

11 General 2-Wire Information All data is transmitted MSB first over the 2-wire bus. One bit of data is transmitted on the 2-wire bus each period. A pullup resistor is required on the SDA line, and, when the bus is idle, both SDA and must remain in a logic-high state. All bus communication must be initiated with a START condition and terminated with a STOP condition. During a START or STOP is the only time SDA is allowed to change states while is high. At all other times, changes on the SDA line can only occur when is low; SDA must remain stable when is high. After every 8-bit (1-byte) transfer, the receiving device must answer with an (or N), which takes one period. Therefore, nine clocks are required for every 1-byte data transfer. Writing to the : To write to the, the master must generate a START followed by an address byte containing the bus address. The value of the R/W bit must be a 0, which indicates that a write is about to take place. The responds with an after receiving the address byte. The master then sends a pointer byte which tells the which register is being written to. The again responds with an after receiving the pointer byte. Following this the master device must immediately begin transmitting data to the. When writing to the configuration register, the master must send one byte of data (see Figure 9B), and when writing to the T OS or T HYST registers the master must send two bytes of data (see Figure 9C). After receiving each data byte, the responds with an, and the transaction is finished with a STOP from the master. All writes to the are made to shadow SRAM. Once data is written to the shadow SRAM, it is only stored to EEPROM by issuance of a Copy Data command from the master. At that time, all registers are copied to EEPROM except the Temperature register which is SRAM only. Reading from the : When reading from the, if the pointer was already pointed to the desired register during a previous transaction, the read can be performed immediately without changing the pointer setting. In this case the master sends a START followed by an address byte containing the bus address. The R/W bit must be a 1, which tells the that a read is being performed. After the sends an in response to the address byte, the begins transmitting the requested data on the next clock cycle. When reading from the configuration register, the transmits one byte of data, after which the master must respond with a N followed by a STOP (see Figure 9E). For two-byte reads (i.e., from the temperature, T OS or T HYST register), the transmits two bytes of data, and the master must respond to the first data byte with an and to the second byte with a N followed by a STOP (see Figure 9A). If only the most significant byte of data is needed, the master can issue a N followed by a STOP after reading the first data byte in which case the transaction is the same as for a read from the configuration register. If the pointer is not already pointing to the desired register, the pointer must first be updated as shown in Figure 9D, which shows a pointer update followed by a single-byte read. The value of the R/W bit in the initial address byte is a 0 ( write ) since the master is going to write a pointer byte to the. After the responds to the address byte with an, the master sends a pointer byte that corresponds to the desired register. The master must then perform a repeated start followed by a standard one or two byte read sequence (with R/W =1) as described in the previous paragraph. The Recall Data command should be issued before a read if assurance is needed that the contents of the EEPROM in the Shadow SRAM when read. Bus Timeout: The has a bus timeout feature that prevents communication errors from leaving the IC in a state where SDA is held low disrupting other devices on the bus. If the holds the SDA line low for a period of t TIMEOUT, its bus interface automatically resets and release the SDA line. Bus communication frequency must be fast enough to prevent a reset during normal operation. The bus timeout feature only applies to when the is holding SDA low. Other devices can hold SDA low for an undefined period without causing the interface to reset. Command Set Recall Data [B8h] Refreshes SRAM shadow register with EEPROM data. It is recommended that a Recall command be performed before reading EEPROM-backed memory locations. The master sends a START followed by an address byte containing the bus address. The R/W bit must be a 0. The responds with an. If the next byte is a 0xB8, the recalls all EEPROM data into shadow RAM locations. 11

12 Copy Data [48h] Copies data from all SRAM shadow registers to EEPROM. It is recommended that a Copy Data command be performed after writing EEPROM-backed memory locations to guarantee data integrity in the event of a power loss. The master sends a START followed by an address byte containing the bus address. The R/W bit must be a 0. The responds with an. If the next byte is a 0x48, the copies all Shadow RAM locations in EEPROM memory. Software POR [54h] The master sends a START followed by an address byte containing the bus address. The R/W bit must be a 0. The responds with an. If the next byte is a 0x54, the resets as if power had been cycled, which stops temperature conversions and resets all registers to their power-up states. No is sent by the IC after the POR command is received. Afterwards, the makes a single temperature conversion or continuous temperature conversions, depending on the state of the SD bit. A) READ 2 BYTES FROM THE TEMPERATURE, T OS, OR T HYST REGISTER (CURRENT POINTER LOCATION) SDA S A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N P START ADDRESS BYTE MS DATA BYTE (FROM SLAVE) (MASTER) LS DATA BYTE (FROM SLAVE) N STOP (MASTER) B) WRITE TO THE CONFIGURATION REGISTER SDA S A2 A1 A0 W A A D7 D6 D5 D4 D3 D2 D1 D0 A P START ADDRESS BYTE POINTER BYTE DATA BYTE (FROM MASTER) STOP C) WRITE TO THE T OS OR T HYST REGISTER SDA S A2 A1 A0 W A P1 P0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 A P START ADDRESS BYTE POINTER BYTE MS DATA BYTE (FROM MASTER) LS DATA BYTE (FROM MASTER) STOP D) READ SINGLE BYTE (NEW POINTER LOCATION) SDA S A2 A1 A0 W A P1 P0 A S A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 N P START ADDRESS BYTE POINTER BYTE REPEAT START ADDRESS BYTE DATA BYTE (FROM SLAVE) N STOP (MASTER) E) READ FROM THE CONFIGURATION REGISTER (CURRENT POINTER LOCATION) SDA S A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 N P START ADDRESS BYTE MS DATA BYTE (FROM SLAVE) N STOP (MASTER) Figure 9. 2-Wire Interface Timing 12

13 Package Information For the latest package outline information and land patterns, go to PAGE TYPE PAGE CODE DOCUMENT NO. 8 SO S µmax U

14 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 2/08 Initial release. 1 3/08 Removed references to exposed pad (μmax package does not have an EP); corrected package information outline document number. 1, 4, 13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.