Understanding the new '5xx Integrated Power Management Module (PMM) Stefan Schauer

Transcription

1 Understanding the new '5xx Integrated Power Management Module (PMM) Stefan Schauer 6/5/ Agenda Introduction into the PMM System Technical Data, specified Values Software controlled PMM configuration Power considerations System Protection Summary 2 1

2 Power Management Module (PMM) 5xx-Core (CPU, Memory, ) uses a low voltage can t accept the higher voltage range required at system level (Unlike pre-5xx) Therefore an internal LDO generates V CORE rail from DVcc Modules reside primarily in DVcc or V CORE domains DVcc: V (Same input range as 2xx/4xx) V CORE : System-programmable to 1.35V/1.55V/1.75V/1.85V according to MCLK requirements Only external Capacitor is required for V CORE (470nF) 3 PMM Highlights PMM has sub-units that provide supervision and monitoring Supervision generates POR if low-voltage event occurs Monitoring provides interrupts on event occurrence VCC is the high-side of LDO, V CORE is low-side Still have zero-power BOR, similar to 4xx Accurate voltage supervision for cost of 100nA! 4 2

3 PMM Supervision Features DVCC and V CORE both have: Programmable supervision/monitoring (SVS/SVM) levels Software-selectable POR and power-fail conditions SVM (Supply Voltage Monitor) Generates interrupt if voltage goes above/below programmable threshold Applies to both DVcc and V CORE SVS (Supply Voltage Supervisor) Generates POR if voltage goes below programmable threshold Applies to both DVcc and V CORE BOR (BrownOut Reset) Minimum V CORE threshold reset Less precision than SVS, but also less power 5 BOR / POR / PUC BOR Resets all SFR bits associated with BOR [-0,-1] POR Resets all SFR bits associated with POR (-0,-1) PUC Resets all SFR bits associated with PUC -0,-1 6 3

4 5xx Operational Modes LPM0/1/2/3/4 are the same as previous families LPM5 Same as LPM4, except LDO/core are powered down RAM/register contents are not retained Wakeup with RST/NMI pulse Future 5xx Devices will also get wakeup for Port pins 7 Supervision/Monitoring Flags automatically set/cleared according to rail state SVM, SVS, BOR are working hand in hand POR event generated as well 8 4

5 Agenda Introduction into the PMM System Technical Data, specified Values Software controlled PMM configuration Power considerations System Protection Summary 9 High side SVS/SVM The high side SVS/SVM is used for system voltage observation SVM provides an early warning and gives the system some time to go into a safe state Shut down critical tasks Reduce current consumption so that the system may recover Save parameters Default operation: SVS H on in Active and LPM0 mode SVS H off in LPM2/3/ Min/Max Typ DVcc(Min) SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM Vcore = 0 Vcore = 1 Vcore = 2 Vcore =

6 Low side SVS/SVM The low side SVS/SVM is mainly used safe change of V CORE SVM generates flag to indicate when the V CORE level is sufficient high for desired MCLK frequency SVS could be used to reset the system in critical applications and ensure only proper execution of instructions Default operation: SVS L on in Active and LPM0 mode SVS L off in LPM2/3/ Min/Max 1.8 Typ DVcc(Min) SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM Vcore = 0 Vcore = 1 Vcore = 2 Vcore = 3 11 BOR / POR / PUC Sources BOR Sources: Power on / Brownout RST/NMI Security violation (protected Memory) Software (Bit in PMM) LPM5 wake up POR Sources: SVS low/high Software (Bit in PMM) PUC Sources: WDT Key Violation (WDT, Flash, PMM, ) Fetch out of Peripheral Area Software (Bit in PMM) 12 6

7 LDO for V CORE The LDO supplies the required current for the CPU and the digital parts of the device. LDO is trimmed for optimized power consumption Switched mode is automatically used in Low Power modes to further reduce the power consumption in standby Note: It is not allowed to use the V CORE LDO for application purposes!! 13 PMMCOREV Levels Most applications can operate at lowest setting, with no need to alter default PMM configurations 14 7

8 Typical Voltage Profile on V CORE Phase 1: 0sec - 25sec CPU : switch between LPM and Active mode Phase 2: 25sec - 55sec ADC measurements are done Phase 3: 55sec - 90sec CPU active all the time LDO continuously adapts to the power required by the system 15 Agenda Introduction into the PMM System Technical Data, specified Values Software controlled PMM configuration Power considerations System Protection Summary 16 8

9 Access to PMM registers (Password) PMM Registers are password protected!!! General Password is located in the PMMCTL register Open PMM with PMMCTL_H PMMCTL_H = 0xA5; 0xA5; Lock PMM with PMMCTL_H PMMCTL_H = 0x00; 0x00; When PMM is open all PMM registers are open for write access Also for clearing the PMM interrupt flags the PMM needs to be opened (except read of IV Register (e.g. SYSSNIV) 17 Recommend Software flow to change V CORE Ensures a safe transition of the V CORE voltage during operation mode. Set and check the required V CORE Voltage before increasing the CPU frequency Increase/decrease V CORE only step by step Voltage SVM L V CORE SVS L time 18 9

10 Example: Increasing MCLK from Default to 20MHz For MCLK>12MHz, must increase V CORE to support higher speed Unlock PMM registers Set SVM to minimum threshold for chosen speed Change LDO output Poll SVM output until voltage OK Disable SVM (if not used) and lock PMM registers PMMCTL0_H PMMCTL0_H = = 0xA5; 0xA5; Open Open PMM PMM module module PMMCTL0 PMMCTL0 = = 0xA500 0xA level; level; Set Set VCore VCore SVSMLCTL SVSMLCTL = = SVMLE SVMLE + + (level (level * * SVSMLRRL0); SVSMLRRL0); Set Set SVM SVM new new Level Level while while ((PMMIFG ((PMMIFG & & SVSMLDLYIFG) SVSMLDLYIFG) == == 0); 0); Wait Wait till till SVM SVM is is settled settled (Delay) (Delay) PMMIFG PMMIFG &= &= ~(SVMLVLRIFG ~(SVMLVLRIFG + + SVMLIFG); SVMLIFG); Clear Clear already already set set flags flags if if ((PMMIFG ((PMMIFG & & SVMLIFG)) SVMLIFG)) while while ((PMMIFG ((PMMIFG & & SVMLVLRIFG) SVMLVLRIFG) == == 0); 0); Wait Wait till till level level is is reached reached PMMCTL0_H PMMCTL0_H = = 0x00; 0x00; Lock Lock PMM PMM module module registers registers Change Change DCO DCO speed speed here here 19 Use of provided Macros and Function Make your life easy by using the provided functions for setting the PMM SetVCore SetVCore (3); (3); Handles Handles Vcore Vcore up up and and down down SetVCoreUp SetVCoreUp (1); (1); Handles Handles Vcore Vcore up up SetVCoreDown SetVCoreDown (0); (0); Handles Handles Vcore Vcore down down 20 10

11 Available Flags and interrupt sources Status flags from SVS/SVM on low and high side are available SVS/SVM provides a Delay interrupt flags which shows that the SVS/SVM has settled after a change (easier software handling) Separate Flags for Resets (BOR, POR, PUC) and their sources are available to allow individual power up handling Different system initialization, e.g. RTC Power up System Violation error 21 Interrupt Vector Generator Registers interrupt interrupt void void SYSNMI_ISR(void) SYSNMI_ISR(void) { PMMCTL0_H PMMCTL0_H = 0xA5; 0xA5; Open Open PMM PMM switch( switch( even_in_range(syssniv, 0x12)) 0x12)) { case case 0x00: 0x00: break; break; No No Int. Int. pending pending case case 0x02: 0x02: msvmlifg_handler(); break; break; case case 0x04: 0x04: msvmhifg_handler(); break; break; case case 0x12: 0x12: msvmhvlrifg_handler(); break; break; default: default: break; break; } PMMCTL0_H PMMCTL0_H = 0x00; 0x00; Lock Lock PMM PMM } 22 11

12 Agenda Introduction into the PMM System Technical Data, specified Values Software controlled PMM configuration Power considerations System Protection Summary 23 Performance Settings SVS H, SVS L, SVM H, SVM L each operate in fast or slow modes (individually controllable) Fast = continuous operation Slow = slower duty cycle driven (switched mode) Default Slower response to under-voltage Very fast under-voltage spikes may go uncaught (proper decoupling necessary to catch very fast under-voltage spikes) Mode Fast Slow Response time ~1us ~150us / 200us Current draw 20uA 100nA 24 12

13 SVS/SVM Performance Control Mode Slow/Fast Mode could be controlled by software or automatically Default is Slow mode In Automatic mode the operation mode switches between the different performance levels of the SVS/SVM Slow: Switched mode of SVS/SVM (slower reaction) Fast: full-performance mode Manual Mode Automatic Mode 25 Current consumption of separate functions SVS high side SVM high side SVS low side SVM low side LDO BOR Off 0 na 0 na 0 na 0 na Slow 100 na 100 na 100 na 100 na ~ 2 ua Full 20 ua 20 ua 20 ua 20 ua 0 na (incl. Active/LPMx Modes) Typical Values 26 13

14 Power Considerations of PMM Modes The default setting (slow mode) gives a high reliability with low power consumption. Applications requiring highest power reliability could switch the SVS into full performance mode - > continuous observation Application less sensitive may switch off the SVS/SVM to get the lowest possible power consumption 27 Low Power Modes with LDO switched mode No high current is required at the LPM Decoupling could buffer all the required current peaks V CORE is increased automatically to give more headroom. For critical application (esp. high Temperature) keep the quality of the Capacitors in mind

15 Low Power Mode 5 (LPM5) LPM5 is LPM4 (same as in 1xx/2xx/4xx) + regulator off More gates = more leakage, therefore LPM4 current higher F449 (60K/2K) 25C, typ: 0.1uA FG4619 (120K/4K) 25C, typ: 0.4uA F5438 (256K/16K) 25C, 3V, typ, PMMCOREV=0: 1.0uA LPM5 shuts down regulator (and core): 0.1uA (25C, typ) No RAM retention Wake up by RST or one of a few I/Os (F5438 is RST only) I/Os become hi-z inputs Wake up issues a BOR reset, so execution starts over Code must handle accordingly! 29 Entering LPM5 LDO operates in all modes except LPM5 LDO shuts off when LPM4 entered while PMMREGOFF bit set (entering LPM5) Active clock request delays LDO shutdown Interrupt occurring between PMMREGOFF=1 & entering LPM4 clears PMMREGOFF Especially possible if clock request delays LPM4 entry Even possible with no clock request unless handled properly! disable_interrupt(); Clears GIE GIE PMMCTL_H = 0xA5; 0xA5; Open Open PMMM PMMM PMMCTL_L = = PMMREGOFF; Disable LDO LDO on on LPM4 LPM4 entry entry bis_sr_register(lpm4+gie); Sets Sets GIE GIE while while entering LPM5 LPM

16 Agenda Introduction into the PMM System Technical Data, specified Values Software controlled PMM configuration Power considerations System Protection Summary 31 Protect from changing the PMM settings A bit in the SYSCTL registers allows the PMM module to be locked, preventing write access After setting this bit there is no user write access allowed to the PMM SYSCTL = SYSPMMPE; PMM could still be accessed via the protected BSL segments Reset of the PMM protection is only possible with BOR 32 16

17 I/O Port Behavior in LPM 5 All I/Os become hi-z inputs when regulator shuts down On F5438, wakeup only from RST; edges on I/Os have no effect All registers - including port registers - get reset when exiting LPM5 33 Summary The PMM module is able to provide the required power at the right time Default system configuration will meet most of the application requirements But for higher system security or lower power consumption the system could be modified by Software PMM provides the highest system security ever available in an MSP

18 Thank you 35 18