Chapter 5: ASICs Vs. PLDs

Transcription

1 Chapter 5: ASICs Vs. PLDs 5.1 Introduction A general definition of the term Application Specific Integrated Circuit (ASIC) is virtually every type of chip that is designed to perform a dedicated task. ASICS, more specifically, are designed by the end user to perform some proprietary application. Semicustom and full-custom Application Specific Integrated Circuits are very useful in integrating digital, analog, mixed signal or system-on-a-chip (SOC) designs but are very costly and not schedule friendly. Depending on the design application, there are many advantages in using ASICs rather than Field Programmable Gate Arrays (FPGAs) or Complex Programmable Logic devices (CPLDs). Some advantages include higher performance, increased densities and decreased space requirements. Some disadvantages include lacking flexibility for changes and difficulty to test and debug. There are some design applications best suited for ASIC technology and others suited for PLDs. Logic designs done in FPGA occupy more space and have decreased performance and may need to be migrated to an ASIC methodology. The migration process introduces issues such as architectural difference and logic mapping to vendor specified functions. 5.2 ASIC Industry The ASIC industry is very volatile with new companies, products and methodologies emerging daily. In the mid-1980s the prediction was that ASIC designs would be taking over 50% of the electronic design market by When 1990 came the ASIC market turned out to be approximately 10%. Most of the focus for ASICS is providing a technology capable of handling 100,000 or more gates with very high performance. Most of the new ASIC designs do not require high density and 79

2 performance. Two-thirds of all ASIC designs fall within the 15,000 to 20,000 gate range. There are three main areas that are driving ASIC technology. The first consists of designers of high complexity segmented systems developing high performance systems on a chip. These designs typically include custom Central Processing Units (CPUs), onchip memory, peripheral control and interface logic for end application. The other driving force behind ASIC technology is the mainstream designers that are concerned with logic consolidation and reducing the overall area that the design occupies. The last driving force is the Electronic Design Automation (EDA) tools, which are available for large complex system designs and have the flexibility to target any type of technology with a single standard design methodology. The main reason for designers to avoid ASICs is the high levels of cost and risk. Many designers do not want to use ASICs because of the concern for missing the schedule and jeopardizing the project. Projects should have contingencies in case the development of the ASIC fails either by fabrication or lack of design performance. The vast majority of design engineers have never designed an ASIC. 5.3 ASIC Advantages and Disadvantages The advantages and the disadvantages are determined by the nature of the proposed application. Factors that contribute to using ASICs are product development budget, available expertise, production volume, desired product features and competition. Sometimes there is a considerable amount of analysis required to determine if an ASIC design is appropriate and/or the application it is intended for can only be designed in an ASIC. The auto industry is concerned about cost reduction associated with large volumes 80

3 of a particular design. The space and military industry is concerned with the reliability and size of the design. The following is a list of ASIC advantages and disadvantages 1. ASIC Advantages ASICS represent the only way the design may be implemented. The desired performance and functionality may not be attainable by using standard components. ASICs can provide or incorporate unique features that may add value to a design making it more marketable. ASICs assist in the consolidation of logic where space and size are a concern for a given application. One single ASIC can replace a number of standard components and incorporate an entire Printed Circuit Board (PCB) design. The use of ASIC technology may be able to incorporate more features into a smaller space. ASICs, when used to reduce the amount of standard logic can decrease system costs, increase reliability and lower the power and cooling requirements. The reduction of power may allow some designs to be converted to battery operation depending on the application and end use. Development time may be reduced for some applications if an entire system has been incorporated into a single ASIC. ASICs provide an increase in performance and throughput when compared to standard Integrated Circuits (ICs) or PLDs. ASICS enhance design security making it virtually impossible to reverse engineer. 81

4 2. ASIC Disadvantages The cost of prototyping is quite high increasing the Nonrecurring Engineering (NRE) costs depending upon the design, complexity and method of implementation. ASICs introduce the risk of having to do multiple iterations, which increase the cost and delays the project schedule. It has been determined that 50% of all the ASIC designs fail on the first try to operate in the targeted system. It is difficult to make minor changes or fine-tune the design late in the development cycle. Testing and debugging are very difficult on an ASIC. The ability for the design to integrate desired functions may make it not suitable for ASIC technology. The cost of making the ASIC is extremely expensive. The increased volume reduces the overall cost of the design per unit. The volume of the design may not reach the break-even point to be cost effective compared to the use of standard components. 5.4 ASIC Design Flow The responsibilities of the development of the ASIC are shared between the ASIC vendor and the designer or user. The extent of the responsibilities, interaction between the vendor and the designer and the data that is exchanged depends on the design methodology. Figure 5.1 shows a top-level view of the basic ASIC design flow. The 82

5 ASIC design flow appears to be slightly more complicated than the Design flow for PLDs. ASIC VENDOR USER Design Consultation System Specification Turnkey design and Analysis Test Pattern Generation Logic Design Simulation Automatic Place and Route Simulation-Level Design Interface Automatic Place and Route Post Layout Simulation Back-annotation Simulation File Approval???? NO YES Layout-Level Design Interface Design Verification Mask Generation Wafer Fabrication Test Program Generation Prototype Assembly and Test Prototype Delivery Prototype Evaluation NO YES Production Figure 5.1 ASIC Design Flow 83

6 5.5 ASIC Design Architectures There are two branches of ASIC design architecture, semi-custom and custom. Custom includes full custom and cell based, which can be broken down to standard cells and compiled cells. Semi-custom includes channeled and channel-less array-based and programmable logic devices. This section will provide a general comparison between the different types, excluding PLDs because they were discussed in Chapter 2. Figure 5.2 is an illustration of an ASIC family tree. ASIC SEMICUSTOM CUSTOM PROGRAMMABLE LOGIC ARRAY- BASED CELL-BASED FULL CUSTOM STANDARD CELL COMPILED CELL CHANNELED CHANNELESS Figure 5.2 ASIC Family Tree Custom ASICs Custom ASIC designs have a wafer fabrication that is unique to a particular custom design. A semi-custom ASIC, uses predefined cell structures requiring only the interconnections to complete the design. 84

7 Full-Custom ASICs In a full custom design the transistors; capacitors, resistors, digital logic and analog circuits are all positioned in the circuit layout. These designs are referred to handcrafted designs. One key feature of this design is that it is very flexible. Each circuit element can be optimized for its particular function and the amount of silicon can be minimized. A full custom design requires designers that are highly skilled in circuit design and layout and may take many years to finish the design. The ASIC design can only be optimized for a specific target process and is not portable to other advanced processes. A full-custom design provides many advantages for a large complex design in system performance and area density. Full custom designs contribute to approximately 10% of the new designs that are being done Cell-Based ASICs Cell-based designs offer a compromise between full custom and array-based. Cell-based provides flexibility in circuit layout but utilizes predefined circuit elements called cells. A cell can be as simple as a resistor and as complex as a processor. The placement of a cell is not fixed to a grid like the array-based. The design process is simple because the designer does not need to know the transistor level design of each of the cells. The cells are predefined and are contained in libraries specified in the vendor s process. The user instantiates the cell into the design, simulates the design, and gives the data base to the vendor. The Vendor will perform the automated computer-based layout. Cell-based and compiled custom designs are getting closer to the performance levels and density as full-custom. They are developed in a less amount of time and are significantly 85

8 lower in cost. Array-based ASICs have the major portion of the market but cell-based is closing the gap. Cell libraries can contain complex higher-level building blocks that include core microprocessors, peripheral controllers, RAM, ROM, mixed digital and analog functions and complex data path elements. Cell-based libraries are difficult to port to array-based processes. Compiled custom cells contain process-independent design methodologies. They require only a design rule check to verify that the simulation meets design requirements before they can be integrated into any process, cell-based or array-based. Cell based methodologies have higher NRE costs and have longer lead times. There are higher manufacturing requirements with cell-based than with array-based. Cell-based and compiled based requires more fabrication steps, up to more than 12 mask layers for standard CMOS process. Array-based only require the interconnection layers to be customized resulting in as low as two mask layers. The more complex the design the more the gap is closed between the two processes. Cell based yield smaller die size than array-based, are not restricted to a grid and do not need to conform to any pattern of array structures. Cell based allows for tighter packaging resulting in shorter connection and a higher performance Semi-custom Array-Based ASICs Array-based methodology represents the largest ASIC market. Gate Arrays are preprocessed down to the interconnection layers. The interconnection layers customize the array and connect up the macro cells. The array slices are fabricated in large quantities resulting in one-time mask costs reducing NRE and providing faster turnaround times for both prototype and production. If there is a design modification or an 86

9 error to be fixed, there will have to be another prototype iteration including mask generation, fabrication, assembly and test. This is less of an impact with array-based because of the reduced layers in the methodology. Array-based ASICs come in two forms, channeled and channel-less. Channeled arrays contain empty channels of silicon separated into rows of unwired transistor pairs, which can be configured into gates, flip-flops or large functions. The routing between the elements are performed by using the dedicated routing channels. These arrays can support designs up to 20,000 gates. channel-less architecture is used for designs beyond the limit of channeled because they offer more efficient routing with the sea-of-gates approach. 20,000 gates are a limit; because fabrication processes are being limited to two layers of metal interconnect. The channeled arrays are reaching three and four layers with increasingly test and integration efforts. In the channel-less arrays the routing channels are removed and the entire array is covered with active usable transistor cells. The unused transistor sites that are not used for the intended design function are used as the routing resources. Interconnection metal is deposited write over the unused transistors. channel-less arrays have the capacity of 100,000 gates and after routing can utilize 40% of that. They are also proceeding to three and four layer processes. RAM can be implemented in array-based methodologies with more difficulty than cell-based. In array-based, an optimized block of RAM of a predetermined size, is positioned in a allocated area in the array. 87

10 5.6 PLD Migration to ASICs PLDs are more cost effective and do not drive the schedule like ASICs. They are available off-the-shelf, contain relatively high densities and performance characteristics. The disadvantages that lead to the migration to ASICs are as follows: FPGAs contain overhead circuitry for programming. An example of overhead circuitry is the antifuse elements or SRAM/EPROM cells. This results in FPGAs that are larger and slower than ASICs. The FPGA contains connection paths that are slowed by the programming circuitry. More area is required in an FPGA than an ASIC for the same amount of logic resulting in connection paths that are longer. The longer paths increase the resistance and capacitance, decreasing the performance of the design to sometimes three to four times slower than ASICs. The area of the design is significantly larger in an FPGA. A design in an FPGA is ten times larger than the same design implemented in an ASIC. PLDs are reaching densities of over 100,000 gates with very high performance improvements. This makes PLDs a very attractive alternative to ASICs. There is a crossover point for the production of the design to be better implemented using an ASIC. This process is called FPGA conversion. One critical thing is that the design can no longer be dynamic but fixed. One concern with FPGA conversion is if the design will work successfully. FPGA conversion consists of changing the netlist design to the vendor design environment. The architecture in an ASIC varies from the architecture found in a FPGA resulting in problems with functionality, timing and pin layout. Table 88

11 5.1 provides a comparison between standard components, PLDs, gate arrays, standard cells and full-custom ASICs. Criterion Standard Components PLDs Gate Arrays Standard Cells Full Custom Time to market Short to Short Medium Medium Long medium Development Immediate Immediate Weeks to Weeks to Years lead time months months Development None Low Medium to Medium to Very high costs high high Availability High High Medium Medium Low Available Many Many Few Few Few sources Volume Low Low High High High dependence Application Much Much Some Some None support Architectural Low Medium High Higher Highest flexibility to high Design change Medium Medium High Higher Highest ease to high Performance Low High High High Very high Density Low Medium Very high Very high Very high Solution Low to Low High High Very high efficiency medium Design change cost Low Medium High High Very high Table 5.1 Technology Comparison FPGA synthesis and optimization software is making it easier to migrate a design to ASIC technology. Synopsys Inc. and Examplar Logic are the two companies that offer this software. Synopsys FPGA compiler offers synthesis that is technology independent using VHDL, Verilog or logic level description. It translates the HDL to one or more ASIC technologies offered by various vendors. FPGA compiler is supported by Actel, Altera, Lucent Technologies, and Xilinx. Actel supports the ASIC migration with a 89

12 program called Technology-Transparent Design (TTD). TTD enables designers to have access to many EDA tools that provide a vendor-independent migration path to ASICs. To migrate a design from FPGAs to ASICs, the netlist file is given to the ASIC vendor. The netlist file is usually in an EDIF format. The migration process includes design layout, inserting scan for testability and developing test vectors through Automatic Test Pattern Generation (ATPG). The test vectors are sent through the simulation process to determine if the design and performance requirements are met. Once the customer reviews the simulation and accepts the design, the prototyping process can begin. There are other conversion factors that need to be taken into consideration. The routing efficiency of an ASIC affects the speed, die size and packaging. The metal mask layers in custom ASICs and traditional gate arrays offer higher speeds and smaller die size. ASICs provide flexible output drive capabilities so the customer can select the output drive strength. Pin assignments need to be considered in making the conversion. FPGA pin assignments are predefined providing less flexibility in pin assignments. Each pin on an ASIC has to be identified as an input, output, bidirectional, power and ground. The following issues need to be taken into consideration when transferring a design from a FPGA to an ASIC: Technology and architectural differences between FPGAs and ASICs. Reliable conversion of the FPGA source files into ASIC source data. Logic and timing errors in the design from the conversion. Verification of the fanout and place and routing rules from one technology to another. 90

13 5.7 Summary ASICs provide higher performance and higher densities for very large complex designs. ASICs provide for flexibility for mixed signal designs but may introduce increased cost and schedule delays. Modifications to the design are impossible late in the design process, creating a complete iteration from mask generation, fabrication, and assembly to test. There are two branches of ASIC design architecture and they are semicustom and custom. Custom includes full-custom and cell based, which can be broken down to standard cells and compiled cells. Semi-custom includes channeled, channelless array-based and programmable logic devices. There is a crossover point for the production of FPGA designs to be better implemented using an ASIC. This process is called FPGA conversion. There are considerations that need to be addressed when converting a design from an FPGA to an ASIC. These considerations include architecture, timing and logic differences. 91