OP ERA TIONS MANUAL LPM/MCM- 6117

Transcription

1 OP ERA TIONS MANUAL LPM/MCM WinSystems reserves the right to make changes in the circuitry and specifications at any time without notice. Copyright 2001 by WinSystems. All Rights Reserved.

2 REVISION HISTORY P/N ECO Number Date Code Rev Level ORIGINATED C D

3 TA BLE OF CON TENTS Section Paragraph Page Number Ti tle Number 1 General Information 1.1 Features General Description Specifications LPM/MCM-6117 Technical Reference 2.1 In tro duc tion ALI M6117 Processor/Chipset Real Time Clock/Calendar Keyboard Interface Serial Interface Parallel Printer Interface Speaker/Sound Interface PC/104 Bus Interface Floppy Disk Interface IDE Hard Disk Interface Watchdog Timer Configuration Battery Select Control STD- Bus Configuration Interrupt Routing Silicon Disk Configuration Multi-I/O Con nec tor Status LED Parallel I/O Flash BIOS Enable Jumper/Connector Sum mary Award BIOS Configuration 3.1 General Information Entering Setup Setup Main Menu Standard CMOS Setup BIOS Features Setup Chipset Features Setup Load BIOS Defaults Load Setup De faults Password Setting IDE HDD Auto Detection Save & Exit Setup Exit without Saving 3-13

4 4 LPM/MCM-6117 Silicon Disk Reference 4.1 Introduction ROMDISK us age Bootable RAMDISK usage Non-Bootable RAMDISK usage Non-Bootable FLASHDISK us age DiskOnChip usage WS16C48 Programming Reference 5.1 Introduction Function Definitions Sample Programs 5-6 APPENDIX A Port I/O Map APPENDIX B Interrupt Map AP PENDIX C WS16C48 I/O Routines and Sample Program Listings

5 Visual Index Quick Reference Top View Connectors/Headers For the convenience of the user, a copy of the Visual Index has been provided with direct links to connector and jumper configuration data. J1 MULTI I/O J3 OVER THE TOP INTERRUPT HEADER J4, J7 PARALLEL I/O J10 FLOPPY DISK J6 COM3/COM4 OUTPUT HEADER J11 MEMORY SOCKET DEVICE J19 8-BIT PC/104 J20 16-BIT PC/104 J28 IDE J21 INTERRUPT J29 STD Bus OPERATIONS MANUAL LPM/MCM-6117 i

6 Visual Index Quick Reference Top View Jumpers For the convenience of the user, a copy of the Visual Index has been provided with direct links to connector and jumper configuration data. J5 BATTERY BACKUP J2 PARALLEL I/O J8, J13 COM1 CONFIGURATION J12, J14 COM3 CONFIGURATION J15, J17 COM4 CONFIGURATION J9, J16 COM2 CONFIGURATION J18 FLASH BIOS J23 PARALLEL PORT DMA JUMPER J25 STD PINS 39 AND 40 CONFIGURATION J27 STDBus V-BAT ENABLE J22 WATCHDOG TIMER J24 MASTER BATTERY J26 PARALLEL PORT DMA REQUEST OPERATIONS MANUAL LPM/MCM-6117 ii

7 1 GENERAL INFORMATION 1.1 FEATURES High Integration 33MHz 386sx Proc es sor Board Up to 8 Mega bytes of ruggedized SMT DRAM Solid State Disk support for EPROM, SRAM, FLASH, or DiskOnChip In dus try Standard AWARD BIOS with POST Four PC Compatible Se rial Ports with optional RS- 422/RS- 485 support Stan dard Par al lel Printer Port Watchdog Timer with Pow er fail/re set On board 16- bit IDE Interface On board Dual Floppy Disk Controller Stan dard AT Key board Support Real-Time Clock with Battery Backup Status and Hard Disk LEDs +5 Volt Only Operation 48 Lines of Parallel I/O with event sense interrupts 1.2 GENERAL DESCRIPTION The LPM/MCM-6117 is a small, high-performance computer sys tem on a single STD- Bus board. It features the high integration ALI M6117 CPU/Chipset com bi na tion IC running at 33MHz. It can be populated with up to 8 Mega bytes of fac tory installed SMT DRAM. Its full PC/AT hard ware com ple ment and in dus try standard AWARD BIOS as sures full hardware and soft ware compatibility with PC soft ware and op er at ing sys tems. The LPM/MCM-6117 in cludes onboard interfaces for floppy disks, IDE fixed disks, par al lel printer, and four serial channels with RS- 232, RS- 422, or RS- 485 ca pa bil ity on ei ther or a ll chan nels. A 16-bit PC/104 expansion bus is pro vided for further expansion to in dus try standard add-on pe riph er als including high- speed VGA con trol lers, sound and speech modules, SCSI controllers, ana log I/O mod ules, and literally hun dreds of other op tions available from Win Sys tems and a variety of ven dors supporting the PC/104 stan dard. An on board Sili con Disk sup ports disks of up to 1 Mega byte in size and can util ize SRAM, PEROM or EPROM as the disk me dia. Boot ca pa bil ity is provided onboard and a set of utili ties and drivers are provided to make the silicon disk based sys tem very user friendly. Al ter nately, the M-Systems' DiskOnChip FLASH mod ules may be populated and disk sizes range from 8 Mega bytes to 288 Mega bytes OPERATIONS MANUAL LPM/MCM-6117 Page 1-1

8 1.3 Specifications Electrical Bus Interface : STD-Bus 8-Bit and 16-Bit PC/104 8-Bit and 16-Bit expansion Bus System Clock : Factory configured for 33Mhz Interrupts : TTL Level in put VCC : VCC1: VCC2: +5V +/-5% at 950mA typical at 33Mhz and 2MB DRAM +12V +/-5% (Not required. PC/104 Expansion Only) -12V +/-5% (Not required. PC/104 Expansion Only) Memory Addressing : 16 Megabyte addressing BIOS ROM : 128K OTPROM Memory : Factory installed SMT DRAM in sizes from 2M, 4M, and 8M SSD Memory : One 32-pin JEDEC standard sockets support 4-MBit SRAM, 4-MBit PEROM, 4-MBit EPROM, 16-MBit EPROM or the M-Systems 32-pin DOC (DiskOnChip) Module Mechanical Dimensions : 4.5 X 7 PC-Board : FR4 Epoxy Glass with 4 signal layers and 2 power planes with screened component legend, and plated through holes. Jumpers : 0.025" square posts on 0.10" cen ters Connectors : Multi I/O : 50 pin RN type IDH-50-LP Floppy Disk : Fixed Disk : PC/104 BUS : 34 Pin RN type IDH-34-LP 40 pin RN type IDH-40-LP 64 pin SAMTEC type ESQ G-D 40 pin SAMTEC type ESQ G-D Page 1-2 OPERATIONS MANUAL LPM/MCM

9 COM3/COM4 : 10-pin RN type IDH-10LP Parallel I/O : 50-pin RN type IDH-50LP Environmental Operating Temperature : -40 to +85 C LPM to +60 C MCM-6117 Non-Condensing Humidity : 5 to 95% OPERATIONS MANUAL LPM/MCM-6117 Page 1-3

10 2 LPM/MCM-6117 Technical Reference 2.1 Introduction This sec tion of the man ual is in tended to pro vide suf fi cient information regarding the con figu ra tion and us age of the LPM/MCM-6117 board. WinSystems maintains a Technical Sup port Group to help an swer ques tions regarding configuration, usage, or pro gram ming of the board. For an swers to ques tions not adequately ad dressed in this man ual, contact Tech ni cal Support at (817) between 8AM and 5PM Cen tral Time. 2.2 ALI M6117 Processor/Chipset The LPM/MCM utilizes the ALI M6117C Processor/Chipset which provides a highly in te grated, high- performance back bone for full PC/AT com pati bil ity. The M6117C con tains not only a fully compatible 80386sx proc es sor but also the logic for DRAM and Bus state control as well as the standard com ple ment of 'AT' class peripherals in ter nally, in clud ing : 8 DMA Channels compatible with PC-AT 8237A DMA Controllers 15 Interrupt inputs compatible with master/slaved 8259 interrupt controllers Three 8254 compatible timer/counter channels A PC- AT compatible real time clock/calendar with CMOS RAM The functional units are 100% PC-AT compatible and are sup ported by the Award BIOS and Setup. Us ers desiring to ac cess these internal peripherals directly should ref er to any manu fac turer's ge neric lit era ture on the equivalent dis crete com po nent. There are a number of in ter nal registers within the M6117 Chipset sec tion that are used by the BIOS for control and configuration. Ref er to the I/O Map in Appendix A for port us age to avoid conflicts when adding external I/O de vices OPERATIONS MANUAL LPM/MCM-6117 Page 2-1

11 2.3 Real Time Clock Calendar Master Battery Enable Jumper J24 J24 3 o The LPM/MCM-6117 contains an onboard Clock/Calendar within the ALI M6117 chip. This clock is fully compatible with the MC146818A used in the origi nal PC-AT computers. This clock has a number of features including periodic and alarm in ter rupt ca pa bili ties. In ad di tion to the Time and Date keeping functions, the sys tem configuration is kept in CMOS RAM con tained within the clock sec tion. This RAM holds all of the setup in for ma tion regarding hard and floppy disk types, video type, shad ow ing, wait states, etc. Ref er to the sec tion on the Award BIOS Setup for com plete information on what is con fig ured via the CMOS RAM. It may be come nec es sary at some time to make the CMOS RAM forget its current con figu ra tion and to start fresh with fac tory defaults. This may be ac com plished by re mov ing power and the board from the sys tem. Then move the jumper from J and place on 2-3 for ap proxi mately 10 seconds. Replace the jumper to its origi nal po si tion, re in stall the board, power up, and re con fig ure the CMOS setup as desired. NOTE : J24 must always be re in stalled. The sys tem will not func tion correctly with out this jumper installed. 2.4 Keyboard Interface The LPM/MCM con tains an on board PC- AT style key board con trol ler. Connection is made through the Multi-I/O con nec tor at J1. An adapter ca ble, P/N CBL , is available from WinSystems to make ready access to all of the de vices ter mi nated at the Multi-I/O con nec tor. Us ers desiring custom con nec tions should refer to the Multi-I/O con nec tor pin defi ni tions given later in this man ual. Page 2-2 OPERATIONS MANUAL LPM/MCM

12 2.5 Serial Interface J o o o J12 3 o J15 3 o J17 3 o COM 3 and COM 4 output header (pinout shown on page 2-12) J o o o J o o o J o o o J o o o The LPM/MCM provides four RS- 232 serial channels on board, configurable as RS-42r RS- 485 with the ad di tion of optional driver ICs. The con figu ra tion op tions for each of the sup ported modes are shown on the fol low ing pages COM 1 - RS-232 COM1 is I/O mapped at 3F8H and utilizes a type UART contained in the Super- I/O chip. When used in RS-232 mode, COM1 is ter mi nated via the Multi-I/O con nec tor at J1. The con figu ra tion details and the pin definitions when used with the CBL cable are shown here : COM1 - DB9 PIN DEFINITIONS J8 3 o J13 3 o U2 - Installed U5 - Not Installed U6 - Not Installed 1 DCD 2 RX Data 3 TX Data 4 DTR 5 6 DSR 7 RTS 8 CTS 9 RI OPERATIONS MANUAL LPM/MCM-6117 Page 2-3

13 2.5.2 COM 2 - RS-232 COM2 is I/O mapped at 2F8H and util izes a type UART con tained in the Super- I/O chip. When used in RS- 232 mode, COM2 is terminated via the multi-i/o con nec tor at J1. The configuration de tails and the pin definitions, when used with the CBL cable, are shown here : COM2 - DB9 PIN DEFINITIONS J9 3 o J16 3 o COM 3 - RS-232 U9 - Installed U11 - Not Installed U12 - Not Installed 1 DCD 2 RX Data 3 TX Data 4 DTR 5 6 DSR 7 RTS 8 CTS 9 RI COM3 is I/O mapped at 3E8H and utilizes a type UART con tained in the 16C532 companion chip. When used in RS- 232 mode, COM3 is terminated via the con nec tor at J6. The con figu ra tion de tails and the pin definitions, when used with the CBL cable, are shown here : COM3 - DB9 PIN DEFINITIONS J12 3 o J14 3 o U4 - Installed U7 - Not Installed U8 - Not Installed 1 DCD 2 RX DATA 3 TX DATA 4 DTR 5 6 DSR 7 RTS 8 CTS 9 RI COM 4 - RS-232 COM4 is I/O mapped at 2E8H and utilizes a type UART con tained in the 16C532 companion chip. When used in RS- 232 mode, COM4 is terminated via the con nec tor at J6. The con figu ra tion de tails and the pin definitions, when used with the CBL cable, are shown on the following page: Page 2-4 OPERATIONS MANUAL LPM/MCM

14 COM4 - DB9 PIN DEFINITIONS J15 3 o J17 3 o U10 - Installed U13 - Not Installed U14 - Not Installed 1 DCD 2 RX DATA 3 TX DATA 4 DTR 5 6 DSR 7 RTS 8 CTS 9 RI COM 1 RS-422 RS-422 sig nal levels are sup ported on any, or all serial chan nels, with the in stal la tiono f the optional Chip Kit WinSystems' part number CK This kit provides the driver ICs nec es sary for a single channel of RS-422. If two channels of RS- 422 are required then two kits will be needed. RS- 422 is a 4- wire point-to-point full- duplex interface al low ing much longer cable runs than are pos si ble than with RS-232. The differential trans mit ter and receiver twisted-pairs of fer a higher degree of noise im mu nity. RS- 422 usually require s that the lines be ter mi nated at both ends. The following il lus tra tions show the correct jump er ing, driver IC in stal la tion, termination resistor location, and I/O con nec tor pin defi ni tions for each of the COM 1 channels when used in RS-422 mode J8 3 o J13 3 o U2 - Not Installed U5 - Installed U6 - Installed COM1 - DB9 PIN DEFINITIONS 1 N/A 2 TX+ 3 TX- 4 N/A 5 6 RX+ 7 RX- 8 N/A 9 N/A VCC R5 RX+ RS-422 NOTE : When used in RS- 422 mode, the transmitter must be enabled by setting the RTS bit in the Modem Con trol Register (Bit1). R4 R3 RX OPERATIONS MANUAL LPM/MCM-6117 Page 2-5

15 2.5.6 COM 2 RS-422 RS-422 sig nal levels are sup ported on any, or all serial chan nels, with the in stal la tiono f the optional Chip Kit WinSystems' part number CK This kit provides the driver ICs nec es sary for a single channel of RS-422. If two channels of RS- 422 are required then two kits will be needed. RS- 422 is a 4- wire point-to-point full- duplex interface al low ing much longer cable runs than are pos si ble than with RS-232. The differential trans mit ter and receiver twisted-pairs of fer a higher degree of noise im mu nity. RS- 422 usually require s that the lines be ter mi nated at both ends. The following il lus tra tions show the correct jump er ing, driver IC installation, termination resistor locations, and I/O connector pin defi ni tions for each of the COM 2 channels when used in RS-422 mode. J9 3 o J16 3 o U9 - Not Installed U11 - Installed U12 - Installed COM2 - DB9 PIN DEFINITIONS 1 N/A 2 TX+ 3 TX- 4 N/A 5 6 RX+ 7 RX- 8 N/A 9 N/A VCC R11 R10 R9 RX+ RX- RS-422 NOTE : When used in RS- 422 mode, the transmitter must be enabled by setting the RTS bit in the Modem Con trol Register (Bit1). Page 2-6 OPERATIONS MANUAL LPM/MCM

16 2.5.7 COM 3 RS-422 RS-422 sig nal levels are sup ported on any, or all serial chan nels, with the in stal la tiono f the optional Chip Kit WinSystems' part number CK This kit provides the driver ICs nec es sary for a single channel of RS-422. If two channels of RS- 422 are required then two kits will be needed. RS- 422 is a 4- wire point-to-point full- duplex interface al low ing much longer cable runs than are pos si ble than with RS-232. The differential trans mit ter and receiver twisted-pairs of fer a higher degree of noise im mu nity. RS- 422 usually require s that the lines be ter mi nated at both ends. The following il lus tra tions show the correct jump er ing, driver IC installation, and I/O con nec tor pin defi ni tions for each of the channels when used in RS- 422 mode. J12 3 o J14 3 o U4 - Not Installed U7 - Installed U8 - Installed COM3 - DB9 PIN DEFINITIONS 1 N/A 2 TX+ 3 TX- 4 N/A 5 6 RX+ 7 RX- 8 N/A 9 N/A VCC R17 R19 R21 RX+ RX- RS-422 NOTE : When used in RS- 422 mode, the transmitter must be enabled by setting the RTS bit in the Modem Con trol Register (Bit1) OPERATIONS MANUAL LPM/MCM-6117 Page 2-7

17 2.5.8 COM 4 RS-422 RS-422 sig nal levels are sup ported on any, or all serial chan nels, with the in stal la tiono f the optional Chip Kit WinSystems' part number CK This kit provides the driver ICs nec es sary for a single channel of RS-422. If two channels of RS- 422 are required then two kits will be needed. RS- 422 is a 4- wire point-to-point full- duplex interface al low ing much longer cable runs than are pos si ble than with RS-232. The differential trans mit ter and receiver twisted-pairs of fer a higher degree of noise im mu nity. RS- 422 usually require s that the lines be ter mi nated at both ends. The following il lus tra tions show the correct jump er ing, driver IC in stal la tion, termination resistor location, and I/O con nec tor pin defi ni tions for each of the channels when used in RS- 422 mode. J15 3 o J17 3 o U10 - Not Installed U13 - Installed U14 - Installed COM4 - DB9 PIN DEFINITIONS 1 N/A 2 TX+ 3 TX- 4 N/A 5 6 RX+ 7 RX- 8 N/A 9 N/A VCC R22 R24 R26 RX+ RX- RS-422 NOTE : When used in RS- 422 mode, the transmitter must be enabled by setting the RTS bit in the Modem Con trol Register (Bit1). Page 2-8 OPERATIONS MANUAL LPM/MCM

18 2.5.9 RS-485 Configuration The RS- 485 multi- drop in ter face is sup ported on all se rial chan nels with the installation of the optional Chip Kit Win Sys tems' part number CK A sin gle kit is sufficient to configure two of the channels for RS-485. RS-485 is a 2- wire multi- drop in ter face where only one sta tion at a time talks (transmits) while all others listen (re ceiv e). RS-485 usually requires the twisted line-pair be terminated at each end of the run. The fol low ing il lus tra tions show the cor rect jump er ing, driver IC in stal la tion, and I/O con nec tor pin- out for each of the channels when used in RS- 485 mode COM 1 RS-485 J8 3 o J13 3 o Normal RS-485 Operation is achieved by jumpering J13 pins 1-2. For RS-485 with Echo-back jumper pins 2-3 U2 - Not Installed U5 - Not Installed U6 - Installed COM1 - DB9 PIN DEFINITIONS 1 N/A 2 TX+/RX+ 3 TX-/RX- 4 N/A 5 6 N/A 7 N/A 8 N/A 9 N/A VCC R8 R7 R6 TX/RX+ TX/RX- RS-485 NOTE : Because RS- 485 uses a sin gle twisted- pair, all trans mit ters are con nected in parallel. Only one station at a time may transmit or have its transmitter enabled. The transmitter Enable/Disable is con trolled in soft ware us ing bit 1 in the Mo dem Con trol Register (RTS). When RTS is set, the trans mit ter is en abled, and when cleared (the normal state) the trans mit ter is dis abled and the re ceiver is enabled. Note that it is necessary to al low some minimal set tling time after ena bling the trans mit ter bef ore trans mit ting the first char ac ter. Like wise, fol low ing a transmission, it is necessary to be sure that all characters have been completely shifted out of the UART (Check Bit 6 in the Line Status Reg is ter) bef ore dis abling the trans mit ter to avoid chop ping off the last char ac ter OPERATIONS MANUAL LPM/MCM-6117 Page 2-9

19 COM 2 RS-485 J9 3 o J16 3 o Normal RS-485 Operation is achieved by jumpering J16 pins 1-2 For RS-485 with Echo-back jumper pins 2-3 U9 - Not Installed U11 - Not Installed U12 - Installed COM2 - DB9 PIN DEFINITIONS 1 N/A 2 TX+/RX+ 3 TX-/RX- 4 N/A 5 6 N/A 7 N/A 8 N/A 9 N/A VCC R14 R13 R12 TX/RX+ TX/RX- RS-485 NOTE : Because RS- 485 uses a sin gle twisted- pair, all trans mit ters are con nected in parallel. Only one station at a time may transmit or have its transmitter enabled. The transmitter Enable/Disable is con trolled in soft ware us ing bit 1 in the Mo dem Con trol Register (RTS). When RTS is set, the trans mit ter is en abled, and when cleared (the normal state) the trans mit ter is dis abled and the re ceiver is enabled. Note that it is necessary to al low some minimal settling time after ena bling the trans mit ter bef ore trans mit ting the first char ac ter. Like wise, fol low ing a transmission, it is necessary to be sure that all characters have been completely shifted out of the UART (Check Bit 6 in the Line Status Reg is ter) bef ore dis abling the trans mit ter to avoid chop ping off the last char ac ter. Page 2-10 OPERATIONS MANUAL LPM/MCM

20 COM 3 RS-485 J12 3 o Normal RS-485 Operation is achieved by jumpering J14 pins 1-2. For RS-485 with Echo-back jumper pins 2-3 R20 R16 R18 VCC J14 3 o TX/RX+ TX/RX- U4 - Not Installed U7 - Not Installed U8 - Installed COM3 - DB9 PIN DEFINITIONS 1 N/A 2 TX+/RX+ 3 TX-/RX- 4 N/A 5 6 N/A 7 N/A 8 N/A 9 N/A RS-485 NOTE : Because RS- 485 uses a single twisted- pair, all trans mit ters are con nected in par al lel. Only one sta tion at a time may transmit or have its trans mit ter en abled. The trans mit ter En able/dis able is con trolled in soft ware using bit 1 in the Mo dem Con trol Register (RTS). When RTS is set, the trans mit ter is en abled, and when cleared (the normal state) the trans mit ter is disabled and the receiver is enabled. Note that it is nec es sary to allow some minimal set tling time after ena bling the transmitter bef ore trans mit ting the first char ac ter. Like wise, fol low ing a trans mis sion, it is nec es sary to be sure that all char ac ters have been com pletely shifted out of the UART (Check Bit 6 in the Line Status Reg is ter) before disabling the transmitter to avoid chop ping off the last char ac ter OPERATIONS MANUAL LPM/MCM-6117 Page 2-11

21 COM 4 RS-485 J15 3 o J17 3 o Normal RS-485 Operation is achieved by jumpering J17 pins 1-2. For RS-485 with Echo-back jumper pins 2-3 U10 - Not Installed U13 - Not Installed U14 - Installed COM4 - DB9 PIN DEFINITIONS 1 N/A 2 TX+/RX+ 3 TX-/RX- 4 N/A 5 6 N/A 7 N/A 8 N/A 9 N/A VCC R27 R25 R23 TX/RX+ TX/RX- RS- 485 NOTE : Be cause RS- 485 uses a sin gle twisted- pair, all trans mit ters are connected in parallel. Only one sta tion at a time may trans mit or have its transmitter enabled. The transmitter Enable/Disable is con trolled in software us ing bit 1 in the Modem Con trol Reg is ter (RTS). When RTS is set, the trans mit ter is en abled, and when cleared (the nor mal state) the transmitter is disabled and the receiver is enabled. Note that it is nec es sary to al low some minimal settling time af ter ena bling the trans mit ter before trans mit ting the first character. Likewise, following a transmission, it is nec es sary to be sure that all char ac ters have been com pletely shifted out of the UART (Check Bit 6 in the Line Status Reg is ter) before dis abling the trans mit ter to avoid chop ping off the last char ac ter COM3/COM4 Output Header COM3 and COM4 are ter mi nated at J6. An adapter ca ble is avail able from WinSystems (P/N CBL-173-1), which adapts J6 to two standard DB9M con nec tors. The pin defi ni tions for J6 are shown here : J6 COM3 DCD COM3 RX COM3 TX COM3 DTR COM4 DCD COM4 RX COM4 TX COM4 DTR o 2 3 o o4 5 o o6 7 o o8 9 o o 10 1 o o o o o o o o o 20 COM3 DSR COM3 RTS COM3 CTR COM3 RI N/C COM4 DSR COM4 RTS COM4 CTS COM4 RI N/C Page 2-12 OPERATIONS MANUAL LPM/MCM

22 2.6 Parallel Printer Interface J23 3 o J o o o Optional ECP configuration jumpers J23 and J26. The LPM/MCM sup ports a stan dard par al lel printer port. An op tional con figu ra tion is avail able with a par al lel port ca pa ble of en hanced EPP and ECP op era tions. The par al lel port is I/O mapped at 278H and is ter mi nated at the Multi-I/O con nec tor J1. The pin definitions for the par al lel port con nec tor DB-25, when used with th e CBL cable, is shown be low : STROBE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ACK BUSY PE SLCT o 14 o 15 3 o o 16 4 o o 17 5 o o 18 6 o o 19 7 o o 20 8 o o 21 9 o o o o 23 1 o 24 1 o o AUTOFD ERROR INIT SLIN ECP DMA Configuration When the optional en hanced par al lel port is used in an ECP configuration, J23 and J26 are used to configure the DMA channel to be used for ECP trans fers. DMA Channel r Chan nel 3 is selectable as shown below : J23 J26 J23 J26 3 o 3 o 3 o 3 o DMA CHANNEL 1 DMA CHANNEL OPERATIONS MANUAL LPM/MCM-6117 Page 2-13

23 2.7 Speaker/Sound Interface The LPM/MCM-6117 util izes a high-impedance, piezo- type de vice for audio output. BIOS beep codes, error signaling, or user- defined tones can be pre sented via this device. 2.8 PC/104 Bus interface The LPM/MCM sup ports I/O expansion through the stan dard PC/104 con nec tors at J19 and J20. The LPM/MCM-6117 sup ports both 8- bit and 16- bit PC/104 modules. The PC/104 con nec tor pin defi ni tions are provided here for reference. J19 J20 RESET +5V IRQ9-5V DRQ2-12V 0WS +12V MEMW MEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE +5V OSC B o A1 B o A2 B3 o o A3 B4 o o A4 B5 o o A5 B6 o o A6 B7 o o A7 B8 o o A8 B9 o o A9 B10 o o A10 B1 o A11 B1 o A12 B13 o o A13 B14 o o A14 B15 o o A15 B16 o o A16 B17 o o A17 B18 o o A18 B19 o o A19 B20 o o A20 B A21 B2 o A22 B23 o o A23 B24 o o A24 B25 o o A25 B26 o o A26 B27 o o A27 B28 o o A28 B29 o o A29 B30 o o A30 B3 o A31 B3 o A32 IOCHK BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 KEY C0 o o D0 C o D1 C o D2 C3 o o D3 C4 o o D4 C5 o o D5 C6 o o D6 C7 o o D7 C8 o o D8 C9 o o D9 C10 o o D10 C1 o D11 C1 o D12 C13 o o D13 C14 o o D14 C15 o o D15 C16 o o D16 C17 o o D17 C18 o o D18 C19 o o D19 MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 VCC MASTER Page 2-14 OPERATIONS MANUAL LPM/MCM

24 2.9 Floppy Disk Interface The LPM/MCM-6117 sup ports up to 2 stan dard 3 1/2" or 5 1/4" PC compatible floppy disk drives. The drives are con nected via the I/O con nec tor at J10. Note that the interconnect cable to the drives is a standard floppy I/O ca ble used on desktop PCs. The cable must have the twisted sec tion prior to the drive A: po si tion. The pin definitions for the J10 con nec tor are shown here for reference. J10 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o o o o o o o o o o o o o o o 30 3 o o o 34 RPM/LC N/C N/C INDEX MTR0 DRV1 DRV0 MTR1 DIR STEP WDATA WGATE TRK0 WPRT RDATA HDSEL DSKCHG 2.10 IDE Hard Disk Interface The LPM/MCM-6117 sup ports standard IDE fixed disks through the I/O con nec tor at J28. A red activity LED is present at D1. The pin definitions for the J28 con nec tor are shown here : RESET D7 D6 D5 D4 D3 D2 D1 D0 IOW IOR N/C N/C INTRQ A1 A0 HDCS0 N/C J28 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o o o o o o o o o o o o o o o 30 3 o o o o o o o o o 40 D8 D9 D10 D11 D12 D13 D14 D15 N/C ALE IOCS16 N/C A2 HDCS OPERATIONS MANUAL LPM/MCM-6117 Page 2-15

25 2.11 Watchdog Timer Configuration J5 3 o J22 3 o J24 3 o The LPM/MCM board fea tures a power- on volt age de tect and a powerdown/power brown-out reset circuit to protect mem ory and I/O from faulty CPU operation during pe ri ods of il le gal volt age levels. This su per vi sory circuitry also features a wa tch dog timer which can be used to guard against soft ware lock ups. An in ter nal self- timer with a pe ri od of 1.5 sec onds will, when en abled, reset the CPU if the watch dog has not been serv iced (pet ted) within the al lot ted time. There are three watch dog op era tional modes available on the LPM/MCM With no jumper installed on J22, the watch dog is totally dis abled and can never re set the CPU. When J22 is jumpered pins 2-3 the watch dog circuit is per ma nently enabled and timing be gins im me di ate ly with power- on. This mode is NOT com pat i ble with the Award BIOS or with MS-DOS but is avail able for directly em bed ded code that takes the place of the BIOS. The watch dog must be accessed at least every 1.5 seconds or a re set will occur. Petting in this mode is ac com plished by writing to I/O port 1EEH with an al ter nat ing 1 and 0 value. The al ter nate mode of operation is via soft ware enable/disable control. This mode is set by jumpering J22 pins 1-2. In this mode the watch dog timer powers-up disabled and must be en abled in soft ware before tim ing will begin. Ena bling is ac com plished by writing a 1 t o I/O port 1EEH. Writ ing a 0 to I/O port 1EEH will dis able the watchdog. After enabling, the watchdog must be serv iced at least every 1.5 seconds or a re set will oc cur. The pet ting is ac com plished by simply writ ing any value to I/O port 1EFH. This mode of operation can be used with the BIOS and DOS provided that the watch dog is disabled before mak ing any ex ten sive BIOS or DOS calls, especially video or disk I/O calls, which in some cases could ex ceed the 1.5 seconds al lowed. The draw back to this mode is that a lockup dur ing the time the watch dog is dis abled will not allow for auto-recovery but will re quire an ex ter nal sourc e for a re set. Page 2-16 OPERATIONS MANUAL LPM/MCM

26 2.12 Battery Select Control The LPM/MCM has an on board lith ium bat tery used to sus tain the Clock/Calendar CMOS setup for in for ma tion, and Solid State Disk in for ma tion when SRAMs are used. A mas ter battery en able jumper is pro vided at J24. With J24 un jumpered the battery is totally dis con nected and no battery volt age is supplied to any cir cuitry on the board. The Solid State Disk socket may be jumpered for battery backup when us ing SRAMs if desired. Refer to the Sili con Disk Configuration sec tion of this man ual for de tails. It may become nec es sary or de sir able at some time to erase the CMOS setup information due to in cor rect or undesirable settings which are caus ing an in abil ity to execute the setup uti l ity or improper operation. To re set the CMOS mem ory to fac tory de faults, re move the jumper from J24 (1-2), and temporarily short all 3 pins of J5. Restore jumper to J24 (1-2). This should result in the BIOS restoring de faults and prompt ing for setup dur ing the next boot. Ref er to sec tion 3, AWARD BIOS Configuration, for setup op tions and de tails STD-Bus Interface STD-Bus connector J29 J25 o 2 3 o o4 5 o o6 The LPM/MCM-6117 is compatible with the STD-8088/188 bus specification. Ven dor spe cific im ple men ta tion information is pro vided below. PIN 35 IOEXP is driven low for I/O access in the 100-1FFH I/O address range. This allows I/O cards supporting IOEXP but only decoding 8 address lines to be safely qualified into a known 256 address predecoded block. PIN 39 When J25 pins 1-3 (Factory default) are jumpered STD- BUS pin 39 acts as the MEMCS16 sig - nal used for dynamic 8-bit/16-bit bus sizing per the P16 STD-BUS standard practice for 16- bit memory ac - cessing. When J25 pins 3-5 are jumpered together, STD-BUS pin 39 assumes a pseudo STATUS1 usage. Some STD-BUS ven dor cards use the STATUS1 signal in place of the WR line for decoding purpo ses. When jumpered in this position the WR signal is gated onto PIN 39 allowing these cards to fun ction. PIN 40 When J25 pins 2-4 (factory default) are jumpered STD- BUS pin 40 acts as the IOCS16 sig nal used for dy namic 8-bit/16- bit bus sizing per the STD-BUS standard practice for 16-Bit I/O accessing. When J25 pins 4-6 are jumpered together. STD-BUS pin 40 assumes a pseudo STATUS0 usage. Some STD-BUS vendor cards use the STATUS0 signal in place of the RD line in their decoding. When jumpered in this po - sition the RD signal is gated onto pin 40 to allow usage of these cards OPERATIONS MANUAL LPM/MCM-6117 Page 2-17

27 2.14 Interrupt Routing J21 Interrupt routing header o o o o o o o o o o J3 J21 36 o o o o 33 3 o o o o o o o o o 23 2 o o o o o o o o o 13 1 o o o9 8 o o 7 6 o o5 4 o o3 o1 J3 over the top (OTT) interrupt connector All interrupt inputs are routed to the appropriate PC/104 bus pins as shown ear lier in the PC/104 bus interface sec tion. Onboard pe riph er als, Se rial, Par al lel, and Disk are routed to their typi cal in ter rupt in puts us ing the jumper block at J21. The block al lows disconnecting or re rout ing of the onboard pe riph er als. An Over The Top (OTT) con nec tor is also pro vided at J3 to al low front-plane rout ing of additional in ter rupt inputs. The pi n defi ni tions for J3 and J21 are shown here : IRQ11 IRQ5 IRQ9 IRQ5 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 IRQ9 IRQ12 IRQ7 IRQ5 IRQ14 IRQ7 IRQ6 IRQ3 IRQ4 J21 36 o o o o 33 3 o o o o o o o o o 23 2 o o o o o o o o o 13 1 o o o9 8 o o 7 6 o o5 4 o o3 o1 Parallel I/O COM3 COM4 SPEAKER From J21 to J3 pin 1 From J21 to J3 pin 3 From J21 to J3 pin 5 From J21 to J3 pin 7 From J21 to J3 pin 9 STD Bus pin 37 STD Bus pin 44 STD Bus pin 46 STD Bus pin 50 HARD LPT1 FLOPPY COM2 COM1 To J21 pin 27 To J21 pin 25 To J21 pin 23 To J21 pin 21 To J21 pin 19 J3 o2 3 o o4 5 o o6 7 o o8 9 o o 10 Page 2-18 OPERATIONS MANUAL LPM/MCM

28 2.15 Silicon Disk Configuration J5 3 o J11 o2 3 o o4 5 o o6 7 o o8 9 o o 10 1 o o o 14 The LPM/MCM-6117 sup ports the use of EPROM, PEROM (Flash), SRAM, and the M- Systems DiskOnChip (DOC) de vices to be used as a Solid State Disk drive. Section 4 of this manual provides the nec es sary information for the generation and us age of the Silicon drive. This section docu ments the re quired hard ware con figu ra tions for the vari ous types of devices. The 32- pin JE DEC mem ory socket at U1 is used to contain the RAM, ROM, FLASH, or DOC de vice used for the disk. The Silicon disk array is mem ory mapped into a 32K byte hole at seg ment E800H and has an I/O con trol register at 1ECH Silicon Disk Mode There are two ba sic modes of Sili con Disk operation avail able on the LPM/MCM The first uses the onboard BIOS ex ten sion and supports the use of a 512K or 1M EPROM, 512K SRAM, or 512K AT MEL Flash device. The sec ond mode uses the M-Systems Disk On Chip de vice. The mode is con trolled via pins on jumper block at J11 as shown here : J11 J11 o2 3 o o4 5 o o6 7 o o8 9 o o 10 1 o o o 14 o2 3 o o4 5 o o6 7 o o8 9 o o 10 1 o o o 14 EPROM, SRAM, PEROM USAGE DOC USAGE OPERATIONS MANUAL LPM/MCM-6117 Page 2-19

29 Note : Jumpering for DOC mode with EPROM, RAM, or FLASH installed effectively acts to disable the Solid State Disk and simi larly when a DOC de vice is installed and the jumper is selected for standard de vices the DOC is dis abled Device Type Selection Bef ore us ing the Sili con Disk the proper de vice type must be selected by prop erly jump er ing J11. The sup ported de vice type jumperings are shown here : o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o 14 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o 14 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o 14 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o 14 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o K X 8 SRAM 512K X 8 EPROM 1M X 8 EPROM 512K X 8 PEROM DOC DEVICE Battery Backup Selection When us ing SRAM de vices and nonvolatile operation is de sired, bat tery backup can be se lected. J5 provides for selecting bat tery- backed vs. nor mal op er at ing mode as shown here: NOTE : Hav ing the jumper se lected for battery backup when us ing anything other than low-power-standby SRAMs (such as with EPROMs, or PEROMs) will re sult in the rapid drain ing of the onboard battery. J5 3 o Normal Operation J5 3 o Battery Backup Selected STD Bus V-Bat Enable The STD-Bus V-bat enable jumper is located at J27. When J27 is enabled, battery voltage is routed to pin 5 of the STD-Bus. When open, J27 isolates battery voltage to the backplane. An example of both is shown on the following page : Page 2-20 OPERATIONS MANUAL LPM/MCM

30 J27 J27 External Enabled V-Bat External Disabled V-Bat 2.16 Multi-I/O Connector The I/O to the se rial channels, the printer port, and keyboard are all ter mi nated via the con nec tor at J1. An adapter ca ble, part number CBL-247-1, is available from WinSystems to adapt to the conventional I/O con nec tors. The pin-out for J1 is shown here: COM1 - DCD COM1 - RXD COM1 - TXD COM1 - DTR COM1 - COM2 - DSR COM2 - RTS COM2 - CTS COM2 - RI LPT - STROBE LPT - PD0 LPT - PD1 LPT - PD2 LPT - PD3 LPT - PD4 LPT - PD5 LPT - PD6 LPT - PD7 LPT - ACK LPT - BUSY LPT - PE LPT - SLCT KEYBD - KEYBD - KDATA KEYBD - +5V J1 o2 3 o o 4 5 o o 6 7 o o8 9 o o 10 1 o o o o o o o o o o o o o o o o o 30 3 o o o o o o o o o 40 4 o o o o o o o o o 50 COM1 - DSR COM1 - RTS COM1 - CTS COM1 - RI COM2 - DCD COM2 - RXD COM2 - TXD COM2 - DTR COM2 - LPT - AUTOFD LPT - ERROR LPT - INIT LPT - SLCTIN LPT - LPT - LPT - LPT - LPT - LPT - LPT - LPT - KEYBD - KEYBD - KEYBD - CLK KEYBD - +5V 2.17 Status LED A red LED is populated on the board at D2 which can be used for any application specific purpose. The LED can be turned on in software by writ ing a 1 to I/O port 1EDH. The LED can be turned off by writ ing a 0 to 1EDH OPERATIONS MANUAL LPM/MCM-6117 Page 2-21

31 2.18 Parallel I/O J2 4 o o3 o1 Parallel I/O configuration jumper J2 The LPM/MCM-6117 util izes the WinSystems WS16C48 ASIC high-density I/O chip mapped at a base address of 120H. The first 24 lines are ca pa ble of fully latched event sens ing with sense po lar ity be ing soft ware pro gram ma ble. Two 50- pin con nec tors al low fo r easy mat ing with in dus try stan dard I/O racks. The pin out for the two connectors are shown on the next page Parallel I/O Connectors The 48 lines of par al lel I/O are ter mi nated through two 50- pin con nec tors at J7 and J4. The J7 con nec tor handles I/O ports 0-2 while J4 handles ports 3-5. The pin defi ni tions for J7 and J4 are shown on the following page. Page 2-22 OPERATIONS MANUAL LPM/MCM

32 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o o o o o o o o o o o o o o o 30 3 o o o o o o o o o 40 4 o o o o o o o o o 50 o 2 3 o o 4 5 o o 6 7 o o 8 9 o o 10 1 o o o o o o o o o o o o o o o o o 30 3 o o o o o o o o o 40 4 o o o o o o o o o Parallel I/O VCC En able The I/O con nec tors can pro vide +5 volts to an I/O rack or for mis cel la ne ous purposes by jump er ing J2. When J2 is jumpered +5 volts can pro vided at pin 49 of both J4 and J7. It the user's re spon si bil ity to limit cur rent to a safe value (less than 1A) to avoid damaging the CPU board. The jumper definitions for J2 are shown here. J2 J2 4 o o 3 o 1 4 o o 3 o 1 4 o o 3 o 1 4 o o 3 o 1 J7 VCC Disabled J7 VCC Enabled J4 VCC Disabled J4 VCC Enabled WS16C48 Reg is ter Definitions The LPM/MCM-6117 uses the Win Sys tems exclusive ASIC de vice, the WS16C48. This de vice pro vides 48 lines of digi tal I/O. There are 17 unique reg is ters within the WS16C48. The following ta ble summarizes the registers and the text that fol lows provides de tailso n each of the in ter nal registers OPERATIONS MANUAL LPM/MCM-6117 Page 2-23

33 I/O Address Offset Page 0 Page 1 Page 2 Page 3 00H Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O 01H Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O 02H Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O 03H Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O 04H Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O 05H Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O 06H Int_Pending Int_Pending Int_Pending Int_Pending 07H Page/Lock Page/Lock Page/Lock Page/Lock 08H N/A Pol_0 Enab_0 Int_ID0 09H N/A Pol_1 Enab_1 Int_ID1 0AH N/A Pol_2 Enab_2 Int_ID2 Reg is ter Details Port 0-5 I/O - Each I/O bit in each of the 6 ports can be in di vidu ally programmed for input or output. Writ ing a '0' to a bit po si tion causes the corresponding output pin to go to a High- Impedance state (pulled high by ex ter nal 10K ohm re sis tors). This al lows it to be used as an in put. When used in the input mode, a read re flects the inverted state of the I/O pin, such that a high on the pin will read as a '0' in the reg is ter. Writ ing a '1' to a bit positio n causes the output pin to sink cur rent (up to 12mA), effectively pull ing it low. INT_PEND ING - This read- only register re flects the com bined state of the INT_ID0 through INT_ID2 reg is ters. When any of the lower 3 bits are set, it indicates that an in ter rupt is pending on the I/O port cor re spond ing to the bit po si tion(s) that are set. Read ing this register al lows an In ter rupt Serv ice Routine to quickly determine if any in ter rupts are pending and which I/O port has a pend ing in ter rupt. PAGE/LOCK - This register serves two pur poses. The up per two bits select the reg is ter page in use as shown here: D7 D6 Page 0 0 Page Page Page Page 3 Bits 5-0 al low for locking the I/O ports. A '1' written to the I/O port po si tion will prohibi t fur ther writes to the cor re spond ing I/O port. POL0- POL2 - These reg is ters are ac ces si ble when page 1 is selected. They al low in ter rupt po lar ity se lec tion on a port- by- port and bit- by- bit ba sis. Writ ing a '1' to a bit Page 2-24 OPERATIONS MANUAL LPM/MCM

34 po si tion selects the rising edge de tec tion in ter rupts while writ ing a '0' to a bit posit ion se lects fal ling edge detection interrupts. ENAB0- ENAB2 - These registers are accessible when page 2 is selected. They al low for port- by- port and bit- by- bit ena bling of the edge detection interrupts. When set to a '1' t he edge detection in ter rupt is enabled for the cor re spond ing port and bit. When cleared to a '0' the bit's edge detection in ter rupt is disabled. Note that this register can be used to individually clear a pend ing interrupt by dis abling and reenabling the pending in ter rupt. INT_ID0 - INT_ID2 - These registers are ac ces si ble when page 3 is selected. They are used to identify cur rently pend ing edge interrupts. A bit when read as a '1' indicates that an edge of the po lar ity programmed into the cor re spond ing po lar ity register has been rec og nized. Note that a write to this register (value ignored) clears ALL of the pend ing in ter rupts in this reg is ter Flash BIOS Enable J18 o 2 The Flash BIOS enable jumper is located at J18. Enabling of the Flash BIOS is done by jumpering J18 as shown below. J18 o 2 Flash BIOS Disabled J18 o 2 Flash BIOS Enabled OPERATIONS MANUAL LPM/MCM-6117 Page 2-25

35 2.20 Jumper Connector Summary Jumper Description Page Reference Connector J1 Multi I/O Connector 2-21 J2 Parallel I/O Configuration 2-22 J3 Over the Top Interrupt Header 2-18 J4 Parallel I/O Connector 2-23 J5 Battery Backup Select 2-20 J6 COM3 COM4 Output Header 2-12 J7 Parallel I/O Connector 2-23 J8 COM1 Configuration Jumper 2-3 J9 COM2 Configuration Jumper 2-3 J10 Floppy Disk Connector 2-15 J11 Memory Socket Device Configuration 2-19 J12 COM3 Configuration Jumper 2-3 J13 COM1 Configuration Jumper 2-3 J14 COM3 Configuration Jumper 2-3 J15 COM4 Configuration Jumper 2-3 J16 COM2 Configuration Jumper 2-3 J17 COM4 Configuration Jumper 2-3 J18 Flash BIOS Enable 2-25 J19 8-bit PC/104 Bus Connector 2-14 J20 16-bit PC/104 Bus Connector 2-14 J21 Interrupt Header 2-18 J22 Watchdog Jumper 2-16 J23 Parallel Port DMA Jumper 2-13 J24 Master Battery Enable Jumper 2-2 J25 STD Pins 39 and 40 Configuration Jumpers 2-17 J26 Parallel Port DMA Request 2-13 J27 STD-Bus V-Bat Enable 2-20 J28 IDE Connector 2-15 J29 STD-Bus Connector 2-17 Page 2-26 OPERATIONS MANUAL LPM/MCM

36 3 AWARD BIOS Configuration 3.1 General Information The LPM/MCM-6117 comes equipped with a standard Award BIOS with Setup in ROM that allows us ers to modify the basic sys tem con figu ra tion. This type of information is stored in battery- backed CMOS RAM so that it retains Setup information when power is turned off. 3.2 Entering Setup To enter setup, power on the computer and press the DEL key im me di ate ly after the message Press Del to Enter Setup ap pears on the lower left of the screen. If the mes sage dis ap pears before you respond and you still wish to enter setup, restart the sys tem by turning it OFF and then ON or by pressing the RESET but ton, if so equipped, or by press ing the CTRL, ALT and DEL keys si mul ta ne ously. Alternately, under certain er ror con di tions of in cor rect setup the mes sage : Press F1 to continue or DEL to Enter Setup 3.3 Setup Main Menu The main menu screen is displayed on the fol low ing page. Each of the op tions will be dis cussed in this section. Use the arrow keys to high light the de sired se lec tion and press ENTER to enter the sub-menu or to execute the func tion selected OPERATIONS MANUAL LPM/MCM-6117 Page 3-1

37 ROM ISA BIOS ( ) CMOS SETUP UTILITY AWARD SOFTWARE, INC. STANDARD CMOS SETUP BIOS FEATURES SETUP CHIPSET FEATURES SETUP LOAD BIOS DEFAULTS LOAD SETUP DEFAULTS PASSWORD SETTING IDE HDD AUTO DETECTION SAVE & EXIT SETUP EXIT WITHOUT SAVING Esc : Quit F10 : Save & Exit Setup :Select Item (Shift) F2 : Change Color Time, Date. Hard Disk, Type Standard CMOS Setup The items in the Standard CMOS Setup menu are di vided into sev er al categories. Each cate gory may in clude one or more setup items. Use the arrow keys to highlight the item and then use the PgUp, PgDn, +, -, keys to select the de sired value for the item. Date The date format is <day>, <date>,<month>,<year> day = The day, from Sun to Sat, determined by the BIOS and is display only date = The date, from 1 to 31 (or the maximum for the current month) month = The month, Jan through Dec year = The year, from 1900 to 2099 Time The time for mat is <hour><minute><sec ond>. The time is cal cu lated on the 24- hour military- time clock, such that 1:00PM is 13:00:00. Page 3-2 OPERATIONS MANUAL LPM/MCM

38 Date (mm:dd:yy) : Wed, Sep Time (hh:mm:ss): 13 : 28 : 46 ROM PCI/ISA BIOS (ALIM6117) STANDARD CMOS SETUP AWARD SOFTWARE, INC. CYLS HEADS PRECOMP LANDZONE SECTORS MODE Drive C : User ( 849Mb) LBA Drive D: None ( 0Mb) Drive A : 1.44M, 3.5 in Drive B: None Video : EGA/VGA Halt On : No Errors Base Memory : 640K Extended Memory : 19456K Other Memory : 384K Total Memory: ESC : Quit : Select Item PU/PD/+/- : Modify F1 : Help (Shift) F2 : Change Color Drive C: type/drive D: type This category identifies the type of hard disk C: or hard disk D: that have been in stalled in the sys tem. There are 46 predefined types and a user definable type. Types 1-46 are predefined as shown in the fol low ing ta ble. Type Size Cyl in ders Heads Sec tors Precomp Landzone None None None None None None None Reserved Type Size Cylinders Heads Sectors Precomp Landzone OPERATIONS MANUAL LPM/MCM-6117 Page 3-3

39 None None None None None None none None None none None None None None None None None None None None None None None None 685 Press PgUp or PgDn to select a num bered hard disk type, or type the number and press En ter. Most manufacturers sup ply hard disk information with their drives that can be used to help iden tify the proper drive type. Mod ern IDE drives sel dom fall into the pre de fined types and are usually best handled with the user defined types. The user mode al lows for either manual or automatic entry of the drive pa rame ters, via the setup op tion IDE Auto Detect. If you de cide to create the user type manu ally, you must supply the required pa rame ters as to Cylinder count, Head count, Precomp Cylinder, Land ing Zone Cyl in der, and number of sectors per track. On fixed disks larger than 528MB it will also be necessary to choose the Logi cal Block Ad dress ing (LBA) mode if you wish the drive to be accessible as a single drive letter. If there is no hard disk in stalled, be sure to se lect type none. Page 3-4 OPERATIONS MANUAL LPM/MCM

40 Drive A: type/drive B: type This category identifies the type of floppy drives at tached as Drive A: or Drive B:. The choices are as fol lows : NONE 360K, 5.25 in. 1.2M, 5.25 in. 720K, 3.5 in. 1.44M, 3.5 in. 2.88M, 3.5 in. Note that the standard LPM/MCM board does not support the 2.88M floppy drives. If 2.88M floppy sup port is required, contact your Win Sys tems Ap pli ca tions En gi neer to in quire about this op tion. VIDEO This category speci fies the type of video adapter used for the pri mary sys tem moni tor that matches your video display board and monitor. The avail able choices are : EGA/VGA CGA40 CGA80 MONO It is recommended that if no dis play card is present that EGA/VGA be cho sen. Er ror Halt This category determines whether the sys tem will halt if a non- fatal error is detected during the power up self test. The choices are : No Errors : The system will not be stopped for any error that may be de tected. All Errors : Whenever the BIOS detects a non-fatal error the system will be stopped and a pro mpt will appear. All, but Keyboard : The system will not stop for a keyboard error, it will stop for all other e rrors. All, but Diskette : The system will only stop on Disk errors. All other will be ignored. All, but Disk/Key : All errors except disk and keyboard will result in a halt and a prompt OPERATIONS MANUAL LPM/MCM-6117 Page 3-5

41 Mem ory This category is dis play only and is determined by the BIOS POST (Power On Self Test). Base Memory The POST rou tines in the BIOS will determine the amount of base (or conventional) mem ory installed in the sys tem. The value of the base mem ory is typically 640K for sys tems with a Mega byte or greater of RAM installed. Extended Memory The BIOS determines how much extended mem ory is present dur ing the POST. This is the amount of mem ory lo cated above 1MB in the CPU's mem ory ad dress space. Other Mem ory This re fers to mem ory lo cated in the 640K to 1024K address space. This is mem ory that can be used for different applications. DOS may use this area to load de vice driv ers and TSRs to keep as much base memory free as pos si ble for ap pli ca tion programs. The most com mon use of this area is for Shadow RAM. 3.5 BIOS Features Setup Virus Warn ing This op tion when en abled, pro tects the boot sector and partition ta ble of the hard disk against un au thor ized writes through the BIOS. Any at tempt to alter these areas will result in an er ror message and a prompt for authorization of the activity. Quick Power On Self Test This op tion when enabled, speeds up the POST dur ing power up. If it is enabled, the BIOS will shorten and/or skip some test items during POST. Page 3-6 OPERATIONS MANUAL LPM/MCM