CS 152 Computer Architecture and Engineering

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1 CS 152 Computer Architecture and Engineering Lecture 7 Pipelining I John Lazzaro ( TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs152/

2 Last Time: ipod nano battery life ipod nano hours battery life (audio playback) ipod nano hours battery life (audio playback) What changed inside? Source: ifixit.com

3 Source: ifixit.com

4 Source: ifixit.com

5 ipod nano a C-shaped PC board, with a battery in the C opening. ipod nano battery lies on top of PC board. Source: ifixit.com

6 How? Small IC packages, fewer parts ipod nano 2006 ipod nano 2005 Source: arstechnica.com

7 Aluminum permits thinner case... Source: ilounge.com

8 Bill of Materials (BOM) - Cost of all parts Source: store.apple.com retail prices $74.90 $97.90 $ Distinction: Costs that are borne for each unit sold (like BOM) vs once-per-new-product costs (like R&D). BOM Source: Wedbush Morgan Securities

9 Last Time: Performance Equation Seconds Program Instructions Program Cycles Instruction Seconds Cycle Goal is to optimize execution time, not individual equation terms. Machines are optimized with respect to program workloads. The CPI of the program. Reflects the program s instruction mix. Clock period. Optimize jointly with machine CPI.

10 Today: Introduction to Pipelining How to apply the performance equation to our single-cycle CPU. Pipelining: an idea from assembly line production applied to CPU design Why pipelining is hard: data hazards, control hazards, structural hazards. Also: Introduction to Lab 3

11 Note: Reading is Fundamental... The book presentation of pipelined processors is sufficient to do Lab 3. These lectures are not. The lectures are a gentle introduction, to prepare you to read the book...

12 + Recall: Our single-cycle processor Challenge: Speed up clock while keeping CPI == 1 Seconds Program Instructions Program Cycles Instruction Seconds Cycle 0x4 CPI == 1 This is good. Slow. This is bad. D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U Data Memory Addr Dout Din WE MemToReg Ext

13 Recall: An R-format CPU design Decode fields to get : ADD $8 $9 $10 opcode rs rt rd shamt funct Logic op RegFile rs1 rs2 rd1 ws rd2 wd WE A L U

14 Reminder: How data flows after posedge PC Instr Mem + D Q Addr Data 0x4 Logic op RegFile rs1 rs2 rd1 ws rd2 wd WE A L U

15 Next posedge: Update state and repeat PC D Q RegFile rs1 rs2 rd1 ws rd2 wd WE

16 Observation: Logic idle most of cycle For most of cycle, ALU is either waiting for its inputs, or holding its output Ideal: a CPU architecture where each part is always working. 0x4 + D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U Data Memory Addr Dout Din WE MemToReg Ext

17 Inspiration: Automobile assembly line Assembly line moves on a steady clock. Each station does the same task on each car. The clock Car body shell Merge station Bolting station Car chassis

18 Inspiration: Automobile assembly line Simpler station tasks more cars per hour. Simple tasks take less time, clock is faster.

19 Inspiration: Automobile assembly line Line speed limited by slowest task. Most efficient if all tasks take same time to do

20 Inspiration: Automobile assembly line Simpler tasks, complex car long line! These lines go 24 x 7, and rarely shut down.

21 Lessons from car assembly lines Faster line movement yields more cars per hour off the line. Faster line movement requires more stages, each doing simpler tasks. To maximize efficiency, all stages should take same amount of time (if not, workers in fast stages are idle) Filling, flushing, and stalling assembly line are all bad news.

22 Key Analogy: The instruction is the car Pipeline Stage #1 Stage #2 Stage #3 Stage #4 Stage #5 Instruction Fetch IR IR IR IR + PC 0x4 Instr Mem Controls hardware in stage 2 Controls hardware in stage 3 Controls hardware in stage 4 Controls hardware in stage 5 D Q Addr Data Data-stationary control

23 + Example: Decode & Register Fetch Stage Pipeline Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch SUB R10, R9,R8 IR OR R7,R6,R5 IR ADD R4,R3,R2 IR 0x4 A sample program D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE Ext A M B ADD R4,R3,R2 OR R7,R6,R5 SUB R10,R9,R8 R s chosen so that instructions are independent - like cars on the line.

24 Performance Equation and Pipelining + Seconds Program Instructions Program Cycles Instruction Seconds Cycle D PC Instr Fetch Decode & Reg Fetch Stage #3 Q 0x4 Addr Instr Mem Data IR IR IR CPI == 1 Once pipe is fill, one instruction completes per cycle rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B Clock period is shorter Less work to do in each cycle To get shortest clock period, balance the work to do in each pipeline stage.

25 Hazards: An instruction is not a car... + Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch D PC Q 0x4 Addr Instr Mem Data OR R5,R4,R2 IR IR IR... wrong value of R4 fetched from RegFile, contract with programmer broken! Oops! rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B ADD R4,R3,R2 R4 not written yet... New sample program ADD R4,R3,R2 OR R5,R4,R2 An example of a hazard -- we must (1) detect and (2) resolve all hazards to make a CPU that matches ISA

26 Performance Equation and Hazards + Seconds Program Instructions Program Cycles Instruction Seconds Cycle D PC Instr Fetch Decode & Reg Fetch Stage #3 Q 0x4 Addr Instr Mem Data IR IR IR Some ways to cope with hazards makes CPI > 1 stalling pipeline rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B Added logic to detect and resolve hazards increases clock period Software slows the machine down Seymour Cray

27 + A (simplified) 5-stage pipelined CPU 1 2 IF Stage Instr Fetch ID/RF Stage Decode & Reg Fetch 3 EX Stage Execution 4 MEM Stage Memory 5 WB Write Back IR IR IR IR WE, MemToReg Mux,Logic op D PC Q 0x4 Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE A M A L U Y M Data Memory Addr Dout Din WE MemToReg R Ext B Welcome to Lab 3!

28 Sometimes, contract is a challenge + D PC IF Stage Instr Fetch Sample Program LW R4,0(R0) OR R5,R4,R2 Q 0x4 1 2 Addr Instr Mem Data IR ID/RF Stage Decode & Reg Fetch OR R5,R4,R2... but we haven t even started the load yet! Mux,Logic rs1 rs2 ws wd RegFile WE rd1 rd2 EX Stage Execution IR A M 3 LW R4, 0(R0) op A L U IR Y M IR WE, MemToReg Data Memory Addr Din 4 MEM Stage Memory Dout WE MemToReg R 5 WB Write Back Ext B One approach: change the contract!

29 From Lecture 1: Delayed Loads... Instruction Fetch Instruction Decode Operand Fetch Execute Fetch the load inst from memory opcode rs rt offset I-Format Decode fields to get : LW $1, ($2) Retrieve register value: $2 Compute memory address: + $2 Result Store Next Instruction CS 152 L1: The MIPS ISA Load memory address contents into: $1 Prepare to fetch instr that follows the LW in the program. Depending on load semantics, new $1 is visible to that instr, or not until the following instr ( delayed loads ).

30 + After we change the contract... D PC IF Stage Instr Fetch Sample Program LW R4,0(R0) OR R5,R4,R2 Q 0x4 1 2 Addr Instr Mem Data IR ID/RF Stage Decode & Reg Fetch OR R5,R4,R2... delayed load contract does not guarantee new R4 is seen. Mux,Logic rs1 rs2 ws wd RegFile WE rd1 rd2 EX Stage Execution IR A M 3 LW R4, 0(R0) op A L U IR Y M MEM Stage Memory IR WE, MemToReg Data Memory Addr Din 4 Dout WE MemToReg R 5 WB Write Back Ext B Only partially solves problem... Thursday we finish the story.

31 Administrivia: Upcoming deadlines... Friday 9/22: Lab 2 Xilinx Checkoff, in section or 3-5 PM, 125 Cory. Monday 9/25: Lab 2 final report due via the submit program, 11:59 PM. Lab 3 now available on the web site Thursday 9/28: At 11:59 PM via Lab 2 peer evaluations, and Lab 3 preliminary design document due.

32 Starting 9/28: Homework, Midterm, Lab Graded on effort Thursday review session. Will cover format, material, and ground rules for test. Midterm two weeks from today, in evening, no class that day. Lab 3 design doc, checkoffs, later in week...

33 Pipelining Your Processor Lab 3 Introduction

34 Week 1 for Lab 3: Pipelining Processors

35 Week 1 for Lab 3: Pipelining Processors

36 Week 2: Hazard-Free Code on the Board A sample program ADD R4,R3,R2 OR R7,R6,R5 SUB R10,R9,R8 R s chosen so that instructions are independent - like cars on the line.

37 Week 3: Run TA s Hard Tests on Xilinx New sample program ADD R4,R3,R2 OR R5,R4,R2 An example of a hazard -- we must (1) detect and (2) resolve all hazards to make a CPU that matches ISA

38 Next 2 Lectures: Pipelining details... Control, Hazards, Forwarding

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