SCope: Efficient HdS simulation for MpSoC with NoC
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1 SCope: Efficient HdS simulation for MpSoC with NoC Eugenio Villar Héctor Posadas University of Cantabria Marcos Martínez DS2
2 Motivation The microprocessor will be the NAND gate of the integrated systems in 2010 Alan Naumann, President and CEO, CoWare DATE 07 Infrastructure Network on Chip Memory SW code Processor Processor 1,1 1,2 1,n BUS º 2,1 2,2 2,n Applicationspecific HW Network Interface Other Peripherals n,1 n,2 n,n
3 Motivation Simulation will remain a fundamental design tool Functional validation Performance estimation Design-space exploration Design verification
4 Motivation Current ISS(+TLM) is too slow for Functional verification Performance estimation Design-space exploration Only valid for final design verification ISS+RTL(logic)
5 Motivation SW execution is only valid for Initial functional validation Temporal behavior missed SW code High-level HW model SW code 1,1 1,2 1,n SW code º 2,1 2,2 2,n SW code n,1 n,2 n,n SW code
6 Contents SCope description Goals Features Platform model Power estimation Application example Conclusions
7 SCope: Goal HW/SW simulation platform for MpSoC with NoC Performance estimation Power estimation Fast As accurate as possible
8 SCope: Features SW source-code simulation Two orders of magnitude faster than ISS Abstract RTOS model Abstraction of the microprocessor Timed simulation Performance estimation Power consumption estimation
9 SCope: Features (cont.) HW TLM(RTL) models HW/SW communication Interruptions Drivers TLM2 Bus model DMA NoC Interface
10 SCope: Platform model Application Code Task 1... Task n POSIX API Packages SW Memory Proc. 1 Drivers Proc. 2 Proc. n Memory Applicationspecific HW Bus 1 Net Per. Net Per. Bus n Peripheral HW
11 SCope: RTOS modeling SW Platform Applic. Code T1 T2... Tn Communication Interruptions OS API (POSIX) Spec. I/O º Synchronization Module Loading OS Core Low-level HAL External Packs (TCP/IP) Drivers Concurrency OS API Memory management Scheduling Low-level HAL File system Devices BUS Access
12 PERFidiX: HAL Modeling HW/SW communication Drivers Linux functions for drivers development File system control and device management Bus Access Reading and writing memory and peripherals Interruptions IRQ from HW platform Interrupt managers and masks
13 PERFidiX: SW Packages POSIX-based RTOS allow inclusion of standard packages Stack TCP/IP: lwip Reduced memory requirements Several protocols implemented IP, ICMP, UDP, TCP, DHCP, ARP,... Uses a Ethernet driver model Connected using the network simulator Work in progress
14 PERFidiX: Execution time and Energy estimation Dynamic Time & Power Estimation Operation Time Total Energy Total OPERATOR Time Energy a = b + d ; 2+7 us 9 us 2+5 uj 7 uj = 2 us 2 uj c = a*b ; 2+68 us 79 us 2+40 uj 49 uj + 7 us 5 uj d = a; if ( c < 0 ) a = c + 1 ; 2 us us 2+7 us 81 us 119 us 128 us 2 uj uj uj 51 uj 81 uj 88 uj * < 68 us 20 us 40 uj 20 uj Total seg. 128 us 687 mw IF 18 us 10 uj
15 PERFidiX: Power estimation Standard RISC processors exhibit stable power consumption per instruction Dynamic simulation allows estimating energy consumption number of assembler instructions executed energy cost per instruction Power estimation energy/execution times Adaptive dynamic voltage-frequency scaling
16 SCope: BUS modeling Data Transfers payload (faster than word by word) Interruptions TLM2 Models Several masters Several slaves Bus chaining SW Applic SW Applic Master (Proc. IF) Master (Proc. IF) BUS TLM2 Memory Map Bandwidth - Priorities Interrupt Generic BUS IF. Generic BUS IF. HW Slave HW Slave Stop / Abort DMA
17 SCope: Generic peripheral interface Bus protocol management Implements transport & send interrupt Manages Stop and Abort operations Waits corresponding time bandwidth and delay Integrated using inheritance Allows modifying protocol management in a specific peripheral Protocol functionality integrated in the peripheral Declare bus ports automatically (SC_EXPORT)
18 SCope: Specific Peripheral models Network Interface Connects the bus and the NoC model Acts as slave Informs the processor through interrupts DMA Master / Slave Moves payloads between other peripherals Memory Allows modeling bus loads of data transfers processor-memory and DMA-memory
19 SCope: Network Modeling Network on Chip simulator: Sicosys University of Cantabria (UC-ATC) Based on models of the NoC components Several NoC configurations Integrated as a SystemC Thread Computes when packages are in the NoC Otherwise Stopped
20 Example: Vocoder GSM Two nodes connected through a NoC Coder Decoder 1 2 Memory Proc. Proc. Memory BUS BUS I/O NoC IF. NoC IF. I/O NoC
21 Example: Platform model Coder Decoder NoC Driver Memory Memory Bus If. Proc. If. Proc. If. Bus If. 1 Data Data Irq Irq Data 2 Data BUS BUS Data Irq Data Irq Irq Data Irq Data Bus If. Bus If. Bus If. Bus If. I/O NoC Card NoC Card I/O
22 Example: Performance Analysis SW execution times Thread statistics Power consumption Bus statistics Contentions Conflicts Network Delays Latencies
23 Example: Performance Analysis
24 Conclusions SystemC powerful framework for complex SoC with NoC modeling SCope Multiprocessing SW simulation SW power consumption Platform modeling Bus, DMA, AS-HW, Memory, NoC IF, NoC simulation Sicosis
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