Description OUT0 1 OUTA1 OUTA1 2 OUTA2 3 OUTA3 OUTA4 OUTB1 6 OUTB2 7 OUTB2 OUTB3 OUTB4. All trademarks are property of their respective owners.
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1 Features Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input Spread spectrum compatible Operates at 3.3V V DD Space-saving Package: (Pb-free & Green available) - 16-Pin TSSOP (L) - 16-Pin SOIC (W) Description The PI6C2409-1H is a PLL based, zero-delay buffer, with the ability to distribute nine outputs of up to 133 MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. PI6C2409-1H has two banks of four outputs that can be controlled by the selection inputs, SEL1 & SEL2. It also has a power sparing feature: when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all outputs are referenced from CLKIN. PI6C2409-1H is available in high drive and industrial environment versions. An internal feedback on OUT0 is used to synchronize the outputs to the input; the relationship between loading of this signal and the outputs determines the input-output delay. PI6C2409-1H are characterized for both commercial and industrial operation Block Diagram Pin Configuration CLKIN SEL1 SEL2 PI6C2409-1H Decode Logic PLL MUX OUT0 1 OUTA1 OUTA1 2 OUTA2 OUTA2 3 OUTA3 VDD 4 OUTA4 OUTB1 OUTB2 OUTB3 OUTB4 CLKIN 5 OUTB1 6 OUTB2 7 SEL Pin W, L OUT0 OUTA4 OUTA3 VDD OUTB4 OUTB3 SEL /02/15
2 Input Select Decoding SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source (OUT0) State 3-State PLL ON 0 1 PLL 3-State PLL ON 1 0 CLKIN CLKIN CLKIN OFF 1 1 PLL PLL PLL ON PLL Pin Description Pin Signal Description 1 CLKIN Input clock reference frequency (weak pull-down) 2, 3, 14, 15 OUTA[1-4] Clock outputs, Bank A 4, 13 VDD 3.3V supply 5, 12 Ground 6, 7, 10,11 OUTB[1-4] Clock outputs, Bank B 8 SEL2 Select input, bit 2 (weak pull-up) 9 SEL1 Select input, bit 1 (weak pull-up) 16 OUT0 Clock Output, internal PLL feedback Zero-Delay and Skew Control CLKIN Input to OUTx Delay vs. Difference in Loading between OUT0 pin and OUTx pins 800 CLKIN - Input to OUTx Delay (ps) PI6C2409-1H Output Load Difference: OUT0 Load - OUTx Load (pf) The relationship between loading of the OUT0 signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. 2
3 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Supply Voltage to Ground Potential V to +4.6V DC Input Voltage V to V DD +0.5V ESD Protection (Input) V min (HBM) Note: Stresses greater than those listed under MAXI- MUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Conditions (V CC = 3.3V ±0.3V) Parameter Description Min. Max. Units V DD Supply Voltage V Commercial Operating Temperature 0 70 T A ºC Industrial Operating Temperature Load Capacitance, below 100 MHz 30 C L Load Capacitance, from 100 MHz to 133 MHz - 15 pf C IN Input Capacitance - 7 DC Electrical Characteristics for Industrial Temperature Devices Parameters Description Test Conditions Min. Max. Units V IL Input LOW Voltage 0.8 V IH Input HIGH Voltage 2.0 I IL Input LOW Current V IN = 0V 50.0 I IH Input HIGH Current V IN = V DD 125 V OL Output LOW Voltage I OL = 12mA 0.4 V OH Output HIGH Voltage I OH = 12mA 2.4 Bypass, PLL OFF SEL1 = 0, SEL2 = I DD Unloaded outputs 100 MHz, Select inputs at Supply Current V DD or 62 Unloaded outputs 66 MHz, CLKIN 44 V µa V ma 3
4 AC Electrical Characteristics for Industrial Temperature Devices Parameters Name Test Conditions Min. Typ. Max. Units F O Output Frequency 30pF load pF load 133 MHz Duty Cycle (1) Measured at V DD/2, F OUT = MHz t DC 50 Duty Cycle (1) Measured at V DD /2V, F OUT <50MHz % t R Rise Time (1) Measured between 0.8V and 2.0V 1.5 t F Fall Time (1) Measured between 0.8V and 2.0V 1.5 ns t SK(O) Output to Output Skew (1) All outputs equally loaded 250 t 0 Delay, CLKIN Rising Edge to OUT0 Rising Edge (1) Measured at V DD /2 0 ±350 ps t SK(D) Device-to-Device Skew (1) Measured at V DD /2 on OUT0 pins of devices t SLEW Output Slew Rate (1) Measured between 0.8V & 2.0V on 1H device using Test Crt #2 1 V/ns t JIT Cycle-to-Cycle Jitter (1) Measured at MHz, loaded 30pF load 250 ps t LOCK PLL Lock Time (1) Stable power supply, valid clocks presented on CLKIN pin 1.0 ms Note: 1. See Switching Waveforms on page 6. DC Electrical Characteristics for Commercial Temperature Devices Parameters Description Test Conditions Min. Max. Units V IL Input LOW Voltage V IH Input HIGH Voltage V I IL Input LOW Current V IN = 0V - 50 I IH Input HIGH Current V IN = V DD µa V OL Output LOW Voltage I OL = 12mA V OH Output HIGH Voltage I OH = 12mA V Bypass, PLL off SEL1 = 0 SEL2 = Unloaded outputs, MHz, - 39 I DD Select inputs at V DD or ma Supply Current Unloaded outputs 100 MHz - 54 Select V DD or 4
5 AC Electrical Characteristics for Commercial Temperature Devices Parameters Description Test Conditions Min. Typ. Max. Units F O Output Frequency 30pF load pF load 133 MHz Duty Cycle (1) Measured at V DD/2, F O = MHz t DC 50 Duty Cycle (1) Measured at V DD /2V, F O <50 MHz % t R Rise Time (1) 1.5 Measured between 0.8V and 2.0V t F Fall Time (1) 1.5 ns t SK(O) Output to Output Skew (1) All outputs equally loaded 250 t 0 Delay, CLKIN Rising Edge to OUT0 Rising Edge (1) Measured at V DD /2 0 ±350 ps t SK(D) Device-to-Device Skew (1) Measured at V DD /2 on OUT0 pins of devices t SLEW Output Slew Rate (1) Measured between 0.8V & 2.0V on 1H device using Test Crt #2 1 V/ns t JIT Cycle-to-Cycle Jitter (1) Measured at MHz, loaded 30pF load 200 ps t LOCK PLL Lock Time (1) Stable power supply, valid clocks presented on CLKIN pin 1.0 ms Note: 1. See Switching Waveforms on page 6. 5
6 Switching Waveforms Duty Cycle Timing thigh tlow tdc = t high thigh+tlow All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V tr 2.0V 0.8V tf 0V 3.3V Output-Output Skew OUTPUT OUTPUT tsk(o) Device-Device Skew OUTPUT Device 1 OUTPUT Device 2 tsk(d) Input-Output Propagation Delay INPUT OUTPUT t0 0.1µF V DD 0.1µF V DD 1k-ohm CLK out CLK out OUTPUTS OUTPUTS CLOAD 1k-ohm 10pF 0.1µF V DD 0.1µF V DD 6
7 Packaging Mechanical: 16-Pin TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC MO-153F/AB 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 16-Pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1310 REVISION: F 7
8 Packaging Mechanical: 16-Pin SOIC (W) DATE: 06/15/12 DESCRIPTION: 16-Pin, 150mil Wide SOIC PACKAGE CODE: W DOCUMENT CONTROL #: PD-1004 REVISION: F Ordering Information Ordering Code Package Code Package Description Operating Range PI6C2409-1HLE L 16-pin, 173-mil Wide (TSSOP) Commercial PI6C2409-1HLEX L 16-pin, 173-mil Wide (TSSOP), Tape & Reel Commercial PI6C2409-1HLIE L 16-pin, 173-mil Wide (TSSOP) Industrial PI6C2409-1HLIEX L 16-pin, 173-mil Wide (TSSOP), Tape & Reel Industrial PI6C2409-1HWE W 16-pin, 150-mil Wide (SOIC) Commercial PI6C2409-1HWEX W 16-pin, 150-mil Wide (SOIC), Tape & Reel Commercial PI6C2409-1HWIE W 16-pin, 150-mil Wide (SOIC) Industrial PI6C2409-1HWIEX W 16-pin, 150-mil Wide (SOIC), Tape & Reel Industrial Notes: 1. Thermal characteristics can be found on the company web site at 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation
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Features ÎÎInput Clock Frequency up to 6 GHz Typical ÎÎMaximum Input Data Rate up to 12 Gbps Typical ÎÎ2 pairs of differential CML outputs ÎÎLow additive jitter, < 0.05ps (max) ÎÎInput accepts: CML, LVDS,
74ALVC132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and. and Outputs. General Description.
74ALC132 Low oltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6 Tolerant Inputs and General Description The ALC132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration
PI4IOE5V bit I 2 C-bus and SMBus low power I/O port with interrupt and reset
Features Operation power supply voltage from 2.3V to 5.5V 2-bit I 2 C-bus GPIO with interrupt and reset 5V tolerant I/Os Active Low interrupt output Active Low reset input Polarity inversion register Low
9P960. Pin Configuration. Recommended Application. Features/Benefits. Block Diagram ICS9P SSOP DATASHEET
DATASHEET DUAL CHANNEL DDRII/III ZER DELAY BUFFER 9P96 Recommended Application Dual DDR zero delay buffer Features/Benefits High performance, low jitter zero delay buffer I 2 C for functional and output
Wireless Access Point Server/Storage DIFF1 DIFF2
PCI-EXPRESS GEN 1, GEN 2, AND GEN 3 1:2 FAN-OUT CLOCK BUFFER Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant devices Two low-power PCIe clock outputs Supports Serial-ATA (SATA) at 100 MHz No termination
CD4023BC Buffered Triple 3-Input NAND Gate
CD4023BC Buffered Triple 3-Input NAND Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P- channel enhancement mode transistors.
ICS8543I. Features. General Description. Pin Assignment. Block Diagram LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543I General Description The ICS8543I is a low skew, high performance ICS 1-to-4 Differential-to-LVDS Clock Fan Buffer and a member of the family
PART OBSOLETE - USE PI3PCIE3242A
PART OBSOLETE - USE A 3.3V PCI Express 3.0 4 Channel 2x2 Exchange Switch Features ÎÎ4 Differential Channel 2x2 Exchange Switch ÎÎPCI Express 3.0 performance, 8.0 Gbps ÎÎBi-directional operation ÎÎLow Bit-to-Bit
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 16,384-BIT EPROM WITH I/O! 2048 Words x 8 Bits! Single + 5V Power Supply
Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3673
19-44 ; Rev 0; 2/09 E V A L U A T I O N K I T A V A I L A B L E Low-Jitter Frequency Synthesizer General Description The is a low-jitter frequency synthesizer that accepts two reference clock inputs and
16-megabit 2.5-volt or 2.7-volt DataFlash AT45DB161D
Features Single 2.5V - 3.6V or 2.7V - 3.6V Supply RapidS Serial Interface: 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 User Configurable Page Size 512 Bytes per Page 528 Bytes per Page
CD4010C Hex Buffers (Non-Inverting)
Hex Buffers (Non-Inverting) General Description The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical
Low Power Multiclock Generator with XO AK8137A
Low Power Multiclock Generator with XO AK8137A Features 25MHz Crystal Input One 25MHz-Reference Output Selectable Clock out Frequencies: - 100, 133, 166, 200MHz - 96MHz - 100MHz - 25MHz Low Jitter Performance
PI3VDP411LS. Digital Video Level Shifter from AC Coupled Digital Video Input to a DVI/HDMI Transmitter. Features. Description
Features ÎÎConverts low-swing AC coupled differential input to HDMI rev 1.3 compliant open-drain current steering Rx terminated differential output ÎÎHDMI level shifting operation up to 2.5Gbps per lane
USB1T1102 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
Universal Serial Bus Peripheral Transceiver with Voltage Regulator General Description This chip provides a USB Transceiver functionality with a voltage regulator that is compliant to USB Specification
PART. *EP = Exposed pad. LVDS IN+ IN- PCB OR TWISTED PAIR. Maxim Integrated Products 1
19-0849; Rev 1; 12/07 10-Bit LVDS Serializer General Description The serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data
Description. Features. Pin Configuration PI4IOE5V9539
16-bit I 2 C-bus and SMBus low power I/O port with interrupt and reset Features Operation power supply voltage from 2.3V to 5.5V 16-bit I 2 C-bus GPIO with interrupt and reset 5V tolerant I/Os Polarity
DS1233A 3.3V EconoReset
3.3V EconoReset www.maxim-ic.com FEATURES Automatically restarts microprocessor after power failure Monitors pushbutton for external override Internal circuitry debounces pushbutton switch Maintains reset
24C08/24C16. Two-Wire Serial EEPROM. Preliminary datasheet 8K (1024 X 8)/16K (2048 X 8) General Description. Pin Configuration
Two-Wire Serial EEPROM Preliminary datasheet 8K (1024 X 8)/16K (2048 X 8) Low-voltage Operation 1.8 (VCC = 1.8V to 5.5V) Operating Ambient Temperature: -40 C to +85 C Internally Organized 1024 X 8 (8K),
XRD8775 CMOS 8-Bit High Speed Analog-to-Digital Converter
CMOS 8-Bit High Speed Analog-to-Digital Converter April 2002-4 FEATURES 8-Bit Resolution Up to 20MHz Sampling Rate Internal S/H Function Single Supply: 5V V IN DC Range: 0V to V DD V REF DC Range: 1V to
24AA16/24LC16B. 16K I 2 C Serial EEPROM. Device Selection Table. Description: Features: Package Types. Block Diagram. Temp. Ranges.
6K I C Serial EEPROM Device Selection Table Part Number Features: Vcc Range Max. Clock Frequency Temp. Ranges A6.7-. 00 khz () I LC6B.-. 00 khz I, E Note : 00 khz for
Remote 16-bit I/O expander for Fm+ I 2 C-bus with interrupt and reset. Description
Remote 16-bit I/O expander for Fm+ I 2 C-bus with interrupt and reset Features Operation power supply voltage from 2.3V to 5.5V 16-bit remote I/O pins that default to inputs at powerup 1 MHz I 2 C-bus
Description. Block Diagram DDC_SCL DDC_SDA AUX+ AUX- TB_Rx_1(p) TB_Rx_1(n) CA_DET_Out. CA_DET_Out
10.3Gbps Thunderbolt and DisplayPort Switch Features ÎÎSupports 5.4Gbps for DisplayPort 1.2 and 10.3Gbps for Thunderbolt Electrical Standard ÎÎSupports DP and DP++ Configuration ÎÎSupports AUX and DDC
DS1232 MicroMonitor Chip
DS1232 MicroMonitor Chip www.maxim-ic.com FEATURES Halts and restarts an out-of-control microprocessor Holds microprocessor in check during power transients Automatically restarts microprocessor after
IC S8745B- 21. Description. Features. Pin Assignment. Block Diagram 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR IC S8745B- 21 Description The ICS8745B-21 is a highly versatile 1:1 LVDS ICS Clock Generator and a member of the HiPerClockS HiPerClockS f family of
Triangular spread spectrum profile for maximum EMI reduction (Si50122-A2) 2.5 V, 3.3 V Power supply. (2.0 x 2.5 mm) down spread outputs
CRYSTAL-LESS PCI-EXPRESS GEN1 DUAL OUTPUT CLOCK GENERATOR Features Crystal-less clock generator with integrated CMEMS PCI-Express Gen 1 compliant Triangular spread spectrum profile for maximum EMI reduction
UNISONIC TECHNOLOGIES CO., LTD
UNINIC TECHNOLOGIES CO., LTD 20-BIT SERIAL TO PARALLEL CONVERTER DESCRIPTION The UTC LS3718 is a 20-bit serial to parallel converter utilizing CMOS Technology. It is incorporates control circuit, shift
IDTVP386. General Description. Features. Block Diagram DATASHEET ADVANCE INFORMATION 8/28-BIT LVDS RECEIVER FOR VIDEO
DATASHEET ADVANCE INFORMATION IDTVP386 General Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps