ECE 4510/5530 Microcontroller Applications Week 9

Transcription

1 ECE 45/553 Microcontroller Applications Week 9 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Lab 7 & 8 Elements & Project 2 Midterm Exam LCD Display for Calculator SPI, ADC/DAC and Temperature Measurement SPI and ADC ECE 25 2

3 ECE 45/553 3

4 Problem See Lab 5, Task 2 midterm example problem This waveform is designed to support a stepper motor full stepping driving operation, so the phases must be sequential and exactly equal to /2 of the total period. Assume that you are using a 24 MHz Eclock and that the PWM signal frequencies should all be 5 khz. Hints : If the period count were a perfect multiple of 2 or 4, such as 4, each channel would be turned on for a count of 2 to create a perfect 2/4 duty cycle. Hint 2: While PWM. and PWM.5 are left aligned, does PWM.3 and PWM.7 look like they might be center aligned on a count of 2? If so, how do the period and duty cycle values differ? ECE 4 45/553

5 Midterm Example Problem PWMPRCLK = x44; // Prescale A and B by 6 (.5 MHz) PWMCLK = x; // Select A and B clocks PWMCTL = PSWAI PFRZ; // All 8 bit registers, stop clocks for W or F PWMCAE = CAE2; // PWM.2 is center aligned PWMCAE &= ~(CAE4 CAE); // PWM. and PWM.4 are left aligned PWMPOL = PPOL; // PWM. is positive polarity PWMPOL &= ~(PPOL2 PPOL4); // PWM.2 and PWM.4 are negative polarity PWMPER = 5; // Left aligned 5 count period ( khz) PWMPER2 = 75; // Center aligned 2 x 75 count period ( khz) PWMPER4 = 5; // Left aligned 5 count period ( khz) PWMDTY = 5; // Positive 5/5 duty cycle PWMDTY2 = 5; // Centered Negative (755)/75 duty cycle PWMDTY4 = ; // Negative (5)/5 duty cycle PWME = (PWME PWME2 PWME4); //Enable channel, 2 and 4 ECE 45/553 5

6 Problem 2 See Lab 4, Task 4 for a single output compare operations. See Example 8.4 in the textbook and notes (Week5_) for a single output. The repeat period is to be 2 msec or 5 Hz with the sequential on times of 5 usec each. Compose the main() C program to initialize the ECT so that the sequence can be achieved and then wait in an infinite while loop. Four similar interrupt service routines are to be used to generate each of the on times for the four output compare timer channels. ECE 45/553 6

7 Example 8.4 Modified # include "mc9s2dp52.h" #define HiCnt 2 #define LoCnt 8 char HiorLo; void main (void) { asm( sei"); // disable interrupt globally timer_init(); asm("cli"); // enable interrupt globally timer5_start(); void timer_init(void) { TSCR = x9; // enable TCNT and fast timer flag clear TSCR2 = x3; // disable TCNT interrupt, set prescaler to 8 } TIOS = OC5; TFLG = xff; // enable OC5 function // clear all CxF flags while(); { asm( nop ); asm( nop ); } } interrupt void timer5_isr (void) { if(hiorlo){ TC5 += HiCnt; HiorLo = ; } else{ TC5 += LoCnt; HiorLo = ; } } void timer5_start(void) { extern char HiorLo; TCTL = xc; // set OC5 action to be pull high CFORC = x2; // Force pin action to high TFLG = xx2; // clear all C5F flags TCTL = x4; // set OC5 pin action to toggle TC5 = TCNT + HiCnt; // start an new OC5 operation HiorLo = ; // add LoCnt for the next OC5 operation TIE = x2; // enable OC5 interrupt locally } 7

8 Problem 3 (a) Initialization function: Use port H (PTH) for the control signals and port P (PTP) for the data signals. Provide a function call that sets data direction for all control signals and assumes that the data bus will be an input. Note: for bidirectional data buses, signals are not driven by any connected device until required. Therefore, at initialization the data bus should be an input. (b) Write LCD function: Based on the data write timing diagram, compose a Ccode function that pass an 8bit value to the function and execute a write. (c) Read LCD function: Based on the data read timing diagram, compose a Ccode function that reads an 8bit value and provide it as the return value for the function. ECE 45/553 8

9 LCD Read and Write Data Write Timing Table of Min/Max Required Times Time Item Symbol Min Max Unit Enable Cycle t CYCLE nsec Enable Pulse Width High Level t PWEH 45 nsec Enable Pulse Width Low Level t PWEL 35 nsec Address Setup Time (RS,R/Wn) t AS nsec Address Hold Time (RS,R/Wn) t AH nsec Data Setup Time t DSW nsec Data Hold Time t DHR 2 nsec Data Read Delay Time t DDR 9 nsec Data Read Timing ECE 45/553 9

10 LCD Operation The interface consists of three control signals and 8 parallel data bits. The control signals are register_select (RS), selecting control (low) or memory (high) registers, read/write_not (R/Wn), read or write operation select, and enable (E), the controller positive enable. The timing diagrams to perform a write and a read follow with times shown in the diagrams and table. Control: Port H (PTH), 3 pins RS Register Select = control=memory R/Wn Read/Write not = write =read E Enable = not enabled = enabled Data: Port P (PTP), 8 pins for 8 parallel bits ECE 45/553

11 LCD Initialization Port H has 3 outputs DDRH for 3 outputs. DDRP =? Initial condition of outputs. PTH =? RS don t care Read/Write not always in read when inactive Enable always when inactive DDRP for 8 bidirectional data lines Should be inputs whenever not actively requiring an output signal DDRP =? Is there anything else? ECE 45/553

12 Prototype Time Delays: Write ECE 45/553 t AS nsec min. 3 Eclock cycles t PWEH 45 nsec min Eclock cycles t AH nsec min. Eclock cycles t DSW nsec nom. 3 Eclock cycles t DHR 2 nsec min. Eclock cycles t DDR 9 nsec nom. 5 Eclock cycles t PWEL 35 nsec min 9Eclock cycles t CYCLE nsec min. 24 Eclock cycles ) RS & Wn 2) 3 nop 3) E Enable 4) 7 nop 5) DDRP, Data 6) 3 nop 7) E Disable 8) nop 9) all to steady state 2 (DDRP and R/Wn)

13 Prototype Time Delays: Read ECE 45/553 t AS nsec min. 3 Eclock cycles t PWEH 45 nsec min Eclock cycles t AH nsec min. Eclock cycles t DSW nsec nom. 3 Eclock cycles t DHR 2 nsec min. Eclock cycles t DDR 9 nsec nom. 5 Eclock cycles t PWEL 35 nsec min 9Eclock cycles t CYCLE nsec min. 24 Eclock cycles ) RS & read 2) 3 nop 3) E Enable 4) nop 5) PTP input 6) E Disable 7) nop 8) all to steady state 3

14 LCD INTERFACE ECE 45/553 4

15 LCD Display SSC2F6DLNW See Data Sheet Mechanical Electrical Timing Initialization sequence Controller IC Hitachi HD4478U Note: code in textbook is setup for a 4bit data, write only interface. Used on the Dragon demo board. p Textbook notes follow. ECE 45/553 5

16 A HD4478Based LCD Kit ( of 3) Display capability: 4 x 2 Uses the HD4478 as the controller as shown in Figure Pins DB7~DB are used to exchange data with the CPU. E input should be connected to one of the address decoder output or I/O pin. The RS signal selects instruction register () or data register (). The VEE signal allows the user to adjust the LCD contrast. The HD4478 can be configured to display line, 2line, and 4line information. The pin assignment for characterbased LCD module with less than and more than 8 characters are shown in Table 7.7 and 7.8. DB7 COM 6 LCDP (FRD769) DB E R/W RS V EE V CC V SS CONTROLLER LSI HD4478 SEG 4 4 SEG 6 SEGMENT DRIVER x 4 Figure 7.35 Block diagram of a HD4478based LCD kit

17 A HD4478Based LCD Kit (2 of 3) Table 7.7 Pin assignment for displays with less than 8 characters Pin No. symbol I/O Function VSS VCC VEE RS R/W E DB DB DB2 DB3 DB4 DB5 DB6 DB7 I I I I/O I/O I/O I/O I/O I/O I/O I/O Power supply (GND) Power supply (+5V) Contrast adjust = instruction input, = data input = write to LCD, = read from LCD enable signal data bus line data bus line data bus line 2 data bus line 3 data bus line 4 data bus line 5 data bus line 6 data bus line 7

18 Interfacing the HD4478 with the HCS2 One can treat the LCD kit as an I/O device and use an I/O port and several other I/O pins as control signals. The interface can be 4 bits or 8 bits. To read or write the LCD successfully, one must satisfy the timing requirements of the LCD. The timing diagrams for read and write are shown in Figure 7.37 and HCS2 MCU PK6 PK5 PK4 E R/W RS HD4478Ubased LCD Module V CC 5V 5V HCS2 MCU PK PK RS E HD4478Ubased LCD Module R/W V CC 5V 5V V EE V EE PH7...PH DB7..DB PK5...PK2 DB7..DB4 GND GND Figure 7.36a LCD interface example (8bit bus, used in SSE256) Figure 7.36b LCD interface example (4bit bus, used in Dragon2)

19 HD4478 Timing ( of 2) RS t AS t AH R/W PW EH t Ef E t Er t DDR t DHR DBDB7 Valid data t CYCLE Figure 7.37 HD4478U LCD controller read timing diagram RS t AS t AH R/W PW EH t Ef E t Er t DSW t H DBDB7 Valid data t CYCLE Figure 7.38 HD4478U LCD controller write timing diagram

20 HD4478 Timing ( of 2) Table 7.5 HD4478U bus timing parameters (2 MHz operation) Symbol Meaning Min Typ Max. Unit t CYCLE PW EH t Er, t Ef t AS t DDR t DSW t H t DHR t AH Enable cycle time Enable pulse width (high level) Enable rise and decay time Address setup time, RS, R/W, E Data delay time Data setup time Data hold time (write) Data hold time (read) Address hold time Procedure to send a command to the IR register Step Pull the RS and the E signals to low. Step 2 Pull the R/W signal to low. Step 3 Pull the E signal to high. Step 4 Output data to the output port attached to the LCD data bus. One needs to configure the I/O Port for output before writing data to the LCD kit. Step 5 Pull the E signal to low and make sure that the internal operation is complete ns ns ns ns ns ns ns ns ns

21 Registers of HD4478 The HD4478 has two 8bit user accessible registers: instruction register (IR) and data register (DR). To write data into display data RAM or character generator RAM, the MCU writes into the DR register. The address of the data RAM should be set up with a previous instruction. The DR register is also used for data storage when reading data from DDRAM or CGRAM. The HD4478 has a busy flag that is output from the DB7 pin. The HD4478 uses a 7bit address counter to keep track of the address of the next DDRAM or CGRAM location to be accessed. Table 7.2 Register selection RS R/W Operation IR write as an internal operation (display clear, etc) Read busy flag (DB7) and address counter (DB to DB6) DR write as an internal operation (DR to DDRAM or CGRAM) DR read as an internal operation (DDRAM or CGRAM to DR)

22 HD4478 Commands ( of 4) Table 7.9 HD4478U instruction set Code Instruction RS R/W B7 B6 B5 B4 B3 B2 B B Description Execution time Clear display Cursor home Entry mode set Display on/off control Cursor /display shift Function set Set CGRAM address Set DDRAM address Read busy flag and address counter Write CGRAM or DDRAM Read from CGRAM or DDRAM BF S/C R/L * DL N D F C * * I/D S B CGRAM address DDRAM address CGRAM/DDRAM address write data read data * * Clears display and returns cursor to the home position (address ). Returns cursor to home position (address ). Also returns display being shifted to the original position. DDRAM contents remain unchanged. Set cursor move direction (I/D), specifies to shift the display (S). These operations are performed during data read/write. Sets on/off of all display (D), cursor on/ off (C) and blink of cursor position character (B). Sets cursormove or display(s/c), shift direction (R/L). DDRAM contents remains unchanged. Sets interface data length (DL), number of display line (N) and character font (F). Sets the CGRAM address. CGRAM data is sent and received after this setting. Sets the DDRAM address. DDRAM data is sent and received after this setting. Reads busy flag (BF) indicating internal operation is being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction). Writes data to CGRAM or DDRAM. Reads data from CGRAM or DDRAM..64 ms.64 ms 4 s 4 s 4 s 4 s 4 s 4 s s 4 s 4 s

23 HD4478 Commands (2 of 4) Table 7. LCD instruction bit names Bit name I/D S D C B S/C R/L DL N F BF = decrement cursor position. = no display shift. = display off = cursor off = cursor blink off = move cursor = shift left = 4bit interface = /8 or / duty ( line) = 5x8 dots = can accept instruction Settings = increment cursor position = display shift = display on = cursor on = cursor blink on = shift display = shift right = 8bit interface = /6 duty (2 lines) = 5 x dots = internal operation in progress

24 HD4478 Commands (3 of 4) The HD4478 has a display data RAM (DDRAM) to store data to be displayed on the LCD. The address range of DDRAM for line, 2line, and 4line LCDs are shown in Table 7.a, 7.b, and 7.c. The HD4478 has a character generator ROM that can generates 5 8 or 5 character patterns from a 8bit code. The user can rewrite character patterns into the character generator RAM (CGRAM). Up to eight 5 8 patterns or four 5 patterns can be programmed. Table 7.a DDRAM address usage for a line LCD Display size Visible character positions DDRAM addresses * 8 * 6 * 2 * 24 * 32 * x..x7 x..xf x..x3 x..x7 x..xf x..x27

25 HD4478 Commands (4 of 4) Table 7.b DDRAM address usage for a 2line LCD Display size 2 * 6 2 * 2 2 * 24 2 * 32 2 * 4 Visible character positions DDRAM addresses x..xf + x4..x4f x..x3 + x4..x53 x..x7 + x4..x57 x..xf + x4..x5f x..x27 + x4..x67 Table 7.c DDRAM address usage for a 4line LCD Display size 4 * 6 4 * 2 4 * 4 Visible character positions on st controller and..39 on 2nd controller DDRAM addresses x..xf + x4..x4f + x4..x23 + x54..x63 x..x3 + x4..x53 + x4..x27 + x54..x67 x..x27 + x4..x67 on st controller and x..x27 + x4..x67 on 2nd controller

26 HD4478 Data Sheet This data sheet reads rather well to describe registers and the initialization procedure. ECE 45/553 26