An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal)

Size: px
Start display at page:

Download "An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal)"

Transcription

1

2

3 An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal) OR A Software-generated CALL (internally derived from the execution of an instruction or by some other internal event

4 An interrupt is used to cause a temporary halt in the execution of program. The meaning of interrupts is to break the sequence of operation. While the Microprocessor is executing a program, an interrupt breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, IRET returns the control back again to the main program. Interrupt processing is an alternative to polling.

5 The keyboard controller can hold only a single keystroke. Therefore, the keyboard controller must be freed before the next keystroke arrives. The keystroke is passed to the CPU by putting it in the keyboard buffer. So, the keyboard controller keeps on passing the keystroke input to the CPU, But how does the CPU attend to it? The CPU is not at the disposal of the keyboard controller; it is usually busy doing several other operations. So, we need some mechanism to indicate to the CPU that a keystroke has arrived. How is this done? There are two approaches to making sure that the CPU pays attention:

6 The CPU executes other program, as soon as a key is pressed, the Keyboard generates an interrupt. The CPU will response to the interrupt read the data and after that returns to the original program. So by proper use of interrupt, the CPU can serve many devices at the same time

7 The Purpose of Interrupts...

8 Interrupts are useful when interfacing I/O devices at relatively low data transfer rates, such as keyboard inputs. Interrupt processing allows the processor to execute other software while the keyboard operator is thinking about what to type next. When a key is pressed, the keyboard encoder debounces the switch and puts out one pulse that interrupts the microprocessor.

9

10

11 TYPES OF INTERRUPT SOFTWARE INTERRUPTS: There are instructions in 8086 which cause an interrupt. INT instructions with type number specified. INT 3, Break Point Interrupt instruction. INTO, Interrupt on overflow instruction. HARDWARE INTERRUPTS: The primary sources of interrupts, however, are the PCs timer chip, keyboard, serial ports, parallel ports, disk drives, CMOS real-time clock, mouse, sound cards, and other peripheral devices.

12 TYPE 0 Interrupt The divide error : whenever the results from a division overflows or an attempt is made to divide by zero.

13

14 Type 2 The non-maskable interrupt occurs when a logic 1 is placed on the NMI input pin to the microprocessor. nonmaskable it cannot be disabled

15 Type 3 A special one-byte instruction (INT 3) that uses this vector to access its interrupt-service procedure. It often used to store a breakpoint in a program for debugging

16 TYPE 4 Overflow is a special vector used with the INTO instruction. The INTO instruction interrupts the program if an overflow condition exists.

17 TYPE 5 The BOUND instruction compares a register with boundaries stored in the memory. If the contents of the register are greater than or equal to the first word in memory and less than or equal to the second word, no interrupt occurs because the contents of the register are within bounds. if the contents of the register are out of bounds, a type 5 interrupt ensues as reflected by the overflow flag (OF)

18

19 Type 7 The coprocessor not available interrupt occurs when a coprocessor is not found, as dictated by the machine status word (MSW or CR0). If an ESC or WAIT instruction executes and no coprocessor is found, a type 7 exception or interrupt occurs

20 Type 8 A double fault interrupt is activated when two separate interrupts occur during the same instruction.

21 Type 9 The coprocessor segment overrun occurs if the ESC instruction memory operand extends beyond offset address FFFFH in real mode.

22 Type 10 An invalid task state segment interrupt occurs in the protected mode if the TSS is invalid because the segment limit field is not 002BH or higher. Type 11 The segment not present interrupt occurs when the protected mode P bit (P = 0) in a descriptor indicates that the segment is not present or not valid.

23 Type 12 A stack segment overrun occurs if the stack segment is not present (P = 0) in the protected mode or if the limit of the stack segment is exceeded.

24 Type 13 The general protection fault occurs for most protection violations in Core2 in protected mode system. These errors occur in Windows as general protection faults. A list of these protection violations follows.

25 Type 14 Page fault interrupts occur for any page fault memory or code access in 80386, 80486, and Pentium Core2 processors. Type 16 Coprocessor error takes effect when a coprocessor error (ERROR = 0) occurs for ESCape or WAIT instructions for 80386, 80486, and Pentium Core2 only.

26 Type 17 Alignment checks indicate word and double word data are addressed at an odd memory location (or incorrect location, in the case of a double word). interrupt is active in and Pentium Core2

27 Type 18 A machine check activates a system memory management mode interrupt in Pentium Core2.

An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal)

An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal) An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal) OR A Software-generated CALL (internally derived from the execution of an instruction or by some other internal

More information

The Purpose of Interrupt

The Purpose of Interrupt Interrupts 3 Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is a hardware-initiated

More information

BASIC INTERRUPT PROCESSING

BASIC INTERRUPT PROCESSING Interrupts BASIC INTERRUPT PROCESSING This section discusses the function of an interrupt in a microprocessor-based system. Structure and features of interrupts available to Intel microprocessors. The

More information

eaymanelshenawy.wordpress.com

eaymanelshenawy.wordpress.com Lectures on Memory Interface Designed and Presented by Dr. Ayman Elshenawy Elsefy Dept. of Systems & Computer Eng.. Al-Azhar University Email : eaymanelshenawy@yahoo.com eaymanelshenawy.wordpress.com Chapter

More information

Chapter 12: INTERRUPTS

Chapter 12: INTERRUPTS Chapter 12: INTERRUPTS 12 1 BASIC INTERRUPT PROCESSING This section discusses the function of an interrupt in a microprocessor-based system. Structure and features of interrupts available to Intel microprocessors.

More information

For more notes of DAE

For more notes of DAE Created by ARSLAN AHMED SHAAD ( 1163135 ) AND MUHMMAD BILAL ( 1163122 ) VISIT : www.vbforstudent.com Also visit : www.techo786.wordpress.com For more notes of DAE CHAPTER # 8 INTERRUPTS COURSE OUTLINE

More information

7/19/2013. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to: Chapter Objectives 12 1 BASIC INTERRUPT PROCESSING

7/19/2013. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to: Chapter Objectives 12 1 BASIC INTERRUPT PROCESSING Chapter 12: Interrupts Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is

More information

Chapter 12: Interrupts

Chapter 12: Interrupts Chapter 12: Interrupts Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is

More information

ECE 485/585 Microprocessor System Design

ECE 485/585 Microprocessor System Design Microprocessor System Design Lecture 3: Polling and Interrupts Programmed I/O and DMA Interrupts Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science

More information

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013

CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 TOPICS TODAY I/O Architectures Interrupts Exceptions FETCH EXECUTE CYCLE 1.7 The von Neumann Model This is a general

More information

2.5 Address Space. The IBM 6x86 CPU can directly address 64 KBytes of I/O space and 4 GBytes of physical memory (Figure 2-24).

2.5 Address Space. The IBM 6x86 CPU can directly address 64 KBytes of I/O space and 4 GBytes of physical memory (Figure 2-24). Address Space 2.5 Address Space The IBM 6x86 CPU can directly address 64 KBytes of I/O space and 4 GBytes of physical memory (Figure 2-24). Memory Address Space. Access can be made to memory addresses

More information

UMBC. contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. contain displacement added to IP.

UMBC. contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. contain displacement added to IP. Procedures: CALL: Pushes the address of the instruction following the CALL instruction onto the stack. RET: Pops the address. SUM PROC NEAR USES BX CX DX ADD AX, BX ADD AX, CX MOV AX, DX RET SUM ENDP NEAR

More information

The K Project. Interrupt and Exception Handling. LSE Team. May 14, 2018 EPITA. The K Project. LSE Team. Introduction. Interrupt Descriptor Table

The K Project. Interrupt and Exception Handling. LSE Team. May 14, 2018 EPITA. The K Project. LSE Team. Introduction. Interrupt Descriptor Table and Exception Handling EPITA May 14, 2018 (EPITA) May 14, 2018 1 / 37 and Exception Handling Exception : Synchronous with program execution (e.g. division by zero, accessing an invalid address) : Asynchronous

More information

8086 Interrupts and Interrupt Responses:

8086 Interrupts and Interrupt Responses: UNIT-III PART -A INTERRUPTS AND PROGRAMMABLE INTERRUPT CONTROLLERS Contents at a glance: 8086 Interrupts and Interrupt Responses Introduction to DOS and BIOS interrupts 8259A Priority Interrupt Controller

More information

MICROPROCESSOR MEMORY ORGANIZATION

MICROPROCESSOR MEMORY ORGANIZATION MICROPROCESSOR MEMORY ORGANIZATION 1 3.1 Introduction 3.2 Main memory 3.3 Microprocessor on-chip memory management unit and cache 2 A memory unit is an integral part of any microcomputer, and its primary

More information

Mechanisms for entering the system

Mechanisms for entering the system Mechanisms for entering the system Yolanda Becerra Fontal Juan José Costa Prats Facultat d'informàtica de Barcelona (FIB) Universitat Politècnica de Catalunya (UPC) BarcelonaTech 2017-2018 QP Content Introduction

More information

Systems Programming and Computer Architecture ( ) Timothy Roscoe

Systems Programming and Computer Architecture ( ) Timothy Roscoe Systems Group Department of Computer Science ETH Zürich Systems Programming and Computer Architecture (252-0061-00) Timothy Roscoe Herbstsemester 2016 AS 2016 Exceptions 1 17: Exceptions Computer Architecture

More information

+ Overview. Projects: Developing an OS Kernel for x86. ! Handling Intel Processor Exceptions: the Interrupt Descriptor Table (IDT)

+ Overview. Projects: Developing an OS Kernel for x86. ! Handling Intel Processor Exceptions: the Interrupt Descriptor Table (IDT) + Projects: Developing an OS Kernel for x86 Low-Level x86 Programming: Exceptions, Interrupts, and Timers + Overview! Handling Intel Processor Exceptions: the Interrupt Descriptor Table (IDT)! Handling

More information

These three counters can be programmed for either binary or BCD count.

These three counters can be programmed for either binary or BCD count. S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers.

More information

PC Interrupt Structure and 8259 DMA Controllers

PC Interrupt Structure and 8259 DMA Controllers ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 PC Interrupt Structure and 8259 DMA Controllers This lecture covers the use of interrupts and the vectored interrupt

More information

The control of I/O devices is a major concern for OS designers

The control of I/O devices is a major concern for OS designers Lecture Overview I/O devices I/O hardware Interrupts Direct memory access Device dimensions Device drivers Kernel I/O subsystem Operating Systems - June 26, 2001 I/O Device Issues The control of I/O devices

More information

Interrupts. Chapter 20 S. Dandamudi. Outline. Exceptions

Interrupts. Chapter 20 S. Dandamudi. Outline. Exceptions Interrupts Chapter 20 S. Dandamudi Outline What are interrupts? Types of interrupts Software interrupts Hardware interrupts Exceptions Interrupt processing Protected mode Real mode Software interrupts

More information

Computer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2.

Computer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2. BASIC ELEMENTS Simplified view: Processor Slide 1 Computer System Overview Operating Systems Slide 3 Main Memory referred to as real memory or primary memory volatile modules 2004/S2 secondary memory devices

More information

Computer System Overview

Computer System Overview Computer System Overview Operating Systems 2005/S2 1 What are the objectives of an Operating System? 2 What are the objectives of an Operating System? convenience & abstraction the OS should facilitate

More information

CS609 Final Term Solved MCQs with References Without Repetitions 14/02/2013

CS609 Final Term Solved MCQs with References Without Repetitions 14/02/2013 1 CS609 Final Term Solved MCQs with References Without Repetitions 14/02/2013 In BPB, root directory is saved in. (BIOS parameter block) Cluster#0 Cluster#1 (Ref) Cluster#2 Cluster#3 In NTFS, total sizes

More information

SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013)

SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013) SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE EC6504 MICROPROCESSOR AND MICROCONTROLLER (REGULATION 2013) UNIT I THE 8086 MICROPROCESSOR PART A (2 MARKS) 1. What are the functional

More information

Reset, Interrupts, Exceptions, and Break ECE 3534

Reset, Interrupts, Exceptions, and Break ECE 3534 Reset, Interrupts, Exceptions, and Break ECE 3534 1 Reset, Interrupts, Exceptions, Break These topics are closely related Both software and hardware aspects of a processor are involved On the MicroBlaze,

More information

Phoenix Technologies, Ltd.

Phoenix Technologies, Ltd. Phoenix Technologies, Ltd. AwardBIOS Version 4.51PG Post Codes & Error Messages Table of Contents POST Codes - 2 Error Messages - 7 ----------------------------------------------- Proprietary Notice and

More information

COS 318: Operating Systems

COS 318: Operating Systems COS 318: Operating Systems OS Structures and System Calls Jaswinder Pal Singh Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) Outline Protection mechanisms

More information

1. state the priority of interrupts of Draw and explain MSW format of List salient features of

1. state the priority of interrupts of Draw and explain MSW format of List salient features of Q.1) 1. state the priority of interrupts of 80286. Ans- 1. Instruction exceptions 2. Single step 3. NMI 4. Processor extension segment overrun 5. INTR 6. INT 2. Draw and explain MSW format of 80286. Ans-

More information

MP Assignment IV. 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals.

MP Assignment IV. 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals. MP Assignment IV 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals. The 80386 has a 32-bit data bus and four banks of memory. A logical address

More information

6/17/2011. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to:

6/17/2011. Introduction. Chapter Objectives Upon completion of this chapter, you will be able to: Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Introduction This chapter presents the microprocessor

More information

Chapter 2: The Microprocessor and its Architecture

Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Chapter 2: The Microprocessor and its Architecture Introduction This chapter presents the microprocessor

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 16 Ch.7 The 80386 and 80486 Microprocessors 21-Apr-15 1 System Descriptors The system descriptor defines information about the system

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 15 Ch.7 The 80386 and 80486 Microprocessors 21-Apr-15 1 Chapter Objectives Contrast the 80386 and 80486 microprocessors with earlier

More information

COS 318: Operating Systems

COS 318: Operating Systems COS 318: Operating Systems OS Structures and System Calls Prof. Margaret Martonosi Computer Science Department Princeton University http://www.cs.princeton.edu/courses/archive/fall11/cos318/ Outline Protection

More information

8086 PIN Diagram Signals with common functions in both Modes: The following signal description is common for both the minimum and maximum modes.

8086 PIN Diagram Signals with common functions in both Modes: The following signal description is common for both the minimum and maximum modes. UNIT II - 8086 SYSTEM BUS STRUCTURE 8086 signals Basic configurations System bus timing System design using 8086 IO programming Introduction to Multiprogramming System Bus Structure Multiprocessor configurations

More information

9/25/ Software & Hardware Architecture

9/25/ Software & Hardware Architecture 8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called

More information

INTERRUPTS in microprocessor systems

INTERRUPTS in microprocessor systems INTERRUPTS in microprocessor systems Microcontroller Power Supply clock fx (Central Proccesor Unit) CPU Reset Hardware Interrupts system IRQ Internal address bus Internal data bus Internal control bus

More information

CSC227: Operating Systems Fall Chapter 1 INTERRUPTS. Dr. Soha S. Zaghloul

CSC227: Operating Systems Fall Chapter 1 INTERRUPTS. Dr. Soha S. Zaghloul CSC227: Operating Systems Fall 2016 Chapter 1 INTERRUPTS Dr. Soha S. Zaghloul LAYOUT 1.3 Devices Controlling Techniques 1.3.1 Polling 1.3.2 Interrupts H/W Interrupts Interrupt Controller Process State

More information

Intel386 TM DX MICROPROCESSOR SPECIFICATION UPDATE

Intel386 TM DX MICROPROCESSOR SPECIFICATION UPDATE Intel386 TM DX MICROPROCESSOR SPECIFICATION UPDATE Release Date: July, 1996 Order Number 272874-001 The Intel386 TM DX Microprocessor may contain design defects or errors known as errata. Characterized

More information

Description of the Simulator

Description of the Simulator Description of the Simulator The simulator includes a small sub-set of the full instruction set normally found with this style of processor. It includes advanced instructions such as CALL, RET, INT and

More information

MICROPROCESSOR ALL IN ONE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)

MICROPROCESSOR ALL IN ONE. Prof. P. C. Patil UOP S.E.COMP (SEM-II) MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 ALL IN ONE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Architecture of 80386 2 ARCHITECTURE

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 13 Ch.6 The 80186, 80188, and 80286 Microprocessors 21-Apr-15 1 Chapter Objectives Describe the hardware and software enhancements

More information

Intel386 DX PROCESSOR SPECIFICATION UPDATE

Intel386 DX PROCESSOR SPECIFICATION UPDATE Intel386 DX PROCESSOR SPECIFICATION UPDATE Release Date: August, 2004 Order Number: 272874-003 The Intel386 DX processor may contain design defects or errors known as errata. Characterized errata that

More information

CPU Structure and Function

CPU Structure and Function Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com http://www.yildiz.edu.tr/~naydin CPU Structure and Function 1 2 CPU Structure Registers

More information

UNIT- 5. Chapter 12 Processor Structure and Function

UNIT- 5. Chapter 12 Processor Structure and Function UNIT- 5 Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers

More information

MPLAB X Debugging Techniques

MPLAB X Debugging Techniques TLS0102-004 MPLAB X Debugging Techniques Exception Conditions Author: Rob Ostapiuk, Stu Chandler Microchip Technology Exception Events Causes and Tools for Resolving Them Exception Events Definition An

More information

MATH CO-PROCESSOR 8087

MATH CO-PROCESSOR 8087 MATH CO-PROCESSOR 8087 1 Gursharan Singh Tatla professorgstatla@gmail.com INTRODUCTION 8087 was the first math coprocessor for 16-bit processors designed by Intel. It was built to pair with 8086 and 8088.

More information

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture

Last 2 Classes: Introduction to Operating Systems & C++ tutorial. Today: OS and Computer Architecture Last 2 Classes: Introduction to Operating Systems & C++ tutorial User apps OS Virtual machine interface hardware physical machine interface An operating system is the interface between the user and the

More information

FIFTH SEMESTER B.TECH DEGREE EXAMINATION MODEL TEST QUESTION PAPER, NOVEMBER CS 305: Microprocessor and Microcontrollers PART A

FIFTH SEMESTER B.TECH DEGREE EXAMINATION MODEL TEST QUESTION PAPER, NOVEMBER CS 305: Microprocessor and Microcontrollers PART A Reg No Name FIFTH SEMESTER B.TECH DEGREE EXAMINATION MODEL TEST QUESTION PAPER, NOVEMBER 2017 CS 305: Microprocessor and Microcontrollers Max. Marks: 100 Duration: 3 Hours PART A Answer all questions.

More information

CS 3803 Lab 6 Interrupts Assigned 2/25/10 Point Value: 30

CS 3803 Lab 6 Interrupts Assigned 2/25/10 Point Value: 30 CS 3803 Lab 6 Interrupts Assigned 2/25/10 Point Value: 30 Purpose Interrupts are crucial to an operating system. They are used to get status and data from the timer, keyboard, and disk drives to mention

More information

EC-333 Microprocessor and Interfacing Techniques

EC-333 Microprocessor and Interfacing Techniques EC-333 Microprocessor and Interfacing Techniques Lecture 3 The Microprocessor and its Architecture Dr Hashim Ali Fall - 2018 Department of Computer Science and Engineering HITEC University Taxila Slides

More information

Lecture (02) The Microprocessor and Its Architecture By: Dr. Ahmed ElShafee

Lecture (02) The Microprocessor and Its Architecture By: Dr. Ahmed ElShafee Lecture (02) The Microprocessor and Its Architecture By: Dr. Ahmed ElShafee ١ INTERNAL MICROPROCESSOR ARCHITECTURE Before a program is written or instruction investigated, internal configuration of the

More information

Process Description and Control. Chapter 3

Process Description and Control. Chapter 3 Process Description and Control Chapter 3 Contents Process states Process description Process control Unix process management Process From processor s point of view execute instruction dictated by program

More information

Troubleshooting & Repair

Troubleshooting & Repair Chapter Troubleshooting & Repair 6.1 Introduction This chapter provides the most common problem encountered with the M785 notebook computer and some troubleshooting means. Some of the common problems are:

More information

PART B UNIT II PART A

PART B UNIT II PART A SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (Deemed University) DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING QUESTION BANK SUB : Microprocessor/CS201 YEAR/SEM : II/III UNIT I PART - A 1. Differentiate accumulator

More information

MICROPROCESSOR MICROPROCESSOR ARCHITECTURE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)

MICROPROCESSOR MICROPROCESSOR ARCHITECTURE. Prof. P. C. Patil UOP S.E.COMP (SEM-II) MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 MICROPROCESSOR ARCHITECTURE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Introduction

More information

MICROPROCESSOR MICROPROCESSOR ARCHITECTURE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)

MICROPROCESSOR MICROPROCESSOR ARCHITECTURE. Prof. P. C. Patil UOP S.E.COMP (SEM-II) MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 MICROPROCESSOR ARCHITECTURE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Introduction

More information

Interrupt/Timer/DMA 1

Interrupt/Timer/DMA 1 Interrupt/Timer/DMA 1 Exception An exception is any condition that needs to halt normal execution of the instructions Examples - Reset - HWI - SWI 2 Interrupt Hardware interrupt Software interrupt Trap

More information

Operating Systems 2010/2011

Operating Systems 2010/2011 Operating Systems 2010/2011 Input/Output Systems part 1 (ch13) Shudong Chen 1 Objectives Discuss the principles of I/O hardware and its complexity Explore the structure of an operating system s I/O subsystem

More information

CPEG300 Embedded System Design. Lecture 6 Interrupt System

CPEG300 Embedded System Design. Lecture 6 Interrupt System CPEG300 Embedded System Design Lecture 6 Interrupt System Hamad Bin Khalifa University, Spring 2018 Correction Lecture 3, page 18: Only direct addressing mode is allowed for pushing or popping the stack:

More information

CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING

CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING CHATER 6 INTERRUT AND EXCETION HANDLING This chapter describes the interrupt and exception-handling mechanism when operating in protected mode on an I ntel 64 or I A-32 processor. Most of the information

More information

CS 550 Operating Systems Spring Interrupt

CS 550 Operating Systems Spring Interrupt CS 550 Operating Systems Spring 2019 Interrupt 1 Revisit -- Process MAX Stack Function Call Arguments, Return Address, Return Values Kernel data segment Kernel text segment Stack fork() exec() Heap Data

More information

Lecture 13: I/O I/O. Interrupts. How?

Lecture 13: I/O I/O. Interrupts. How? Lecture 13: I/O I/O Interrupts MS-DOS Function Calls Input,Output, File I/O Video Keyboard Getting data into your program: define it in the data area use immediate operands Very limiting Most programs

More information

BASIC OPERATIONS. Managing System Resources

BASIC OPERATIONS. Managing System Resources 48 PART 2 BASIC OPERATIONS C H A P T E R 5 Managing System Resources CHAPTER 5 MANAGING SYSTEM RESOURCES 49 THE part of Windows Vista that you see the Vista desktop is just part of the operating system.

More information

Moodle WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics

Moodle WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics Moodle 4 WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics Advanced Microprocessors and Introduction to Microcontroller Moodle developed By Dr. S. R. Kumbhar Department of Electronics Willingdon

More information

Chapter 12. CPU Structure and Function. Yonsei University

Chapter 12. CPU Structure and Function. Yonsei University Chapter 12 CPU Structure and Function Contents Processor organization Register organization Instruction cycle Instruction pipelining The Pentium processor The PowerPC processor 12-2 CPU Structures Processor

More information

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss Grundlagen Microcontroller Interrupts Günther Gridling Bettina Weiss 1 Interrupts Lecture Overview Definition Sources ISR Priorities & Nesting 2 Definition Interrupt: reaction to (asynchronous) external

More information

PROTECTION CHAPTER 4 PROTECTION

PROTECTION CHAPTER 4 PROTECTION Protection 4 CHAPTER 4 PROTECTION In protected mode, the Intel Architecture provides a protection mechanism that operates at both the segment level and the page level. This protection mechanism provides

More information

ECE 372 Microcontroller Design Parallel IO Ports - Interrupts. ECE 372 Microcontroller Design Parallel IO Ports - Interrupts

ECE 372 Microcontroller Design Parallel IO Ports - Interrupts. ECE 372 Microcontroller Design Parallel IO Ports - Interrupts Interrupts An interrupt can be compared with a phone call interrupting your task which you will resume when the call is finished You can mask an interrupt just as you can decide not to answer any phone

More information

EEM336 Microprocessors I. The Microprocessor and Its Architecture

EEM336 Microprocessors I. The Microprocessor and Its Architecture EEM336 Microprocessors I The Microprocessor and Its Architecture Introduction This chapter presents the microprocessor as a programmable device by first looking at its internal programming model and then

More information

Topics. Interfacing chips

Topics. Interfacing chips 8086 Interfacing ICs 2 Topics Interfacing chips Programmable Communication Interface PCI (8251) Programmable Interval Timer (8253) Programmable Peripheral Interfacing - PPI (8255) Programmable DMA controller

More information

OPERATING SYSTEMS CS136

OPERATING SYSTEMS CS136 OPERATING SYSTEMS CS136 Jialiang LU Jialiang.lu@sjtu.edu.cn Based on Lecture Notes of Tanenbaum, Modern Operating Systems 3 e, 1 Chapter 5 INPUT/OUTPUT 2 Overview o OS controls I/O devices => o Issue commands,

More information

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5.

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5. DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6502- MICROPROCESSORS AND MICROCONTROLLERS UNIT I: 8085 PROCESSOR PART A 1. What is the need for ALE signal in

More information

Overview. M. Krishna Kumar MM/M4/LU10/V1/2004 1

Overview. M. Krishna Kumar MM/M4/LU10/V1/2004 1 Overview Each processor in the 80x86 family has a corresponding coprocessor with which it is compatible Math Coprocessor is known as NPX,NDP,FUP. Numeric processor extension (NPX), Numeric data processor

More information

EEL 4744C: Microprocessor Applications. Lecture 7. Part 1. Interrupt. Dr. Tao Li 1

EEL 4744C: Microprocessor Applications. Lecture 7. Part 1. Interrupt. Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 7 Part 1 Interrupt Dr. Tao Li 1 M&M: Chapter 8 Or Reading Assignment Software and Hardware Engineering (new version): Chapter 12 Dr. Tao Li 2 Interrupt An

More information

Reading Assignment. Interrupt. Interrupt. Interrupt. EEL 4744C: Microprocessor Applications. Lecture 7. Part 1

Reading Assignment. Interrupt. Interrupt. Interrupt. EEL 4744C: Microprocessor Applications. Lecture 7. Part 1 Reading Assignment EEL 4744C: Microprocessor Applications Lecture 7 M&M: Chapter 8 Or Software and Hardware Engineering (new version): Chapter 12 Part 1 Interrupt Dr. Tao Li 1 Dr. Tao Li 2 Interrupt An

More information

EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers UNIT-I

EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers UNIT-I EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers 1. Define microprocessors? UNIT-I A semiconductor device(integrated circuit) manufactured by using the LSI technique. It includes

More information

EC6504 MICROPROCESSOR AND MICROCONTROLLER

EC6504 MICROPROCESSOR AND MICROCONTROLLER UNIT I THE 8086 MICROPROCESSOR 1. What do you mean by Addressing modes? (May/June 2014) The different ways that a microprocessor can access data are referred to as addressing modes. 2. What is meant by

More information

EC 6504 Microprocessor and Microcontroller. Unit II System Bus Structure

EC 6504 Microprocessor and Microcontroller. Unit II System Bus Structure EC 6504 Microprocessor and Microcontroller Unit II 8086 System Bus Structure Syllabus: 8086 Signals Basic Configurations System bus timing System Design using 8086 IO Programming Introduction to multiprogramming

More information

Introduction to Embedded Systems

Introduction to Embedded Systems Stefan Kowalewski, 4. November 25 Introduction to Embedded Systems Part 2: Microcontrollers. Basics 2. Structure/elements 3. Digital I/O 4. Interrupts 5. Timers/Counters Introduction to Embedded Systems

More information

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU Structure and Function Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition CPU must: CPU Function Fetch instructions Interpret/decode instructions Fetch data Process data

More information

Introduction to general architectures of 8 and 16 bit micro-processor and micro-controllers

Introduction to general architectures of 8 and 16 bit micro-processor and micro-controllers Introduction to general architectures of 8 and 16 bit micro-processor and micro-controllers A microcontroller is a microprocessor with inbuilt peripherals.a microcontroller can also be compared with a

More information

Chapter 8 PC Peripheral Chips - Pt 3 Interrupts

Chapter 8 PC Peripheral Chips - Pt 3 Interrupts Chapter 8 PC Peripheral Chips - Pt 3 Interrupts PC Architecture for Technicians: Level-1 Systems Manufacturing Training and Employee Development Copyright 1996 Intel Corp. Ch 8 - Page 1 OBJECTIVES: AT

More information

Process Description and Control. Major Requirements of an Operating System

Process Description and Control. Major Requirements of an Operating System Process Description and Control Chapter 3 1 Major Requirements of an Operating System Interleave the execution of several processes to maximize processor utilization while providing reasonable response

More information

Major Requirements of an Operating System Process Description and Control

Major Requirements of an Operating System Process Description and Control Major Requirements of an Operating System Process Description and Control Chapter 3 Interleave the execution of several processes to maximize processor utilization while providing reasonable response time

More information

QUESTION BANK CS2252 MICROPROCESSOR AND MICROCONTROLLERS

QUESTION BANK CS2252 MICROPROCESSOR AND MICROCONTROLLERS FATIMA MICHAEL COLLEGE OF ENGINEERING & TECHNOLOGY Senkottai Village, Madurai Sivagangai Main Road, Madurai -625 020 QUESTION BANK CS2252 MICROPROCESSOR AND MICROCONTROLLERS UNIT 1 - THE 8085 AND 8086

More information

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.

1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085. (1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic

More information

Processes. Process Management Chapter 3. When does a process gets created? When does a process gets terminated?

Processes. Process Management Chapter 3. When does a process gets created? When does a process gets terminated? Processes Process Management Chapter 3 1 A process is a program in a state of execution (created but not terminated) Program is a passive entity one on your disk (survivor.class, kelly.out, ) Process is

More information

W4118: interrupt and system call. Junfeng Yang

W4118: interrupt and system call. Junfeng Yang W4118: interrupt and system call Junfeng Yang Outline Motivation for protection Interrupt System call 2 Need for protection Kernel privileged, cannot trust user processes User processes may be malicious

More information

Process Context & Interrupts. New process can mess up information in old process. (i.e. what if they both use the same register?)

Process Context & Interrupts. New process can mess up information in old process. (i.e. what if they both use the same register?) 1 Process Context 1.1 What is context? A process is sometimes called a task, subroutine or program. Process context is all the information that the process needs to keep track of its state. Registers Temporary

More information

General Purpose Programmable Peripheral Devices. Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar

General Purpose Programmable Peripheral Devices. Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar Chapter 15 General Purpose Programmable Peripheral Devices by Rahul Patel, Assistant Professor, EC Dept., Sankalchand Patel College of Engg.,Visnagar Microprocessor & Interfacing (140701) Rahul Patel 1

More information

8086 Hardware Specification

8086 Hardware Specification Content: Segment 5 8086 Hardware Specification 8086 Modes of operation. Pin diagram and pin function of 8086. 8284A Clock generator operation and pin functions. Prepared By: Mohammed Abdul Kader Lecturer,

More information

IA32 Intel 32-bit Architecture

IA32 Intel 32-bit Architecture 1 2 IA32 Intel 32-bit Architecture Intel 32-bit Architecture (IA32) 32-bit machine CISC: 32-bit internal and external data bus 32-bit external address bus 8086 general registers extended to 32 bit width

More information

UNIT II SYSTEM BUS STRUCTURE 1. Differentiate between minimum and maximum mode 2. Give any four pin definitions for the minimum mode. 3. What are the pins that are used to indicate the type of transfer

More information

Chapter 2 COMPUTER SYSTEM HARDWARE

Chapter 2 COMPUTER SYSTEM HARDWARE Chapter 2 COMPUTER SYSTEM HARDWARE A digital computer system consists of hardware and software. The hardware consists of the physical components of the system, whereas the software is the collection of

More information

Operating Systems CMPSCI 377 Spring Mark Corner University of Massachusetts Amherst

Operating Systems CMPSCI 377 Spring Mark Corner University of Massachusetts Amherst Operating Systems CMPSCI 377 Spring 2017 Mark Corner University of Massachusetts Amherst Last Class: Intro to OS An operating system is the interface between the user and the architecture. User-level Applications

More information

Microprocessors & Interfacing

Microprocessors & Interfacing Lecture Overview Microprocessors & Interfacing Interrupts (I) Lecturer : Dr. Annie Guo Introduction to Interrupts Interrupt system specifications Multiple sources of interrupts Interrupt priorities Interrupts

More information

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1 Interrupts (I) Lecturer: Sri Notes by Annie Guo Week8 1 Lecture overview Introduction to Interrupts Interrupt system specifications Multiple Sources of Interrupts Interrupt Priorities Interrupts in AVR

More information